mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-18 13:55:18 +03:00
Updated to correctly support STM32FX411 device. Removed HSE bypass
references. Minor cleanup.
This commit is contained in:
Patrick Johnson
parent
06239d2a0d
commit
a0b3afae31
1 changed files with 27 additions and 160 deletions
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@ -346,21 +346,6 @@ uint32_t hse_value = HSE_VALUE;
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/* #define DATA_IN_ExtSDRAM */
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#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
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#if defined(STM32F410xx) || defined(STM32F411xE)
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/*!< Uncomment the following line if you need to clock the STM32F410xx/STM32F411xE by HSE Bypass
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through STLINK MCO pin of STM32F103 microcontroller. The frequency cannot be changed
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and is fixed at 8 MHz.
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Hardware configuration needed for Nucleo Board:
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– SB54, SB55 OFF
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– R35 removed
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– SB16, SB50 ON */
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/* #define USE_HSE_BYPASS */
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#if defined(USE_HSE_BYPASS)
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#define HSE_BYPASS_INPUT_FREQUENCY 8000000
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#endif /* USE_HSE_BYPASS */
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#endif /* STM32F410xx || STM32F411xE */
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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@ -379,17 +364,10 @@ uint32_t hse_value = HSE_VALUE;
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#elif defined (STM32F446xx)
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#define PLL_M 8
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#elif defined (STM32F410xx) || defined (STM32F411xE)
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#if defined(USE_HSE_BYPASS)
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#define PLL_M 8
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#else /* !USE_HSE_BYPASS */
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#define PLL_M 8
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#endif /* USE_HSE_BYPASS */
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#else
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#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */
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/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
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#define PLL_Q 7
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#if defined(STM32F446xx)
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/* PLL division factor for I2S, SAI, SYSTEM and SPDIF: Clock = PLL_VCO / PLLR */
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#define PLL_R 7
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@ -399,24 +377,32 @@ uint32_t hse_value = HSE_VALUE;
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#define PLL_N 360
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/* SYSCLK = PLL_VCO / PLL_P */
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#define PLL_P 2
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/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
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#define PLL_Q 7
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#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
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#if defined (STM32F40_41xxx)
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#define PLL_N 336
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/* SYSCLK = PLL_VCO / PLL_P */
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#define PLL_P 2
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/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
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#define PLL_Q 7
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#endif /* STM32F40_41xxx */
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#if defined(STM32F401xx)
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#define PLL_N 336
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/* SYSCLK = PLL_VCO / PLL_P */
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#define PLL_P 4
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/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
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#define PLL_Q 7
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#endif /* STM32F401xx */
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#if defined(STM32F410xx) || defined(STM32F411xE)
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#define PLL_N 400
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#define PLL_N 384
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/* SYSCLK = PLL_VCO / PLL_P */
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#define PLL_P 4
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/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
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#define PLL_Q 8
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#endif /* STM32F410xx || STM32F411xE */
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/******************************************************************************/
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@ -450,7 +436,7 @@ uint32_t hse_value = HSE_VALUE;
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#endif /* STM32F401xx */
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#if defined(STM32F410xx) || defined(STM32F411xE)
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uint32_t SystemCoreClock = 100000000;
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uint32_t SystemCoreClock = 96000000;
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#endif /* STM32F410xx || STM32F401xE */
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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@ -585,7 +571,6 @@ void SystemCoreClockUpdate(void)
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
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if (pllsource != 0)
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{
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/* HSE used as PLL clock source */
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@ -596,21 +581,7 @@ void SystemCoreClockUpdate(void)
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/* HSI used as PLL clock source */
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pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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#elif defined(STM32F410xx) || defined(STM32F411xE)
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#if defined(USE_HSE_BYPASS)
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if (pllsource != 0)
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{
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/* HSE used as PLL clock source */
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pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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#else
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if (pllsource == 0)
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{
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/* HSI used as PLL clock source */
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pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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#endif /* USE_HSE_BYPASS */
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#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F446xx || STM32F469_479xx */
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pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
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SystemCoreClock = pllvco/pllp;
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break;
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@ -657,7 +628,6 @@ void SystemCoreClockUpdate(void)
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*/
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void SetSysClock(void)
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{
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#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx)|| defined(STM32F469_479xx)
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/******************************************************************************/
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/* PLL (clocked by HSE) used as System clock source */
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/******************************************************************************/
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@ -707,16 +677,22 @@ void SetSysClock(void)
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RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
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#endif /* STM32F401xx */
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#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx)
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/* Configure the main PLL */
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RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
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(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
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#endif /* STM32F40_41xxx || STM32F401xx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */
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#if defined(STM32F410xx) || defined(STM32F411xE)
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/* PCLK2 = HCLK / 2*/
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RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
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/* PCLK1 = HCLK / 4*/
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RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
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#endif /* STM32F410xx || STM32F411xE */
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#if defined(STM32F446xx)
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/* Configure the main PLL */
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RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
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(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28);
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#else
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/* Configure the main PLL */
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RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
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(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
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#endif /* STM32F446xx */
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/* Enable the main PLL */
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@ -737,19 +713,17 @@ void SetSysClock(void)
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while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
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{
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}
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/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
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#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
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#if defined(STM32F40_41xxx)
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#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
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/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
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#endif /* STM32F40_41xxx */
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#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
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#if defined(STM32F401xx)
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#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE)
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/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
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#endif /* STM32F401xx */
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#endif /* STM32F401xx || STM32F410xx || STM32F411xE*/
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/* Select the main PLL as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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@ -764,113 +738,6 @@ void SetSysClock(void)
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{ /* If HSE fails to start-up, the application will have wrong clock
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configuration. User can add here some code to deal with this error */
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}
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#elif defined(STM32F410xx) || defined(STM32F411xE)
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#if defined(USE_HSE_BYPASS)
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/******************************************************************************/
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/* PLL (clocked by HSE) used as System clock source */
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/******************************************************************************/
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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/* Enable HSE and HSE BYPASS */
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RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CR & RCC_CR_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if (HSEStatus == (uint32_t)0x01)
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{
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/* Select regulator voltage output Scale 1 mode */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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PWR->CR |= PWR_CR_VOS;
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/* HCLK = SYSCLK / 1*/
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RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
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/* PCLK2 = HCLK / 2*/
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RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
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/* PCLK1 = HCLK / 4*/
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RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
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/* Configure the main PLL */
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RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
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(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
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/* Enable the main PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till the main PLL is ready */
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while((RCC->CR & RCC_CR_PLLRDY) == 0)
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{
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}
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/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
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/* Select the main PLL as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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/* Wait till the main PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
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{
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}
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}
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else
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{ /* If HSE fails to start-up, the application will have wrong clock
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configuration. User can add here some code to deal with this error */
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}
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#else /* HSI will be used as PLL clock source */
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/* Select regulator voltage output Scale 1 mode */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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PWR->CR |= PWR_CR_VOS;
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/* HCLK = SYSCLK / 1*/
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RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
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/* PCLK2 = HCLK / 2*/
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RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
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/* PCLK1 = HCLK / 4*/
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RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
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/* Configure the main PLL */
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RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24);
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/* Enable the main PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till the main PLL is ready */
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while((RCC->CR & RCC_CR_PLLRDY) == 0)
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{
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}
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/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
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/* Select the main PLL as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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/* Wait till the main PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
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{
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}
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#endif /* USE_HSE_BYPASS */
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#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */
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}
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/**
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