mirror of
https://github.com/betaflight/betaflight.git
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STM32H730 - Initial ST32H730 support.
The H730 is a value-line CPU, similar to the H723/H725, but with only 128kb RAM. The FC firmware code is designed to RUN from external flash in MEMORY MAPPED mode, via OctoSPI. Use of ITCM/DTCM advised for core loops, like PID control. A bootloader is required to enable memory-mapped mode and jump to the firmware, similar to how EXST bootloader system works. Config storage is not part of this commit and is a problem when using a single flash chip in memory mapped mode because the CPU can't run read/write routines from the flash chip while writing to the flash chip. Until flash read/write routines are updated the solution requires either a second flash chip on an SPI interface, or the use of an SD card for config storage. Additional commits will support read/write of config to the code/data storage flash chip to enable cheap and space efficient single-flash-chip FC solutions. Squashed commits: STM32H730 - Workaround issue with 2GB `.elf` files being created. STM32H730 - Reduce firmware size to 1MB. STM32H730 - Add USB HS configuration. STM32H730 - Add ADC internal tag mappings. STM32H730 - Update all ADC mappings based on the referenced ST documentation. Add the VBAT channels. STM32H730 - Fix DMA continuous requests. STM32H730 - Fix ADC_INTERNAL confusion. STM32H730/G4 - Disambiguate use of ADC_CHANNEL_INTERNAL_FIRST_ID. STM32H730 - Fix documentation reference. STM32H730 - Add DMA request mapping for ADC3. STM32H730 - Explicitly set the ADC clock. STM32H730 - Configure PLL2 speeds correctly. * Tested with Ultrafast 64GB SanDisk SDXC card. STM32H730 - Use 50Mhz clock for SDXC cards. * Tested with SanDisk Ultra 64GB. 100Mhz clock gave CRC errors. STM32H730 - Ensure USB has a lower NVIC priority than the SDMMC card reads. If it's higher, 0, then the SDMMC's DMA IRQ handler doesn't get called when handing USB MSC storage reads. STM32H730 - Support CPU name in CLI. STM32H730 - Rebuild when linker scripts changes.
This commit is contained in:
Dominic Clifton
Dominic Clifton
parent
0b7fcb7df4
commit
a325e2386d
24 changed files with 1382 additions and 43 deletions
174
src/link/stm32_h730_common.ld
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174
src/link/stm32_h730_common.ld
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@ -0,0 +1,174 @@
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/* Entry Point */
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = ORIGIN(STACKRAM) + LENGTH(STACKRAM); /* end of RAM */
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/* Base address where the quad spi. */
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__octospi1_start = ORIGIN(OCTOSPI1);
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__octospi2_start = ORIGIN(OCTOSPI2);
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/* Generate a link error if heap and stack don't fit into RAM */
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_Min_Heap_Size = 0; /* required amount of heap */
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_Min_Stack_Size = 0x800; /* required amount of stack */
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/* Define output sections */
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SECTIONS
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{
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_isr_vector_table_flash_base = LOADADDR(.isr_vector);
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PROVIDE (isr_vector_table_flash_base = _isr_vector_table_flash_base);
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.isr_vector :
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{
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. = ALIGN(512);
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PROVIDE (isr_vector_table_base = .);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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PROVIDE (isr_vector_table_end = .);
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} >VECTAB AT> MAIN
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_ram_isr_vector_table_base = LOADADDR(.ram_isr_vector);
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PROVIDE (ram_isr_vector_table_base = _ram_isr_vector_table_base);
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.ram_isr_vector (NOLOAD) :
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{
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. = ALIGN(512); /* Vector table offset must be multiple of 0x200 */
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PROVIDE (ram_isr_vector_table_base = .);
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. += (isr_vector_table_end - isr_vector_table_base);
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. = ALIGN(4);
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PROVIDE (ram_isr_vector_table_end = .);
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} >DTCM_RAM
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/* The program code and other data goes into MAIN */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .; /* define a global symbols at end of code */
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} >MAIN
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/* Critical program code goes into ITCM RAM */
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/* Copy specific fast-executing code to ITCM RAM */
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tcm_code = LOADADDR(.tcm_code);
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.tcm_code :
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{
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. = ALIGN(4);
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tcm_code_start = .;
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*(.tcm_code)
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*(.tcm_code*)
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. = ALIGN(4);
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tcm_code_end = .;
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} >ITCM_RAM AT >MAIN
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} >MAIN
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.ARM :
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{
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__exidx_start = .;
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*(.ARM.exidx*) __exidx_end = .;
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} >MAIN
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.pg_registry :
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{
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PROVIDE_HIDDEN (__pg_registry_start = .);
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KEEP (*(.pg_registry))
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KEEP (*(SORT(.pg_registry.*)))
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PROVIDE_HIDDEN (__pg_registry_end = .);
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} >MAIN
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.pg_resetdata :
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{
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PROVIDE_HIDDEN (__pg_resetdata_start = .);
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KEEP (*(.pg_resetdata))
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PROVIDE_HIDDEN (__pg_resetdata_end = .);
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} >MAIN
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/* used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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/* Initialized data sections goes into RAM, load LMA copy after code */
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.data :
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{
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. = ALIGN(4);
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_sdata = .; /* create a global symbol at data start */
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*(.data) /* .data sections */
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*(.data*) /* .data* sections */
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. = ALIGN(4);
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_edata = .; /* define a global symbol at data end */
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} >DTCM_RAM AT >MAIN
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/* Uninitialized data section */
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. = ALIGN(4);
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.bss (NOLOAD) :
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{
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/* This is used by the startup in order to initialize the .bss secion */
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_sbss = .; /* define a global symbol at bss start */
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__bss_start__ = _sbss;
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*(.bss)
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*(SORT_BY_ALIGNMENT(.bss*))
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*(COMMON)
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. = ALIGN(4);
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_ebss = .; /* define a global symbol at bss end */
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__bss_end__ = _ebss;
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} >RAM
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/* Uninitialized data section */
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. = ALIGN(4);
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.sram2 (NOLOAD) :
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{
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/* This is used by the startup in order to initialize the .sram2 secion */
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_ssram2 = .; /* define a global symbol at sram2 start */
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__sram2_start__ = _ssram2;
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*(.sram2)
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*(SORT_BY_ALIGNMENT(.sram2*))
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. = ALIGN(4);
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_esram2 = .; /* define a global symbol at sram2 end */
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__sram2_end__ = _esram2;
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} >RAM
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/* used during startup to initialized fastram_data */
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_sfastram_idata = LOADADDR(.fastram_data);
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/* Initialized FAST_DATA section for unsuspecting developers */
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.fastram_data :
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{
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. = ALIGN(4);
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_sfastram_data = .; /* create a global symbol at data start */
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*(.fastram_data) /* .data sections */
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*(.fastram_data*) /* .data* sections */
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. = ALIGN(4);
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_efastram_data = .; /* define a global symbol at data end */
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} >FASTRAM AT >MAIN
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. = ALIGN(4);
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.fastram_bss (NOLOAD) :
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{
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_sfastram_bss = .;
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__fastram_bss_start__ = _sfastram_bss;
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*(.fastram_bss)
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*(SORT_BY_ALIGNMENT(.fastram_bss*))
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. = ALIGN(4);
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_efastram_bss = .;
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__fastram_bss_end__ = _efastram_bss;
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} >FASTRAM
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}
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44
src/link/stm32_h730_common_post.ld
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44
src/link/stm32_h730_common_post.ld
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@ -0,0 +1,44 @@
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SECTIONS
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{
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.persistent_data (NOLOAD) :
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{
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__persistent_data_start__ = .;
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*(.persistent_data)
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. = ALIGN(4);
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__persistent_data_end__ = .;
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} >RAM
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/* User_heap_stack section, used to check that there is enough RAM left */
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_heap_stack_end = ORIGIN(STACKRAM)+LENGTH(STACKRAM) - 8; /* 8 bytes to allow for alignment */
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_heap_stack_begin = _heap_stack_end - _Min_Stack_Size - _Min_Heap_Size;
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. = _heap_stack_begin;
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._user_heap_stack :
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{
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. = ALIGN(4);
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PROVIDE ( end = . );
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PROVIDE ( _end = . );
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. = . + _Min_Heap_Size;
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. = . + _Min_Stack_Size;
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. = ALIGN(4);
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} >STACKRAM = 0xa5
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/* MEMORY_bank1 section, code must be located here explicitly */
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/* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
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.memory_b1_text :
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{
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*(.mb1text) /* .mb1text sections (code) */
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*(.mb1text*) /* .mb1text* sections (code) */
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*(.mb1rodata) /* read-only data (constants) */
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*(.mb1rodata*)
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} >MEMORY_B1
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/* Remove information from the standard libraries */
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/DISCARD/ :
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{
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libc.a ( * )
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libm.a ( * )
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libgcc.a ( * )
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}
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.ARM.attributes 0 : { *(.ARM.attributes) }
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}
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143
src/link/stm32_ram_h730_exst.ld
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143
src/link/stm32_ram_h730_exst.ld
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/*
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*****************************************************************************
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**
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** File : stm32_flash_h750_exst.ld
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**
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** Abstract : Linker script for STM32H750xB Device with
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** 512K AXI-RAM mapped onto AXI bus on D1 domain
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** 128K SRAM1 mapped on D2 domain
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** 128K SRAM2 mapped on D2 domain
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** 32K SRAM3 mapped on D2 domain
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** 64K SRAM4 mapped on D3 domain
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** 64K ITCM
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** 128K DTCM
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**
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*****************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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/*
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0x00000000 to 0x0000FFFF 64K ITCM
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0x20000000 to 0x2001FFFF 128K DTCM, main RAM
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0x24000000 to 0x2404FFFF 320K AXI SRAM, D1 domain
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0x30000000 to 0x30003FFF 16K SRAM1, D2 domain
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0x30004000 to 0x30007FFF 16K SRAM2, D2 domain
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0x38000000 to 0x38003FFF 16K SRAM4, D3 domain, unused
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0x38800000 to 0x38800FFF 4K BACKUP SRAM, Backup domain, unused
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0x08000000 to 0x0801FFFF 128K isr vector, startup code, firmware, no config! // FLASH_Sector_0
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*/
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/*
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For H7 EXFL (External Flash) targets a binary is built that is placed on an external device.
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The bootloader will enable the memory mapped mode on the CPU which allows code to run directly from
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the external flash device.
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The bootloader then executes code at the CODE_RAM address. The address of CODE_RAM is fixed to 0x90010000
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and must not be changed.
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The initial CODE_RAM is sized at 1MB.
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*/
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/* see .exst section below */
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_exst_hash_size = 64;
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/* Specify the memory areas */
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MEMORY
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{
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ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
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DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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RAM (rwx) : ORIGIN = 0x24000000, LENGTH = 128K + 192K /* 128K AXI SRAM + 192K ITCM & AXI = 320K */
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D2_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 32K /* SRAM1 16K + SRAM2 16K */
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D3_RAM (rwx) : ORIGIN = 0x38000000, LENGTH = 16K /* SRAM4 16K */
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BACKUP_SRAM (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
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MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
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OCTOSPI2 (rx) : ORIGIN = 0x70000000, LENGTH = 256M
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OCTOSPI1 (rx) : ORIGIN = 0x90000000, LENGTH = 256M
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OCTOSPI1_CODE (rx): ORIGIN = ORIGIN(OCTOSPI1) + 1M, LENGTH = 1M - _exst_hash_size /* hard coded start address, as required by SPRACINGH7 boot loader, don't change! */
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EXST_HASH (rx) : ORIGIN = ORIGIN(OCTOSPI1_CODE) + LENGTH(OCTOSPI1_CODE), LENGTH = _exst_hash_size
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}
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REGION_ALIAS("STACKRAM", DTCM_RAM)
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REGION_ALIAS("FASTRAM", DTCM_RAM)
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REGION_ALIAS("MAIN", OCTOSPI1_CODE)
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REGION_ALIAS("VECTAB", MAIN)
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INCLUDE "stm32_h730_common.ld"
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SECTIONS
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{
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/* used during startup to initialized dmaram_data */
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_sdmaram_idata = LOADADDR(.dmaram_data);
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. = ALIGN(32);
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.dmaram_data :
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{
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PROVIDE(dmaram_start = .);
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_sdmaram = .;
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_dmaram_start__ = _sdmaram;
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_sdmaram_data = .; /* create a global symbol at data start */
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*(.dmaram_data) /* .data sections */
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*(.dmaram_data*) /* .data* sections */
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. = ALIGN(32);
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_edmaram_data = .; /* define a global symbol at data end */
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} >RAM AT >MAIN
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. = ALIGN(32);
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.dmaram_bss (NOLOAD) :
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{
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_sdmaram_bss = .;
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__dmaram_bss_start__ = _sdmaram_bss;
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*(.dmaram_bss)
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*(SORT_BY_ALIGNMENT(.dmaram_bss*))
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. = ALIGN(32);
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_edmaram_bss = .;
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__dmaram_bss_end__ = _edmaram_bss;
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} >RAM
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. = ALIGN(32);
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.DMA_RAM (NOLOAD) :
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{
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KEEP(*(.DMA_RAM))
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PROVIDE(dmaram_end = .);
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_edmaram = .;
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_dmaram_end__ = _edmaram;
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} >RAM
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.DMA_RW_D2 (NOLOAD) :
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{
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. = ALIGN(32);
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PROVIDE(dmarw_start = .);
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_sdmarw = .;
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_dmarw_start__ = _sdmarw;
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KEEP(*(.DMA_RW))
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PROVIDE(dmarw_end = .);
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_edmarw = .;
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_dmarw_end__ = _edmarw;
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} >D2_RAM
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.DMA_RW_AXI (NOLOAD) :
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{
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. = ALIGN(32);
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PROVIDE(dmarwaxi_start = .);
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_sdmarwaxi = .;
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_dmarwaxi_start__ = _sdmarwaxi;
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KEEP(*(.DMA_RW_AXI))
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PROVIDE(dmarwaxi_end = .);
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_edmarwaxi = .;
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_dmarwaxi_end__ = _edmarwaxi;
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} >RAM
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}
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INCLUDE "stm32_h730_common_post.ld"
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INCLUDE "stm32_ram_h730_exst_post.ld"
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29
src/link/stm32_ram_h730_exst_post.ld
Normal file
29
src/link/stm32_ram_h730_exst_post.ld
Normal file
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@ -0,0 +1,29 @@
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SECTIONS
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{
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/* Create space for a hash. Currently an MD5 has is used, which is 16 */
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/* bytes long. however the last 64 bytes are RESERVED for hash related */
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.exst_hash :
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{
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/* 64 bytes is the size of an MD5 hashing block size. */
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. = ORIGIN(EXST_HASH);
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BYTE(0x00); /* block format */
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BYTE(0x00); /* Checksum method, 0x00 = MD5 hash */
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BYTE(0x00); /* Reserved */
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BYTE(0x00); /* Reserved */
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/* Fill the last 60 bytes with data, including an empty hash aligned */
|
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/* to the last 16 bytes. */
|
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FILL(0x00000000); /* Reserved */
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. = ORIGIN(EXST_HASH) + LENGTH(EXST_HASH) - 16;
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__md5_hash_address__ = .;
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LONG(0x00000000);
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LONG(0x00000000);
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LONG(0x00000000);
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LONG(0x00000000);
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. = ORIGIN(EXST_HASH) + LENGTH(EXST_HASH);
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__firmware_end__ = .;
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} >EXST_HASH
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}
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