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[H7] Enable timer
[TIME] Basic def [TIMER] timer related commits [TIMER] Remove stale comments from timer_stm32h7xx.c [TIMER] New timerClock() based on RM0443 Table 48 [TIMER] Add DMA handling [TIMER] White space tidy in timer_def.h Add TIM1_UP_IRQ handling Fix DEF_TIM_DMA_FULL emitting error for 7th and 15th entry STM32H7 - add TIM15-CH2 (No DMA) Fix comment spelling errors. timer.h change for "Burst Dshot First working version" Fix bad TIM9 handling for non-H7 case Touch-up after rebase (timer.h) F4 and F7 does not have dmaIrqHandler in timerHardware_s (anymore) Changes per PR comment
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4 changed files with 424 additions and 9 deletions
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src/main/drivers/timer_stm32h7xx.c
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src/main/drivers/timer_stm32h7xx.c
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/*
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* This file is part of Cleanflight and Betaflight.
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*
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* Cleanflight and Betaflight are free software. You can redistribute
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* this software and/or modify this software under the terms of the
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* GNU General Public License as published by the Free Software
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* Foundation, either version 3 of the License, or (at your option)
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* any later version.
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*
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* Cleanflight and Betaflight are distributed in the hope that they
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* will be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software.
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*
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "platform.h"
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#ifdef USE_TIMER
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#include "common/utils.h"
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#include "stm32h7xx.h"
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#include "rcc.h"
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#include "timer.h"
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const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
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{ .TIMx = TIM1, .rcc = RCC_APB2(TIM1), .inputIrq = TIM1_CC_IRQn},
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{ .TIMx = TIM2, .rcc = RCC_APB1L(TIM2), .inputIrq = TIM2_IRQn},
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{ .TIMx = TIM3, .rcc = RCC_APB1L(TIM3), .inputIrq = TIM3_IRQn},
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{ .TIMx = TIM4, .rcc = RCC_APB1L(TIM4), .inputIrq = TIM4_IRQn},
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{ .TIMx = TIM5, .rcc = RCC_APB1L(TIM5), .inputIrq = TIM5_IRQn},
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{ .TIMx = TIM6, .rcc = RCC_APB1L(TIM6), .inputIrq = 0},
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{ .TIMx = TIM7, .rcc = RCC_APB1L(TIM7), .inputIrq = 0},
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{ .TIMx = TIM8, .rcc = RCC_APB2(TIM8), .inputIrq = TIM8_CC_IRQn},
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{ .TIMx = TIM12, .rcc = RCC_APB1L(TIM12), .inputIrq = TIM8_BRK_TIM12_IRQn},
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{ .TIMx = TIM13, .rcc = RCC_APB1L(TIM13), .inputIrq = TIM8_UP_TIM13_IRQn},
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{ .TIMx = TIM14, .rcc = RCC_APB1L(TIM14), .inputIrq = TIM8_TRG_COM_TIM14_IRQn},
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{ .TIMx = TIM15, .rcc = RCC_APB2(TIM15), .inputIrq = TIM15_IRQn},
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{ .TIMx = TIM16, .rcc = RCC_APB2(TIM16), .inputIrq = TIM16_IRQn},
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{ .TIMx = TIM17, .rcc = RCC_APB2(TIM17), .inputIrq = TIM17_IRQn},
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};
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uint32_t timerClock(TIM_TypeDef *tim)
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{
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int timpre;
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uint32_t pclk;
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uint32_t ppre;
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// Implement the table:
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// RM0433 "Table 48. Ratio between clock timer and pclk"
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if (tim == TIM1 || tim == TIM8 || tim == TIM15 || tim == TIM16 || tim == TIM17) {
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// Timers on APB2
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pclk = HAL_RCC_GetPCLK2Freq();
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ppre = (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos;
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} else {
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// Timers on APB1
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pclk = HAL_RCC_GetPCLK1Freq();
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ppre = (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos;
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}
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timpre = (RCC->CFGR & RCC_CFGR_TIMPRE) ? 1 : 0;
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int index = (timpre << 3) | ppre;
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static uint8_t periphToKernel[16] = { // The mutiplier table
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1, 1, 1, 1, 2, 2, 2, 2, // TIMPRE = 0
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1, 1, 1, 1, 2, 4, 4, 4 // TIMPRE = 1
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};
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return pclk * periphToKernel[index];
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}
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#endif
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