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FIX: Adding USE_DMA wrapper around those only available with USE_DMA active (#14133)

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* FIX: Adding USE_DMA wrapper around those only available with USE_DMA active

* Additional condition

* Renaming to dmaInitRx and dmaInitTx
This commit is contained in:
Jay Blackman 2025-01-10 06:29:43 +11:00 • committed by GitHub
parent 67bb6f88b7
commit a8d599e187
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
6 changed files with 156 additions and 154 deletions
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18
src/main/drivers/bus.h
View file

@ -62,16 +62,16 @@ typedef struct busDevice_s {
} busType_u;
bool useDMA;
uint8_t deviceCount;
#ifdef USE_DMA
dmaChannelDescriptor_t *dmaTx;
dmaChannelDescriptor_t *dmaRx;
#ifdef USE_DMA
// Use a reference here as this saves RAM for unused descriptors
#if defined(USE_FULL_LL_DRIVER)
LL_DMA_InitTypeDef *initTx;
LL_DMA_InitTypeDef *initRx;
LL_DMA_InitTypeDef *dmaInitTx;
LL_DMA_InitTypeDef *dmaInitRx;
#else
DMA_InitTypeDef *initTx;
DMA_InitTypeDef *initRx;
DMA_InitTypeDef *dmaInitTx;
DMA_InitTypeDef *dmaInitRx;
#endif
#endif // USE_DMA
volatile struct busSegment_s* volatile curSegment;
@ -97,11 +97,11 @@ typedef struct extDevice_s {
#ifdef USE_DMA
// Cache the init structure for the next DMA transfer to reduce inter-segment delay
#if defined(USE_FULL_LL_DRIVER)
LL_DMA_InitTypeDef initTx;
LL_DMA_InitTypeDef initRx;
LL_DMA_InitTypeDef dmaInitTx;
LL_DMA_InitTypeDef dmaInitRx;
#else
DMA_InitTypeDef initTx;
DMA_InitTypeDef initRx;
DMA_InitTypeDef dmaInitTx;
DMA_InitTypeDef dmaInitRx;
#endif
#endif // USE_DMA
// Support disabling DMA on a per device basis

6
src/main/drivers/bus_spi.c
View file

@ -365,8 +365,10 @@ bool spiSetBusInstance(extDevice_t *dev, uint32_t device)
bus->busType = BUS_TYPE_SPI;
bus->useDMA = false;
bus->deviceCount = 1;
bus->initTx = &dev->initTx;
bus->initRx = &dev->initRx;
#ifdef USE_DMA
bus->dmaInitTx = &dev->dmaInitTx;
bus->dmaInitRx = &dev->dmaInitRx;
#endif
return true;
}

68
src/platform/APM32/bus_spi_apm32.c
View file

@ -99,31 +99,31 @@ void spiInitDevice(SPIDevice device)
void spiInternalResetDescriptors(busDevice_t *bus)
{
DDL_DMA_InitTypeDef *initTx = bus->initTx;
DDL_DMA_InitTypeDef *dmaInitTx = bus->dmaInitTx;
DDL_DMA_StructInit(initTx);
DDL_DMA_StructInit(dmaInitTx);
initTx->Channel = bus->dmaTx->channel;
initTx->Mode = DDL_DMA_MODE_NORMAL;
initTx->Direction = DDL_DMA_DIRECTION_MEMORY_TO_PERIPH;
initTx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DATA;
initTx->Priority = DDL_DMA_PRIORITY_LOW;
initTx->PeriphOrM2MSrcIncMode = DDL_DMA_PERIPH_NOINCREMENT;
initTx->PeriphOrM2MSrcDataSize = DDL_DMA_PDATAALIGN_BYTE;
initTx->MemoryOrM2MDstDataSize = DDL_DMA_MDATAALIGN_BYTE;
dmaInitTx->Channel = bus->dmaTx->channel;
dmaInitTx->Mode = DDL_DMA_MODE_NORMAL;
dmaInitTx->Direction = DDL_DMA_DIRECTION_MEMORY_TO_PERIPH;
dmaInitTx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DATA;
dmaInitTx->Priority = DDL_DMA_PRIORITY_LOW;
dmaInitTx->PeriphOrM2MSrcIncMode = DDL_DMA_PERIPH_NOINCREMENT;
dmaInitTx->PeriphOrM2MSrcDataSize = DDL_DMA_PDATAALIGN_BYTE;
dmaInitTx->MemoryOrM2MDstDataSize = DDL_DMA_MDATAALIGN_BYTE;
if (bus->dmaRx) {
DDL_DMA_InitTypeDef *initRx = bus->initRx;
DDL_DMA_InitTypeDef *dmaInitRx = bus->dmaInitRx;
DDL_DMA_StructInit(initRx);
DDL_DMA_StructInit(dmaInitRx);
initRx->Channel = bus->dmaRx->channel;
initRx->Mode = DDL_DMA_MODE_NORMAL;
initRx->Direction = DDL_DMA_DIRECTION_PERIPH_TO_MEMORY;
initRx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DATA;
initRx->Priority = DDL_DMA_PRIORITY_LOW;
initRx->PeriphOrM2MSrcIncMode = DDL_DMA_PERIPH_NOINCREMENT;
initRx->PeriphOrM2MSrcDataSize = DDL_DMA_PDATAALIGN_BYTE;
dmaInitRx->Channel = bus->dmaRx->channel;
dmaInitRx->Mode = DDL_DMA_MODE_NORMAL;
dmaInitRx->Direction = DDL_DMA_DIRECTION_PERIPH_TO_MEMORY;
dmaInitRx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DATA;
dmaInitRx->Priority = DDL_DMA_PRIORITY_LOW;
dmaInitRx->PeriphOrM2MSrcIncMode = DDL_DMA_PERIPH_NOINCREMENT;
dmaInitRx->PeriphOrM2MSrcDataSize = DDL_DMA_PDATAALIGN_BYTE;
}
}
@ -175,34 +175,34 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit)
int len = segment->len;
uint8_t *txData = segment->u.buffers.txData;
DDL_DMA_InitTypeDef *initTx = bus->initTx;
DDL_DMA_InitTypeDef *dmaInitTx = bus->dmaInitTx;
if (txData) {
initTx->MemoryOrM2MDstAddress = (uint32_t)txData;
initTx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_INCREMENT;
dmaInitTx->MemoryOrM2MDstAddress = (uint32_t)txData;
dmaInitTx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_INCREMENT;
} else {
dummyTxByte = 0xff;
initTx->MemoryOrM2MDstAddress = (uint32_t)&dummyTxByte;
initTx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_NOINCREMENT;
dmaInitTx->MemoryOrM2MDstAddress = (uint32_t)&dummyTxByte;
dmaInitTx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_NOINCREMENT;
}
initTx->NbData = len;
dmaInitTx->NbData = len;
if (dev->bus->dmaRx) {
uint8_t *rxData = segment->u.buffers.rxData;
DDL_DMA_InitTypeDef *initRx = bus->initRx;
DDL_DMA_InitTypeDef *dmaInitRx = bus->dmaInitRx;
if (rxData) {
/* Flush the D cache for the start and end of the receive buffer as
* the cache will be invalidated after the transfer and any valid data
* just before/after must be in memory at that point
*/
initRx->MemoryOrM2MDstAddress = (uint32_t)rxData;
initRx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_INCREMENT;
dmaInitRx->MemoryOrM2MDstAddress = (uint32_t)rxData;
dmaInitRx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_INCREMENT;
} else {
initRx->MemoryOrM2MDstAddress = (uint32_t)&dummyRxByte;
initRx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_NOINCREMENT;
dmaInitRx->MemoryOrM2MDstAddress = (uint32_t)&dummyRxByte;
dmaInitRx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_NOINCREMENT;
}
initRx->NbData = len;
dmaInitRx->NbData = len;
}
}
@ -235,8 +235,8 @@ void spiInternalStartDMA(const extDevice_t *dev)
DDL_EX_DMA_EnableIT_TC(streamRegsRx);
// Update streams
DDL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->initTx);
DDL_DMA_Init(dmaRx->dma, dmaRx->stream, bus->initRx);
DDL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->dmaInitTx);
DDL_DMA_Init(dmaRx->dma, dmaRx->stream, bus->dmaInitRx);
/* Note from AN4031
*
@ -265,7 +265,7 @@ void spiInternalStartDMA(const extDevice_t *dev)
DDL_EX_DMA_EnableIT_TC(streamRegsTx);
// Update streams
DDL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->initTx);
DDL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->dmaInitTx);
/* Note from AN4031
*

64
src/platform/AT32/bus_spi_at32bsp.c
View file

@ -100,29 +100,29 @@ void spiInitDevice(SPIDevice device)
void spiInternalResetDescriptors(busDevice_t *bus)
{
dma_init_type *initTx = bus->initTx;
dma_init_type *dmaInitTx = bus->dmaInitTx;
dma_default_para_init(initTx);
dma_default_para_init(dmaInitTx);
initTx->direction=DMA_DIR_MEMORY_TO_PERIPHERAL;
initTx->loop_mode_enable=FALSE;
initTx->peripheral_base_addr=(uint32_t)&bus->busType_u.spi.instance->dt ;
initTx->priority =DMA_PRIORITY_LOW;
initTx->peripheral_inc_enable =FALSE;
initTx->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
initTx->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dmaInitTx->direction=DMA_DIR_MEMORY_TO_PERIPHERAL;
dmaInitTx->loop_mode_enable=FALSE;
dmaInitTx->peripheral_base_addr=(uint32_t)&bus->busType_u.spi.instance->dt ;
dmaInitTx->priority =DMA_PRIORITY_LOW;
dmaInitTx->peripheral_inc_enable =FALSE;
dmaInitTx->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dmaInitTx->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
if (bus->dmaRx) {
dma_init_type *initRx = bus->initRx;
dma_init_type *dmaInitRx = bus->dmaInitRx;
dma_default_para_init(initRx);
dma_default_para_init(dmaInitRx);
initRx->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
initRx->loop_mode_enable = FALSE;
initRx->peripheral_base_addr = (uint32_t)&bus->busType_u.spi.instance->dt;
initRx->priority = DMA_PRIORITY_LOW;
initRx->peripheral_inc_enable = FALSE;
initRx->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dmaInitRx->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dmaInitRx->loop_mode_enable = FALSE;
dmaInitRx->peripheral_base_addr = (uint32_t)&bus->busType_u.spi.instance->dt;
dmaInitRx->priority = DMA_PRIORITY_LOW;
dmaInitRx->peripheral_inc_enable = FALSE;
dmaInitRx->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
}
}
@ -175,31 +175,31 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit)
int len = segment->len;
uint8_t *txData = segment->u.buffers.txData;
dma_init_type *initTx = bus->initTx;
dma_init_type *dmaInitTx = bus->dmaInitTx;
if (txData) {
initTx->memory_base_addr = (uint32_t)txData;
initTx->memory_inc_enable =TRUE;
dmaInitTx->memory_base_addr = (uint32_t)txData;
dmaInitTx->memory_inc_enable =TRUE;
} else {
dummyTxByte = 0xff;
initTx->memory_base_addr = (uint32_t)&dummyTxByte;
initTx->memory_inc_enable =FALSE;
dmaInitTx->memory_base_addr = (uint32_t)&dummyTxByte;
dmaInitTx->memory_inc_enable =FALSE;
}
initTx->buffer_size =len;
dmaInitTx->buffer_size =len;
if (dev->bus->dmaRx) {
uint8_t *rxData = segment->u.buffers.rxData;
dma_init_type *initRx = bus->initRx;
dma_init_type *dmaInitRx = bus->dmaInitRx;
if (rxData) {
initRx->memory_base_addr= (uint32_t)rxData;
initRx->memory_inc_enable = TRUE;
dmaInitRx->memory_base_addr= (uint32_t)rxData;
dmaInitRx->memory_inc_enable = TRUE;
} else {
initRx->memory_base_addr = (uint32_t)&dummyRxByte;
initRx->memory_inc_enable = FALSE;
dmaInitRx->memory_base_addr = (uint32_t)&dummyRxByte;
dmaInitRx->memory_inc_enable = FALSE;
}
initRx->buffer_size = len;
dmaInitRx->buffer_size = len;
}
}
@ -229,8 +229,8 @@ void spiInternalStartDMA(const extDevice_t *dev)
xDMA_ITConfig(streamRegsRx, DMA_IT_TCIF, TRUE);
// Update streams
xDMA_Init(streamRegsTx, dev->bus->initTx);
xDMA_Init(streamRegsRx, dev->bus->initRx);
xDMA_Init(streamRegsTx, dev->bus->dmaInitTx);
xDMA_Init(streamRegsRx, dev->bus->dmaInitRx);
// Enable streams
xDMA_Cmd(streamRegsRx, TRUE);
@ -253,7 +253,7 @@ void spiInternalStartDMA(const extDevice_t *dev)
xDMA_Cmd(streamRegsTx, FALSE);
// Update stream
xDMA_Init(streamRegsTx, dev->bus->initTx);
xDMA_Init(streamRegsTx, dev->bus->dmaInitTx);
// Enable stream
xDMA_Cmd(streamRegsTx, TRUE);

80
src/platform/STM32/bus_spi_ll.c
View file

@ -146,45 +146,45 @@ void spiInitDevice(SPIDevice device)
void spiInternalResetDescriptors(busDevice_t *bus)
{
LL_DMA_InitTypeDef *initTx = bus->initTx;
LL_DMA_InitTypeDef *dmaInitTx = bus->dmaInitTx;
LL_DMA_StructInit(initTx);
LL_DMA_StructInit(dmaInitTx);
#if defined(STM32G4) || defined(STM32H7)
initTx->PeriphRequest = bus->dmaTx->channel;
dmaInitTx->PeriphRequest = bus->dmaTx->channel;
#else
initTx->Channel = bus->dmaTx->channel;
dmaInitTx->Channel = bus->dmaTx->channel;
#endif
initTx->Mode = LL_DMA_MODE_NORMAL;
initTx->Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
dmaInitTx->Mode = LL_DMA_MODE_NORMAL;
dmaInitTx->Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
#if defined(STM32H7)
initTx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->TXDR;
dmaInitTx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->TXDR;
#else
initTx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DR;
dmaInitTx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DR;
#endif
initTx->Priority = LL_DMA_PRIORITY_LOW;
initTx->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
initTx->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
initTx->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
dmaInitTx->Priority = LL_DMA_PRIORITY_LOW;
dmaInitTx->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
dmaInitTx->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
dmaInitTx->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
if (bus->dmaRx) {
LL_DMA_InitTypeDef *initRx = bus->initRx;
LL_DMA_InitTypeDef *dmaInitRx = bus->dmaInitRx;
LL_DMA_StructInit(initRx);
LL_DMA_StructInit(dmaInitRx);
#if defined(STM32G4) || defined(STM32H7)
initRx->PeriphRequest = bus->dmaRx->channel;
dmaInitRx->PeriphRequest = bus->dmaRx->channel;
#else
initRx->Channel = bus->dmaRx->channel;
dmaInitRx->Channel = bus->dmaRx->channel;
#endif
initRx->Mode = LL_DMA_MODE_NORMAL;
initRx->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
dmaInitRx->Mode = LL_DMA_MODE_NORMAL;
dmaInitRx->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
#if defined(STM32H7)
initRx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->RXDR;
dmaInitRx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->RXDR;
#else
initRx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DR;
dmaInitRx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DR;
#endif
initRx->Priority = LL_DMA_PRIORITY_LOW;
initRx->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
initRx->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
dmaInitRx->Priority = LL_DMA_PRIORITY_LOW;
dmaInitRx->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
dmaInitRx->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
}
}
@ -285,7 +285,7 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit)
int len = segment->len;
uint8_t *txData = segment->u.buffers.txData;
LL_DMA_InitTypeDef *initTx = bus->initTx;
LL_DMA_InitTypeDef *dmaInitTx = bus->dmaInitTx;
if (txData) {
#ifdef __DCACHE_PRESENT
@ -301,19 +301,19 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit)
(((uint32_t)txData & CACHE_LINE_MASK) + len - 1 + CACHE_LINE_SIZE) & ~CACHE_LINE_MASK);
}
#endif // __DCACHE_PRESENT
initTx->MemoryOrM2MDstAddress = (uint32_t)txData;
initTx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
dmaInitTx->MemoryOrM2MDstAddress = (uint32_t)txData;
dmaInitTx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
} else {
initTx->MemoryOrM2MDstAddress = (uint32_t)&dummyTxByte;
initTx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
dmaInitTx->MemoryOrM2MDstAddress = (uint32_t)&dummyTxByte;
dmaInitTx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
}
initTx->NbData = len;
dmaInitTx->NbData = len;
#if !defined(STM32G4) && !defined(STM32H7)
if (dev->bus->dmaRx) {
#endif
uint8_t *rxData = segment->u.buffers.rxData;
LL_DMA_InitTypeDef *initRx = bus->initRx;
LL_DMA_InitTypeDef *dmaInitRx = bus->dmaInitRx;
if (rxData) {
/* Flush the D cache for the start and end of the receive buffer as
@ -333,13 +333,13 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit)
(((uint32_t)rxData & CACHE_LINE_MASK) + len - 1 + CACHE_LINE_SIZE) & ~CACHE_LINE_MASK);
}
#endif // __DCACHE_PRESENT
initRx->MemoryOrM2MDstAddress = (uint32_t)rxData;
initRx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
dmaInitRx->MemoryOrM2MDstAddress = (uint32_t)rxData;
dmaInitRx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
} else {
initRx->MemoryOrM2MDstAddress = (uint32_t)&dummyRxByte;
initRx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
dmaInitRx->MemoryOrM2MDstAddress = (uint32_t)&dummyRxByte;
dmaInitRx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
}
initRx->NbData = len;
dmaInitRx->NbData = len;
#if !defined(STM32G4) && !defined(STM32H7)
}
#endif
@ -373,8 +373,8 @@ void spiInternalStartDMA(const extDevice_t *dev)
LL_DMA_EnableIT_TC(dmaRx->dma, dmaRx->stream);
// Update channels
LL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->initTx);
LL_DMA_Init(dmaRx->dma, dmaRx->stream, bus->initRx);
LL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->dmaInitTx);
LL_DMA_Init(dmaRx->dma, dmaRx->stream, bus->dmaInitRx);
// Enable channels
LL_DMA_EnableChannel(dmaTx->dma, dmaTx->stream);
@ -395,8 +395,8 @@ void spiInternalStartDMA(const extDevice_t *dev)
LL_EX_DMA_EnableIT_TC(streamRegsRx);
// Update streams
LL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->initTx);
LL_DMA_Init(dmaRx->dma, dmaRx->stream, bus->initRx);
LL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->dmaInitTx);
LL_DMA_Init(dmaRx->dma, dmaRx->stream, bus->dmaInitRx);
/* Note from AN4031
*
@ -436,7 +436,7 @@ void spiInternalStartDMA(const extDevice_t *dev)
LL_EX_DMA_EnableIT_TC(streamRegsTx);
// Update streams
LL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->initTx);
LL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->dmaInitTx);
/* Note from AN4031
*

74
src/platform/STM32/bus_spi_stdperiph.c
View file

@ -106,29 +106,29 @@ void spiInitDevice(SPIDevice device)
void spiInternalResetDescriptors(busDevice_t *bus)
{
DMA_InitTypeDef *initTx = bus->initTx;
DMA_InitTypeDef *dmaInitTx = bus->dmaInitTx;
DMA_StructInit(initTx);
initTx->DMA_Channel = bus->dmaTx->channel;
initTx->DMA_DIR = DMA_DIR_MemoryToPeripheral;
initTx->DMA_Mode = DMA_Mode_Normal;
initTx->DMA_PeripheralBaseAddr = (uint32_t)&bus->busType_u.spi.instance->DR;
initTx->DMA_Priority = DMA_Priority_Low;
initTx->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
initTx->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
initTx->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_StructInit(dmaInitTx);
dmaInitTx->DMA_Channel = bus->dmaTx->channel;
dmaInitTx->DMA_DIR = DMA_DIR_MemoryToPeripheral;
dmaInitTx->DMA_Mode = DMA_Mode_Normal;
dmaInitTx->DMA_PeripheralBaseAddr = (uint32_t)&bus->busType_u.spi.instance->DR;
dmaInitTx->DMA_Priority = DMA_Priority_Low;
dmaInitTx->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
dmaInitTx->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
dmaInitTx->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
if (bus->dmaRx) {
DMA_InitTypeDef *initRx = bus->initRx;
DMA_InitTypeDef *dmaInitRx = bus->dmaInitRx;
DMA_StructInit(initRx);
initRx->DMA_Channel = bus->dmaRx->channel;
initRx->DMA_DIR = DMA_DIR_PeripheralToMemory;
initRx->DMA_Mode = DMA_Mode_Normal;
initRx->DMA_PeripheralBaseAddr = (uint32_t)&bus->busType_u.spi.instance->DR;
initRx->DMA_Priority = DMA_Priority_Low;
initRx->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
initRx->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_StructInit(dmaInitRx);
dmaInitRx->DMA_Channel = bus->dmaRx->channel;
dmaInitRx->DMA_DIR = DMA_DIR_PeripheralToMemory;
dmaInitRx->DMA_Mode = DMA_Mode_Normal;
dmaInitRx->DMA_PeripheralBaseAddr = (uint32_t)&bus->busType_u.spi.instance->DR;
dmaInitRx->DMA_Priority = DMA_Priority_Low;
dmaInitRx->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
dmaInitRx->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
}
}
@ -182,36 +182,36 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit)
int len = segment->len;
uint8_t *txData = segment->u.buffers.txData;
DMA_InitTypeDef *initTx = bus->initTx;
DMA_InitTypeDef *dmaInitTx = bus->dmaInitTx;
if (txData) {
initTx->DMA_Memory0BaseAddr = (uint32_t)txData;
initTx->DMA_MemoryInc = DMA_MemoryInc_Enable;
dmaInitTx->DMA_Memory0BaseAddr = (uint32_t)txData;
dmaInitTx->DMA_MemoryInc = DMA_MemoryInc_Enable;
} else {
dummyTxByte = 0xff;
initTx->DMA_Memory0BaseAddr = (uint32_t)&dummyTxByte;
initTx->DMA_MemoryInc = DMA_MemoryInc_Disable;
dmaInitTx->DMA_Memory0BaseAddr = (uint32_t)&dummyTxByte;
dmaInitTx->DMA_MemoryInc = DMA_MemoryInc_Disable;
}
initTx->DMA_BufferSize = len;
dmaInitTx->DMA_BufferSize = len;
if (dev->bus->dmaRx) {
uint8_t *rxData = segment->u.buffers.rxData;
DMA_InitTypeDef *initRx = bus->initRx;
DMA_InitTypeDef *dmaInitRx = bus->dmaInitRx;
if (rxData) {
initRx->DMA_Memory0BaseAddr = (uint32_t)rxData;
initRx->DMA_MemoryInc = DMA_MemoryInc_Enable;
dmaInitRx->DMA_Memory0BaseAddr = (uint32_t)rxData;
dmaInitRx->DMA_MemoryInc = DMA_MemoryInc_Enable;
} else {
initRx->DMA_Memory0BaseAddr = (uint32_t)&dummyRxByte;
initRx->DMA_MemoryInc = DMA_MemoryInc_Disable;
dmaInitRx->DMA_Memory0BaseAddr = (uint32_t)&dummyRxByte;
dmaInitRx->DMA_MemoryInc = DMA_MemoryInc_Disable;
}
// If possible use 16 bit memory writes to prevent atomic access issues on gyro data
if ((initRx->DMA_Memory0BaseAddr & 0x1) || (len & 0x1)) {
initRx->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
if ((dmaInitRx->DMA_Memory0BaseAddr & 0x1) || (len & 0x1)) {
dmaInitRx->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
} else {
initRx->DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
dmaInitRx->DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
}
initRx->DMA_BufferSize = len;
dmaInitRx->DMA_BufferSize = len;
}
}
@ -240,8 +240,8 @@ void spiInternalStartDMA(const extDevice_t *dev)
DMA_ITConfig(streamRegsRx, DMA_IT_TC, ENABLE);
// Update streams
DMA_Init(streamRegsTx, dev->bus->initTx);
DMA_Init(streamRegsRx, dev->bus->initRx);
DMA_Init(streamRegsTx, dev->bus->dmaInitTx);
DMA_Init(streamRegsRx, dev->bus->dmaInitRx);
/* Note from AN4031
*
@ -269,7 +269,7 @@ void spiInternalStartDMA(const extDevice_t *dev)
DMA_ITConfig(streamRegsTx, DMA_IT_TC, ENABLE);
// Update stream
DMA_Init(streamRegsTx, dev->bus->initTx);
DMA_Init(streamRegsTx, dev->bus->dmaInitTx);
/* Note from AN4031
*