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FIX: Adding USE_DMA wrapper around those only available with USE_DMA active (#14133)

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* FIX: Adding USE_DMA wrapper around those only available with USE_DMA active

* Additional condition

* Renaming to dmaInitRx and dmaInitTx
This commit is contained in:
Jay Blackman 2025-01-10 06:29:43 +11:00 • committed by GitHub
parent 67bb6f88b7
commit a8d599e187
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
6 changed files with 156 additions and 154 deletions
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64
src/platform/AT32/bus_spi_at32bsp.c
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@ -100,29 +100,29 @@ void spiInitDevice(SPIDevice device)
void spiInternalResetDescriptors(busDevice_t *bus)
{
dma_init_type *initTx = bus->initTx;
dma_init_type *dmaInitTx = bus->dmaInitTx;
dma_default_para_init(initTx);
dma_default_para_init(dmaInitTx);
initTx->direction=DMA_DIR_MEMORY_TO_PERIPHERAL;
initTx->loop_mode_enable=FALSE;
initTx->peripheral_base_addr=(uint32_t)&bus->busType_u.spi.instance->dt ;
initTx->priority =DMA_PRIORITY_LOW;
initTx->peripheral_inc_enable =FALSE;
initTx->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
initTx->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dmaInitTx->direction=DMA_DIR_MEMORY_TO_PERIPHERAL;
dmaInitTx->loop_mode_enable=FALSE;
dmaInitTx->peripheral_base_addr=(uint32_t)&bus->busType_u.spi.instance->dt ;
dmaInitTx->priority =DMA_PRIORITY_LOW;
dmaInitTx->peripheral_inc_enable =FALSE;
dmaInitTx->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dmaInitTx->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
if (bus->dmaRx) {
dma_init_type *initRx = bus->initRx;
dma_init_type *dmaInitRx = bus->dmaInitRx;
dma_default_para_init(initRx);
dma_default_para_init(dmaInitRx);
initRx->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
initRx->loop_mode_enable = FALSE;
initRx->peripheral_base_addr = (uint32_t)&bus->busType_u.spi.instance->dt;
initRx->priority = DMA_PRIORITY_LOW;
initRx->peripheral_inc_enable = FALSE;
initRx->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dmaInitRx->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dmaInitRx->loop_mode_enable = FALSE;
dmaInitRx->peripheral_base_addr = (uint32_t)&bus->busType_u.spi.instance->dt;
dmaInitRx->priority = DMA_PRIORITY_LOW;
dmaInitRx->peripheral_inc_enable = FALSE;
dmaInitRx->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
}
}
@ -175,31 +175,31 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit)
int len = segment->len;
uint8_t *txData = segment->u.buffers.txData;
dma_init_type *initTx = bus->initTx;
dma_init_type *dmaInitTx = bus->dmaInitTx;
if (txData) {
initTx->memory_base_addr = (uint32_t)txData;
initTx->memory_inc_enable =TRUE;
dmaInitTx->memory_base_addr = (uint32_t)txData;
dmaInitTx->memory_inc_enable =TRUE;
} else {
dummyTxByte = 0xff;
initTx->memory_base_addr = (uint32_t)&dummyTxByte;
initTx->memory_inc_enable =FALSE;
dmaInitTx->memory_base_addr = (uint32_t)&dummyTxByte;
dmaInitTx->memory_inc_enable =FALSE;
}
initTx->buffer_size =len;
dmaInitTx->buffer_size =len;
if (dev->bus->dmaRx) {
uint8_t *rxData = segment->u.buffers.rxData;
dma_init_type *initRx = bus->initRx;
dma_init_type *dmaInitRx = bus->dmaInitRx;
if (rxData) {
initRx->memory_base_addr= (uint32_t)rxData;
initRx->memory_inc_enable = TRUE;
dmaInitRx->memory_base_addr= (uint32_t)rxData;
dmaInitRx->memory_inc_enable = TRUE;
} else {
initRx->memory_base_addr = (uint32_t)&dummyRxByte;
initRx->memory_inc_enable = FALSE;
dmaInitRx->memory_base_addr = (uint32_t)&dummyRxByte;
dmaInitRx->memory_inc_enable = FALSE;
}
initRx->buffer_size = len;
dmaInitRx->buffer_size = len;
}
}
@ -229,8 +229,8 @@ void spiInternalStartDMA(const extDevice_t *dev)
xDMA_ITConfig(streamRegsRx, DMA_IT_TCIF, TRUE);
// Update streams
xDMA_Init(streamRegsTx, dev->bus->initTx);
xDMA_Init(streamRegsRx, dev->bus->initRx);
xDMA_Init(streamRegsTx, dev->bus->dmaInitTx);
xDMA_Init(streamRegsRx, dev->bus->dmaInitRx);
// Enable streams
xDMA_Cmd(streamRegsRx, TRUE);
@ -253,7 +253,7 @@ void spiInternalStartDMA(const extDevice_t *dev)
xDMA_Cmd(streamRegsTx, FALSE);
// Update stream
xDMA_Init(streamRegsTx, dev->bus->initTx);
xDMA_Init(streamRegsTx, dev->bus->dmaInitTx);
// Enable stream
xDMA_Cmd(streamRegsTx, TRUE);