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Merge pull request #8682 from hydra/fix-invalid-spracingh7extreme-load-address-2

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Fix invalid H7 EXST targert invalid load addresses (Solution B)
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Dominic Clifton 2019-08-09 12:32:43 +02:00 • committed by GitHub
commit aa1f22d9e1
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1 changed files with 6 additions and 6 deletions
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12
src/link/stm32_flash_h750_exst.ld
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@ -20,8 +20,8 @@ ENTRY(Reset_Handler)
/* /*
0x00000000 to 0x0000FFFF 64K ITCM 0x00000000 to 0x0000FFFF 64K ITCM
0x20000000 to 0x2001FFFF 128K DTCM 0x20000000 to 0x2001FFFF 128K DTCM, main RAM
0x24000000 to 0x2407FFFF 512K AXI SRAM, D1 domain, main RAM 0x24000000 to 0x2407FFFF 512K AXI SRAM, D1 domain
0x30000000 to 0x3001FFFF 128K SRAM1, D2 domain, unused 0x30000000 to 0x3001FFFF 128K SRAM1, D2 domain, unused
0x30020000 to 0x3003FFFF 128K SRAM2, D2 domain, unused 0x30020000 to 0x3003FFFF 128K SRAM2, D2 domain, unused
0x30040000 to 0x30047FFF 32K SRAM3, D2 domain, unused 0x30040000 to 0x30047FFF 32K SRAM3, D2 domain, unused
@ -58,9 +58,9 @@ MEMORY
{ {
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
RAM (rwx) : ORIGIN = 0x24000000, LENGTH = 128K RAM (rwx) : ORIGIN = 0x24000000, LENGTH = 64K
CODE_RAM (rx) : ORIGIN = 0x24020000, LENGTH = 384K - _exst_hash_size CODE_RAM (rx) : ORIGIN = 0x24010000, LENGTH = 448K - _exst_hash_size
EXST_HASH (rx) : ORIGIN = 0x24020000 + LENGTH(CODE_RAM), LENGTH = _exst_hash_size EXST_HASH (rx) : ORIGIN = 0x24010000 + LENGTH(CODE_RAM), LENGTH = _exst_hash_size
D2_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 256K /* SRAM1 + SRAM2 */ D2_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 256K /* SRAM1 + SRAM2 */
@ -178,7 +178,7 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
_edata = .; /* define a global symbol at data end */ _edata = .; /* define a global symbol at data end */
} >RAM AT >CODE_RAM } >DTCM_RAM AT >CODE_RAM
/* Uninitialized data section */ /* Uninitialized data section */
. = ALIGN(4); . = ALIGN(4);