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https://github.com/betaflight/betaflight.git
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New timer implementation
This is first part of new softserial code. Main timer code is changed, changes to rest of code are kept to minimum. macros for BASEPRI based synchronization are added to project (atomic.h) TIMER_PERIOD fixed in pwm_rx.c
This commit is contained in:
Petr Ledvina
parent
2c8b3af88d
commit
aa7f5c4a1e
17 changed files with 953 additions and 249 deletions
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@ -21,12 +21,18 @@
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#include <string.h>
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#include "platform.h"
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#include "common/utils.h"
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#include "common/atomic.h"
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#include "nvic.h"
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#include "gpio.h"
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#include "system.h"
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#include "timer.h"
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#include "timer_impl.h"
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#define TIM_N(n) (1 << (n))
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/* FreeFlight/Naze32 timer layout
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TIM2_CH1 RC1 PWM1
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@ -86,11 +92,7 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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{ TIM4, GPIOB, Pin_9, TIM_Channel_4, TIM4_IRQn, 0, Mode_IPD} // PWM14
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};
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#define MAX_TIMERS 4 // TIM1..TIM4
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static const TIM_TypeDef const *timers[MAX_TIMERS] = {
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TIM1, TIM2, TIM3, TIM4
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};
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#define USED_TIMERS (TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4))
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#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4)
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#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB)
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@ -113,11 +115,7 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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{ TIM2, GPIOA, Pin_2, TIM_Channel_3, TIM2_IRQn, 1, GPIO_Mode_AF_PP}, // S6_OUT
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};
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#define MAX_TIMERS 4 // TIM1..TIM4
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static const TIM_TypeDef const *timers[MAX_TIMERS] = {
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TIM1, TIM2, TIM3, TIM4
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};
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#define USED_TIMERS (TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4))
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#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4)
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#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB)
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@ -141,11 +139,7 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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{ TIM2, GPIOA, Pin_2, TIM_Channel_3, TIM2_IRQn, 0, Mode_AF_PP, GPIO_PinSource2, GPIO_AF_1} // PWM14 - PA2
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};
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#define MAX_TIMERS 7
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static const TIM_TypeDef const *timers[MAX_TIMERS] = {
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TIM1, TIM2, TIM3, TIM4, TIM8, TIM16, TIM17
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};
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#define USED_TIMERS (TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(8) | TIM_N(16) | TIM_N(17))
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#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4)
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#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM8 | RCC_APB2Periph_TIM16 | RCC_APB2Periph_TIM17)
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@ -178,11 +172,7 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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{ TIM3, GPIOA, Pin_4, TIM_Channel_2, TIM3_IRQn, 0, Mode_AF_PP, GPIO_PinSource4, GPIO_AF_2} // PWM18 - PA4
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};
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#define MAX_TIMERS 8
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static const TIM_TypeDef const *timers[MAX_TIMERS] = {
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TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16, TIM17
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};
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#define USED_TIMERS (TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(8) | TIM_N(15) | TIM_N(16) | TIM_N(17))
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#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4)
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#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM8 | RCC_APB2Periph_TIM15 | RCC_APB2Periph_TIM16 | RCC_APB2Periph_TIM17)
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@ -209,11 +199,7 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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{ TIM17, GPIOA, Pin_7, TIM_Channel_1, TIM1_TRG_COM_TIM17_IRQn, 1, Mode_AF_PP, GPIO_PinSource7, GPIO_AF_1}, // PA7 - untested
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};
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#define MAX_TIMERS 7
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static const TIM_TypeDef const *timers[MAX_TIMERS] = {
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TIM1, TIM2, TIM3, TIM4, TIM15, TIM16, TIM17
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};
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#define USED_TIMERS (TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(15) | TIM_N(16) | TIM_N(17))
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#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4)
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#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM15 | RCC_APB2Periph_TIM16 | RCC_APB2Periph_TIM17)
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@ -221,91 +207,102 @@ static const TIM_TypeDef const *timers[MAX_TIMERS] = {
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#endif
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#define USED_TIMER_COUNT BITCOUNT(USED_TIMERS)
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#define CC_CHANNELS_PER_TIMER 4 // TIM_Channel_1..4
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#define CC_CHANNELS_PER_TIMER 4 // TIM_Channel_1..4
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static const uint16_t const channels[CC_CHANNELS_PER_TIMER] = {
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TIM_Channel_1, TIM_Channel_2, TIM_Channel_3, TIM_Channel_4
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};
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#define TIM_IT_CCx(ch) (TIM_IT_CC1<<((ch)/4))
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typedef struct timerConfig_s {
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TIM_TypeDef *tim;
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uint8_t channel;
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timerCCCallbackPtr *edgeCallback;
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timerCCCallbackPtr *overflowCallback;
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uint8_t reference;
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timerCCHandlerRec_t* edgeCallback[CC_CHANNELS_PER_TIMER];
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timerOvrHandlerRec_t* overflowCallback[CC_CHANNELS_PER_TIMER];
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timerOvrHandlerRec_t* overflowCallbackActive; // null-terminated linkded list of active overflow callbacks
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} timerConfig_t;
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timerConfig_t timerConfig[USED_TIMER_COUNT];
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static timerConfig_t timerConfig[MAX_TIMERS * CC_CHANNELS_PER_TIMER];
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typedef struct {
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channelType_t type;
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} timerChannelInfo_t;
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timerChannelInfo_t timerChannelInfo[USABLE_TIMER_CHANNEL_COUNT];
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typedef struct {
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uint8_t priority;
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} timerInfo_t;
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timerInfo_t timerInfo[USED_TIMER_COUNT];
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// return index of timer in timer table. Lowest timer has index 0
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#define TIMER_INDEX(i) BITCOUNT((TIM_N(i)-1)&USED_TIMERS)
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static uint8_t lookupTimerIndex(const TIM_TypeDef *tim)
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{
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uint8_t timerIndex = 0;
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while (timers[timerIndex] != tim) {
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timerIndex++;
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#define _CASE_SHF 10 // amount we can safely shift timer address to the right. gcc will throw error if some timers overlap
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#define _CASE_(tim, index) case ((unsigned)tim >> _CASE_SHF): return index; break
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#define _CASE(i) _CASE_(TIM##i##_BASE, TIMER_INDEX(i))
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// let gcc do the work, switch should be quite optimized
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switch((unsigned)tim >> _CASE_SHF) {
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#if USED_TIMERS & TIM_N(1)
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_CASE(1);
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#endif
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#if USED_TIMERS & TIM_N(2)
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_CASE(2);
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#endif
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#if USED_TIMERS & TIM_N(3)
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_CASE(3);
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#endif
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#if USED_TIMERS & TIM_N(4)
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_CASE(4);
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#endif
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#if USED_TIMERS & TIM_N(8)
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_CASE(8);
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#endif
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#if USED_TIMERS & TIM_N(15)
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_CASE(15);
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#endif
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#if USED_TIMERS & TIM_N(16)
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_CASE(16);
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#endif
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#if USED_TIMERS & TIM_N(17)
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_CASE(17);
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#endif
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default: return -1; // make sure final index is out of range
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}
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return timerIndex;
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#undef _CASE
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#undef _CASE_
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}
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static uint8_t lookupChannelIndex(const uint16_t channel)
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TIM_TypeDef * const usedTimers[USED_TIMER_COUNT] = {
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#define _DEF(i) TIM##i
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#if USED_TIMERS & TIM_N(1)
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_DEF(1),
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#endif
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#if USED_TIMERS & TIM_N(2)
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_DEF(2),
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#endif
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#if USED_TIMERS & TIM_N(3)
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_DEF(3),
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#endif
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#if USED_TIMERS & TIM_N(4)
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_DEF(4),
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#endif
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#if USED_TIMERS & TIM_N(8)
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_DEF(8),
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#endif
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#if USED_TIMERS & TIM_N(15)
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_DEF(15),
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#endif
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#if USED_TIMERS & TIM_N(16)
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_DEF(16),
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#endif
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#if USED_TIMERS & TIM_N(17)
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_DEF(17),
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#endif
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#undef _DEF
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};
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static inline uint8_t lookupChannelIndex(const uint16_t channel)
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{
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uint8_t channelIndex = 0;
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while (channels[channelIndex] != channel) {
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channelIndex++;
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}
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return channelIndex;
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}
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static uint8_t lookupTimerConfigIndex(TIM_TypeDef *tim, const uint16_t channel)
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{
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return lookupTimerIndex(tim) + (MAX_TIMERS * lookupChannelIndex(channel));
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}
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void configureTimerChannelCallback(TIM_TypeDef *tim, uint8_t channel, uint8_t reference, timerCCCallbackPtr *edgeCallback)
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{
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configureTimerChannelCallbacks(tim, channel, reference, edgeCallback, NULL);
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}
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void configureTimerChannelCallbacks(TIM_TypeDef *tim, uint8_t channel, uint8_t reference, timerCCCallbackPtr *edgeCallback, timerCCCallbackPtr *overflowCallback)
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{
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assert_param(IS_TIM_CHANNEL(channel));
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uint8_t timerConfigIndex = lookupTimerConfigIndex(tim, channel);
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if (timerConfigIndex >= MAX_TIMERS * CC_CHANNELS_PER_TIMER) {
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return;
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}
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timerConfig[timerConfigIndex].edgeCallback = edgeCallback;
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timerConfig[timerConfigIndex].overflowCallback = overflowCallback;
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timerConfig[timerConfigIndex].channel = channel;
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timerConfig[timerConfigIndex].reference = reference;
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}
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void configureTimerInputCaptureCompareChannel(TIM_TypeDef *tim, const uint8_t channel)
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{
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switch (channel) {
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case TIM_Channel_1:
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TIM_ITConfig(tim, TIM_IT_CC1, ENABLE);
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break;
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case TIM_Channel_2:
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TIM_ITConfig(tim, TIM_IT_CC2, ENABLE);
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break;
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case TIM_Channel_3:
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TIM_ITConfig(tim, TIM_IT_CC3, ENABLE);
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break;
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case TIM_Channel_4:
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TIM_ITConfig(tim, TIM_IT_CC4, ENABLE);
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break;
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}
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}
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void configureTimerCaptureCompareInterrupt(const timerHardware_t *timerHardwarePtr, uint8_t reference, timerCCCallbackPtr *edgeCallback, timerCCCallbackPtr *overflowCallback)
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{
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configureTimerChannelCallbacks(timerHardwarePtr->tim, timerHardwarePtr->channel, reference, edgeCallback, overflowCallback);
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configureTimerInputCaptureCompareChannel(timerHardwarePtr->tim, timerHardwarePtr->channel);
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if (overflowCallback) {
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TIM_ITConfig(timerHardwarePtr->tim, TIM_IT_Update, ENABLE);
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}
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return channel>>2;
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}
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void timerNVICConfigure(uint8_t irq)
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@ -330,12 +327,12 @@ void configTimeBase(TIM_TypeDef *tim, uint16_t period, uint8_t mhz)
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// Thus for 1Mhz: 72000000 / 1000000 = 72, 72 - 1 = 71 = TIM_Prescaler
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TIM_TimeBaseStructure.TIM_Prescaler = (SystemCoreClock / ((uint32_t)mhz * 1000000)) - 1;
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TIM_TimeBaseStructure.TIM_ClockDivision = 0;
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TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
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TIM_TimeBaseInit(tim, &TIM_TimeBaseStructure);
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}
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// old interface for PWM inputs. It should be replaced
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void timerConfigure(const timerHardware_t *timerHardwarePtr, uint16_t period, uint8_t mhz)
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{
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configTimeBase(timerHardwarePtr->tim, period, mhz);
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@ -343,108 +340,375 @@ void timerConfigure(const timerHardware_t *timerHardwarePtr, uint16_t period, ui
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timerNVICConfigure(timerHardwarePtr->irq);
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}
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timerConfig_t *findTimerConfig(TIM_TypeDef *tim, uint16_t channel)
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// allocate and configure timer channel. Timer priority is set to highest priority of channels
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void timerChInit(const timerHardware_t *timHw, channelType_t type, int irqPriority)
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{
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uint8_t timerConfigIndex = lookupTimerConfigIndex(tim, channel);
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return &(timerConfig[timerConfigIndex]);
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unsigned channel = timHw - timerHardware;
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if(channel >= USABLE_TIMER_CHANNEL_COUNT)
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return;
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timerChannelInfo[channel].type = type;
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unsigned timer = lookupTimerIndex(timHw->tim);
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if(timer >= USED_TIMER_COUNT)
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return;
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if(irqPriority < timerInfo[timer].priority) {
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// it would be better to set priority in the end, but current startup sequence is not ready
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configTimeBase(usedTimers[timer], 0, 1);
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TIM_Cmd(usedTimers[timer], ENABLE);
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NVIC_InitTypeDef NVIC_InitStructure;
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NVIC_InitStructure.NVIC_IRQChannel = timHw->irq;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(irqPriority);
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(irqPriority);
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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timerInfo[timer].priority = irqPriority;
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}
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}
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static void timCCxHandler(TIM_TypeDef *tim)
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void timerChCCHandlerInit(timerCCHandlerRec_t *self, timerCCHandlerCallback *fn)
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{
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captureCompare_t capture;
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timerConfig_t *timerConfig;
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uint8_t channel;
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uint8_t channelIndex;
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self->fn = fn;
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}
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if (TIM_GetITStatus(tim, TIM_IT_Update) == SET) {
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TIM_ClearITPendingBit(tim, TIM_IT_Update);
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capture = tim->ARR;
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void timerChOvrHandlerInit(timerOvrHandlerRec_t *self, timerOvrHandlerCallback *fn)
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{
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self->fn = fn;
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self->next = NULL;
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}
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for (channelIndex = 0; channelIndex < CC_CHANNELS_PER_TIMER; channelIndex++) {
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channel = channels[channelIndex];
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timerConfig = findTimerConfig(tim, channel);
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if (!timerConfig->overflowCallback) {
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continue;
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// update overflow callback list
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// some synchronization mechanism is neccesary to avoid disturbing other channels (BASEPRI used now)
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static void timerChConfig_UpdateOverflow(timerConfig_t *cfg, TIM_TypeDef* tim) {
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timerOvrHandlerRec_t **chain = &cfg->overflowCallbackActive;
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ATOMIC_BLOCK(NVIC_PRIO_TIMER) {
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for(int i = 0; i < CC_CHANNELS_PER_TIMER; i++)
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if(cfg->overflowCallback[i]) {
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*chain = cfg->overflowCallback[i];
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chain = &cfg->overflowCallback[i]->next;
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}
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timerConfig->overflowCallback(timerConfig->reference, capture);
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}
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*chain = NULL;
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}
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// enable or disable IRQ
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TIM_ITConfig(tim, TIM_IT_Update, cfg->overflowCallbackActive ? ENABLE : DISABLE);
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}
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// config edge and overflow callback for channel. Try to avoid overflowCallback, it is a bit expensive
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void timerChConfigCallbacks(const timerHardware_t* timHw, timerCCHandlerRec_t *edgeCallback, timerOvrHandlerRec_t *overflowCallback)
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{
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uint8_t timerIndex = lookupTimerIndex(timHw->tim);
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if (timerIndex >= USED_TIMER_COUNT) {
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return;
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}
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uint8_t channelIndex = lookupChannelIndex(timHw->channel);
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if(edgeCallback == NULL) // disable irq before changing callback to NULL
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TIM_ITConfig(timHw->tim, TIM_IT_CCx(timHw->channel), DISABLE);
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// setup callback info
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timerConfig[timerIndex].edgeCallback[channelIndex] = edgeCallback;
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timerConfig[timerIndex].overflowCallback[channelIndex] = overflowCallback;
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// enable channel IRQ
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if(edgeCallback)
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TIM_ITConfig(timHw->tim, TIM_IT_CCx(timHw->channel), ENABLE);
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timerChConfig_UpdateOverflow(&timerConfig[timerIndex], timHw->tim);
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}
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// configure callbacks for pair of channels (1+2 or 3+4).
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// Hi(2,4) and Lo(1,3) callbacks are specified, it is not important which timHw channel is used.
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// This is intended for dual capture mode (each channel handles one transition)
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void timerChConfigCallbacksDual(const timerHardware_t* timHw, timerCCHandlerRec_t *edgeCallbackLo, timerCCHandlerRec_t *edgeCallbackHi, timerOvrHandlerRec_t *overflowCallback)
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{
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uint8_t timerIndex = lookupTimerIndex(timHw->tim);
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if (timerIndex >= USED_TIMER_COUNT) {
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return;
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}
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uint16_t chLo = timHw->channel & ~TIM_Channel_2; // lower channel
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uint16_t chHi = timHw->channel | TIM_Channel_2; // upper channel
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uint8_t channelIndex = lookupChannelIndex(chLo); // get index of lower channel
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if(edgeCallbackLo == NULL) // disable irq before changing setting callback to NULL
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TIM_ITConfig(timHw->tim, TIM_IT_CCx(chLo), DISABLE);
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if(edgeCallbackHi == NULL) // disable irq before changing setting callback to NULL
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TIM_ITConfig(timHw->tim, TIM_IT_CCx(chHi), DISABLE);
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// setup callback info
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||||
timerConfig[timerIndex].edgeCallback[channelIndex] = edgeCallbackLo;
|
||||
timerConfig[timerIndex].edgeCallback[channelIndex + 1] = edgeCallbackHi;
|
||||
timerConfig[timerIndex].overflowCallback[channelIndex] = overflowCallback;
|
||||
timerConfig[timerIndex].overflowCallback[channelIndex + 1] = NULL;
|
||||
|
||||
// enable channel IRQs
|
||||
if(edgeCallbackLo) {
|
||||
TIM_ClearFlag(timHw->tim, TIM_IT_CCx(chLo));
|
||||
TIM_ITConfig(timHw->tim, TIM_IT_CCx(chLo), ENABLE);
|
||||
}
|
||||
if(edgeCallbackHi) {
|
||||
TIM_ClearFlag(timHw->tim, TIM_IT_CCx(chHi));
|
||||
TIM_ITConfig(timHw->tim, TIM_IT_CCx(chHi), ENABLE);
|
||||
}
|
||||
|
||||
for (channelIndex = 0; channelIndex < CC_CHANNELS_PER_TIMER; channelIndex++) {
|
||||
channel = channels[channelIndex];
|
||||
timerChConfig_UpdateOverflow(&timerConfig[timerIndex], timHw->tim);
|
||||
}
|
||||
|
||||
if (channel == TIM_Channel_1 && TIM_GetITStatus(tim, TIM_IT_CC1) == SET) {
|
||||
TIM_ClearITPendingBit(tim, TIM_IT_CC1);
|
||||
// enable/disable IRQ for low channel in dual configuration
|
||||
void timerChITConfigDualLo(const timerHardware_t* timHw, FunctionalState newState) {
|
||||
TIM_ITConfig(timHw->tim, TIM_IT_CCx(timHw->channel&~TIM_Channel_2), newState);
|
||||
}
|
||||
|
||||
timerConfig = findTimerConfig(tim, TIM_Channel_1);
|
||||
capture = TIM_GetCapture1(tim);
|
||||
} else if (channel == TIM_Channel_2 && TIM_GetITStatus(tim, TIM_IT_CC2) == SET) {
|
||||
TIM_ClearITPendingBit(tim, TIM_IT_CC2);
|
||||
// enable or disable IRQ
|
||||
void timerChITConfig(const timerHardware_t* timHw, FunctionalState newState)
|
||||
{
|
||||
TIM_ITConfig(timHw->tim, TIM_IT_CCx(timHw->channel), newState);
|
||||
}
|
||||
|
||||
timerConfig = findTimerConfig(tim, TIM_Channel_2);
|
||||
capture = TIM_GetCapture2(tim);
|
||||
} else if (channel == TIM_Channel_3 && TIM_GetITStatus(tim, TIM_IT_CC3) == SET) {
|
||||
TIM_ClearITPendingBit(tim, TIM_IT_CC3);
|
||||
// clear Compare/Capture flag for channel
|
||||
void timerChClearCCFlag(const timerHardware_t* timHw)
|
||||
{
|
||||
TIM_ClearFlag(timHw->tim, TIM_IT_CCx(timHw->channel));
|
||||
}
|
||||
|
||||
timerConfig = findTimerConfig(tim, TIM_Channel_3);
|
||||
capture = TIM_GetCapture3(tim);
|
||||
} else if (channel == TIM_Channel_4 && TIM_GetITStatus(tim, TIM_IT_CC4) == SET) {
|
||||
TIM_ClearITPendingBit(tim, TIM_IT_CC4);
|
||||
// configure timer channel GPIO mode
|
||||
void timerChConfigGPIO(const timerHardware_t* timHw, GPIO_Mode mode)
|
||||
{
|
||||
gpio_config_t cfg;
|
||||
|
||||
timerConfig = findTimerConfig(tim, TIM_Channel_4);
|
||||
capture = TIM_GetCapture4(tim);
|
||||
} else {
|
||||
continue; // avoid uninitialised variable dereference
|
||||
}
|
||||
cfg.pin = timHw->pin;
|
||||
cfg.mode = mode;
|
||||
cfg.speed = Speed_2MHz;
|
||||
gpioInit(timHw->gpio, &cfg);
|
||||
}
|
||||
|
||||
if (!timerConfig->edgeCallback) {
|
||||
continue;
|
||||
}
|
||||
timerConfig->edgeCallback(timerConfig->reference, capture);
|
||||
// calculate input filter constant
|
||||
// TODO - we should probably setup DTS to higher value to allow reasonable input filtering
|
||||
// - notice that prescaler[0] does use DTS for sampling - the sequence won't be monotonous anymore
|
||||
static unsigned getFilter(unsigned ticks)
|
||||
{
|
||||
static const unsigned ftab[16] = {
|
||||
1*1, // fDTS !
|
||||
1*2, 1*4, 1*8, // fCK_INT
|
||||
2*6, 2*8, // fDTS/2
|
||||
4*6, 4*8,
|
||||
8*6, 8*8,
|
||||
16*5, 16*6, 16*8,
|
||||
32*5, 32*6, 32*8
|
||||
};
|
||||
for(unsigned i = 1; i < ARRAYLEN(ftab); i++)
|
||||
if(ftab[i] > ticks)
|
||||
return i - 1;
|
||||
return 0x0f;
|
||||
}
|
||||
|
||||
// Configure input captupre
|
||||
void timerChConfigIC(const timerHardware_t* timHw, bool polarityRising, unsigned inputFilterTicks)
|
||||
{
|
||||
TIM_ICInitTypeDef TIM_ICInitStructure;
|
||||
|
||||
TIM_ICStructInit(&TIM_ICInitStructure);
|
||||
TIM_ICInitStructure.TIM_Channel = timHw->channel;
|
||||
TIM_ICInitStructure.TIM_ICPolarity = polarityRising ? TIM_ICPolarity_Rising : TIM_ICPolarity_Falling;
|
||||
TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
|
||||
TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
|
||||
TIM_ICInitStructure.TIM_ICFilter = getFilter(inputFilterTicks);
|
||||
|
||||
TIM_ICInit(timHw->tim, &TIM_ICInitStructure);
|
||||
}
|
||||
|
||||
// configure dual channel input channel for capture
|
||||
// polarity is for first Low channel (capture order is always Lo - Hi)
|
||||
void timerChConfigICDual(const timerHardware_t* timHw, bool polarityRising, unsigned inputFilterTicks)
|
||||
{
|
||||
TIM_ICInitTypeDef TIM_ICInitStructure;
|
||||
bool directRising = (timHw->channel & TIM_Channel_2) ? !polarityRising : polarityRising;
|
||||
// configure direct channel
|
||||
TIM_ICStructInit(&TIM_ICInitStructure);
|
||||
|
||||
TIM_ICInitStructure.TIM_Channel = timHw->channel;
|
||||
TIM_ICInitStructure.TIM_ICPolarity = directRising ? TIM_ICPolarity_Rising : TIM_ICPolarity_Falling;
|
||||
TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
|
||||
TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
|
||||
TIM_ICInitStructure.TIM_ICFilter = getFilter(inputFilterTicks);
|
||||
TIM_ICInit(timHw->tim, &TIM_ICInitStructure);
|
||||
// configure indirect channel
|
||||
TIM_ICInitStructure.TIM_Channel = timHw->channel ^ TIM_Channel_2; // get opposite channel no
|
||||
TIM_ICInitStructure.TIM_ICPolarity = directRising ? TIM_ICPolarity_Falling : TIM_ICPolarity_Rising;
|
||||
TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_IndirectTI;
|
||||
TIM_ICInit(timHw->tim, &TIM_ICInitStructure);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void timerChICPolarity(const timerHardware_t* timHw, bool polarityRising)
|
||||
{
|
||||
timCCER_t tmpccer = timHw->tim->CCER;
|
||||
tmpccer &= ~(TIM_CCER_CC1P << timHw->channel);
|
||||
tmpccer |= polarityRising ? (TIM_ICPolarity_Rising << timHw->channel) : (TIM_ICPolarity_Falling << timHw->channel);
|
||||
timHw->tim->CCER = tmpccer;
|
||||
}
|
||||
|
||||
volatile timCCR_t* timerChCCRHi(const timerHardware_t* timHw)
|
||||
{
|
||||
return (volatile timCCR_t*)((volatile char*)&timHw->tim->CCR1 + (timHw->channel | TIM_Channel_2));
|
||||
}
|
||||
|
||||
volatile timCCR_t* timerChCCRLo(const timerHardware_t* timHw)
|
||||
{
|
||||
return (volatile timCCR_t*)((volatile char*)&timHw->tim->CCR1 + (timHw->channel & ~TIM_Channel_2));
|
||||
}
|
||||
|
||||
|
||||
|
||||
volatile timCCR_t* timerChCCR(const timerHardware_t* timHw)
|
||||
{
|
||||
return (volatile timCCR_t*)((volatile char*)&timHw->tim->CCR1 + timHw->channel);
|
||||
}
|
||||
|
||||
void timerChConfigOC(const timerHardware_t* timHw, bool outEnable, bool stateHigh)
|
||||
{
|
||||
TIM_OCInitTypeDef TIM_OCInitStructure;
|
||||
|
||||
TIM_OCStructInit(&TIM_OCInitStructure);
|
||||
if(outEnable) {
|
||||
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Inactive;
|
||||
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
|
||||
TIM_OCInitStructure.TIM_OCPolarity = stateHigh ? TIM_OCPolarity_High : TIM_OCPolarity_Low;
|
||||
} else {
|
||||
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
|
||||
}
|
||||
|
||||
switch (timHw->channel) {
|
||||
case TIM_Channel_1:
|
||||
TIM_OC1Init(timHw->tim, &TIM_OCInitStructure);
|
||||
TIM_OC1PreloadConfig(timHw->tim, TIM_OCPreload_Disable);
|
||||
break;
|
||||
case TIM_Channel_2:
|
||||
TIM_OC2Init(timHw->tim, &TIM_OCInitStructure);
|
||||
TIM_OC2PreloadConfig(timHw->tim, TIM_OCPreload_Disable);
|
||||
break;
|
||||
case TIM_Channel_3:
|
||||
TIM_OC3Init(timHw->tim, &TIM_OCInitStructure);
|
||||
TIM_OC3PreloadConfig(timHw->tim, TIM_OCPreload_Disable);
|
||||
break;
|
||||
case TIM_Channel_4:
|
||||
TIM_OC4Init(timHw->tim, &TIM_OCInitStructure);
|
||||
TIM_OC4PreloadConfig(timHw->tim, TIM_OCPreload_Disable);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void TIM1_CC_IRQHandler(void)
|
||||
|
||||
|
||||
static void timCCxHandler(TIM_TypeDef *tim, timerConfig_t* timerConfig)
|
||||
{
|
||||
timCCxHandler(TIM1);
|
||||
uint16_t capture;
|
||||
unsigned tim_status;
|
||||
tim_status = tim->SR & tim->DIER;
|
||||
#if 1
|
||||
while(tim_status) { // flags will be cleared by reading CCR in dual capture, make sure we call handler correctly
|
||||
unsigned bit = __builtin_clz(tim_status);
|
||||
unsigned mask = ~(0x80000000 >> bit);
|
||||
tim->SR = mask;
|
||||
tim_status &= mask;
|
||||
switch(bit) {
|
||||
case __builtin_clz(TIM_IT_Update):
|
||||
capture = tim->ARR;
|
||||
timerOvrHandlerRec_t *cb = timerConfig->overflowCallbackActive;
|
||||
while(cb) {
|
||||
cb->fn(cb, capture);
|
||||
cb = cb->next;
|
||||
}
|
||||
break;
|
||||
case __builtin_clz(TIM_IT_CC1):
|
||||
timerConfig->edgeCallback[0]->fn(timerConfig->edgeCallback[0], tim->CCR1);
|
||||
break;
|
||||
case __builtin_clz(TIM_IT_CC2):
|
||||
timerConfig->edgeCallback[1]->fn(timerConfig->edgeCallback[1], tim->CCR2);
|
||||
break;
|
||||
case __builtin_clz(TIM_IT_CC3):
|
||||
timerConfig->edgeCallback[2]->fn(timerConfig->edgeCallback[2], tim->CCR3);
|
||||
break;
|
||||
case __builtin_clz(TIM_IT_CC4):
|
||||
timerConfig->edgeCallback[3]->fn(timerConfig->edgeCallback[3], tim->CCR4);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#else
|
||||
if (tim_status & (int)TIM_IT_Update) {
|
||||
tim->SR = ~TIM_IT_Update;
|
||||
capture = tim->ARR;
|
||||
timerOvrHandlerRec_t *cb = timerConfig->overflowCallbackActive;
|
||||
while(cb) {
|
||||
cb->fn(cb, capture);
|
||||
cb = cb->next;
|
||||
}
|
||||
}
|
||||
if (tim_status & (int)TIM_IT_CC1) {
|
||||
tim->SR = ~TIM_IT_CC1;
|
||||
timerConfig->edgeCallback[0]->fn(timerConfig->edgeCallback[0], tim->CCR1);
|
||||
}
|
||||
if (tim_status & (int)TIM_IT_CC2) {
|
||||
tim->SR = ~TIM_IT_CC2;
|
||||
timerConfig->edgeCallback[2]->fn(timerConfig->edgeCallback[1], tim->CCR2);
|
||||
}
|
||||
if (tim_status & (int)TIM_IT_CC3) {
|
||||
tim->SR = ~TIM_IT_CC3;
|
||||
timerConfig->edgeCallback[2]->fn(timerConfig->edgeCallback[2], tim->CCR3);
|
||||
}
|
||||
if (tim_status & (int)TIM_IT_CC4) {
|
||||
tim->SR = ~TIM_IT_CC4;
|
||||
timerConfig->edgeCallback[3]->fn(timerConfig->edgeCallback[3], tim->CCR4);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void TIM2_IRQHandler(void)
|
||||
{
|
||||
timCCxHandler(TIM2);
|
||||
}
|
||||
// handler for shared interrupts when both timers need to check status bits
|
||||
#define _TIM_IRQ_HANDLER2(name, i, j) \
|
||||
void name(void) \
|
||||
{ \
|
||||
timCCxHandler(TIM ## i, &timerConfig[TIMER_INDEX(i)]); \
|
||||
timCCxHandler(TIM ## j, &timerConfig[TIMER_INDEX(j)]); \
|
||||
} struct dummy
|
||||
|
||||
void TIM3_IRQHandler(void)
|
||||
{
|
||||
timCCxHandler(TIM3);
|
||||
}
|
||||
#define _TIM_IRQ_HANDLER(name, i) \
|
||||
void name(void) \
|
||||
{ \
|
||||
timCCxHandler(TIM ## i, &timerConfig[TIMER_INDEX(i)]); \
|
||||
} struct dummy
|
||||
|
||||
void TIM4_IRQHandler(void)
|
||||
{
|
||||
timCCxHandler(TIM4);
|
||||
}
|
||||
|
||||
#if defined(STM32F303) || defined(STM32F3DISCOVERY)
|
||||
void TIM8_CC_IRQHandler(void)
|
||||
{
|
||||
timCCxHandler(TIM8);
|
||||
}
|
||||
|
||||
void TIM1_BRK_TIM15_IRQHandler(void)
|
||||
{
|
||||
timCCxHandler(TIM15);
|
||||
}
|
||||
|
||||
void TIM1_UP_TIM16_IRQHandler(void)
|
||||
{
|
||||
timCCxHandler(TIM16);
|
||||
}
|
||||
|
||||
void TIM1_TRG_COM_TIM17_IRQHandler(void)
|
||||
{
|
||||
timCCxHandler(TIM17);
|
||||
}
|
||||
#if USED_TIMERS & TIM_N(1)
|
||||
_TIM_IRQ_HANDLER(TIM1_CC_IRQHandler, 1);
|
||||
# if defined(STM32F10X)
|
||||
_TIM_IRQ_HANDLER(TIM1_UP_IRQHandler, 1); // timer can't be shared
|
||||
# endif
|
||||
# ifdef STM32F303xC
|
||||
# if USED_TIMERS & TIM_N(16)
|
||||
_TIM_IRQ_HANDLER2(TIM1_UP_TIM16_IRQHandler, 1, 16); // both timers are in use
|
||||
# else
|
||||
_TIM_IRQ_HANDLER(TIM1_UP_TIM16_IRQHandler, 1); // timer16 is not used
|
||||
# endif
|
||||
# endif
|
||||
#endif
|
||||
#if USED_TIMERS & TIM_N(2)
|
||||
_TIM_IRQ_HANDLER(TIM2_IRQHandler, 2);
|
||||
#endif
|
||||
#if USED_TIMERS & TIM_N(3)
|
||||
_TIM_IRQ_HANDLER(TIM3_IRQHandler, 3);
|
||||
#endif
|
||||
#if USED_TIMERS & TIM_N(4)
|
||||
_TIM_IRQ_HANDLER(TIM4_IRQHandler, 4);
|
||||
#endif
|
||||
#if USED_TIMERS & TIM_N(8)
|
||||
_TIM_IRQ_HANDLER(TIM8_CC_IRQHandler, 8);
|
||||
#endif
|
||||
#if USED_TIMERS & TIM_N(15)
|
||||
_TIM_IRQ_HANDLER(TIM1_BRK_TIM15_IRQHandler, 15);
|
||||
#endif
|
||||
#if defined(STM32F303xC) && ((USED_TIMERS & (TIM_N(1)|TIM_N(16))) == (TIM_N(16)))
|
||||
_TIM_IRQ_HANDLER(TIM1_UP_TIM16_IRQHandler, 16); // only timer16 is used, not timer1
|
||||
#endif
|
||||
#if USED_TIMERS & TIM_N(17)
|
||||
_TIM_IRQ_HANDLER(TIM1_TRG_COM_TIM17_IRQHandler, 17);
|
||||
#endif
|
||||
|
||||
void timerInit(void)
|
||||
|
|
@ -482,4 +746,41 @@ void timerInit(void)
|
|||
#endif
|
||||
#endif
|
||||
|
||||
// initialize timer channel structures
|
||||
for(int i = 0; i < USABLE_TIMER_CHANNEL_COUNT; i++) {
|
||||
timerChannelInfo[i].type = TYPE_FREE;
|
||||
}
|
||||
for(int i = 0; i < USED_TIMER_COUNT; i++) {
|
||||
timerInfo[i].priority = ~0;
|
||||
}
|
||||
}
|
||||
|
||||
// finish configuring timers after allocation phase
|
||||
// start timers
|
||||
// TODO - Work in progress - initialization routine must be modified/verified to start correctly without timers
|
||||
void timerStart(void)
|
||||
{
|
||||
#if 0
|
||||
for(unsigned timer = 0; timer < USED_TIMER_COUNT; timer++) {
|
||||
int priority = -1;
|
||||
int irq = -1;
|
||||
for(unsigned hwc = 0; hwc < USABLE_TIMER_CHANNEL_COUNT; hwc++)
|
||||
if((timerChannelInfo[hwc].type != TYPE_FREE) && (timerHardware[hwc].tim == usedTimers[timer])) {
|
||||
// TODO - move IRQ to timer info
|
||||
irq = timerHardware[hwc].irq;
|
||||
}
|
||||
// TODO - aggregate required timer paramaters
|
||||
configTimeBase(usedTimers[timer], 0, 1);
|
||||
TIM_Cmd(usedTimers[timer], ENABLE);
|
||||
if(priority >= 0) { // maybe none of the channels was configured
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
NVIC_InitStructure.NVIC_IRQChannel = irq;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_SPLIT_PRIORITY_BASE(priority);
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_SPLIT_PRIORITY_SUB(priority);
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue