mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-26 01:35:41 +03:00
parent
bc773d8a49
commit
ab2088dc24
5 changed files with 64 additions and 58 deletions
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@ -48,6 +48,8 @@
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#define SPI3_MOSI_PIN PC12
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#define SPI3_MOSI_PIN PC12
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#define USE_FLASH_M25P16
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#define USE_FLASH_M25P16
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#define FLASH_CS_PIN PB3
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#define FLASH_SPI_INSTANCE SPI3
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#define I2C1_SCL_PIN PB8
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#define I2C1_SCL_PIN PB8
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#define I2C1_SDA_PIN PB9
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#define I2C1_SDA_PIN PB9
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@ -55,6 +57,8 @@
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#define I2C2_SCL_PIN PB10
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#define I2C2_SCL_PIN PB10
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#define I2C2_SDA_PIN PB11
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#define I2C2_SDA_PIN PB11
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#define BARO_I2C_INSTANCE I2C2
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#define MAG_I2C_INSTANCE I2C1
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#define USE_MAG
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#define BARO_I2C_INSTANCE I2C1
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#define USE_BARO
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#define USE_BARO
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#define USE_BARO_MS5611
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@ -36,6 +36,9 @@
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#include "drivers/io.h"
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#include "drivers/io.h"
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#include "drivers/rcc.h"
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#include "drivers/rcc.h"
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// Use DMA if possible if this many bytes are to be transferred
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#define SPI_DMA_THRESHOLD 8
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static spi_init_type defaultInit = {
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static spi_init_type defaultInit = {
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.master_slave_mode = SPI_MODE_MASTER,
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.master_slave_mode = SPI_MODE_MASTER,
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.transmission_mode = SPI_TRANSMIT_FULL_DUPLEX,
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.transmission_mode = SPI_TRANSMIT_FULL_DUPLEX,
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@ -143,7 +146,7 @@ static bool spiInternalReadWriteBufPolled(spi_type *instance, const uint8_t *txD
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while (spi_i2s_flag_get(instance, SPI_I2S_RDBF_FLAG) == RESET);
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while (spi_i2s_flag_get(instance, SPI_I2S_RDBF_FLAG) == RESET);
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b=spi_i2s_data_receive(instance);
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b = (uint8_t)spi_i2s_data_receive(instance);
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if (rxData) {
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if (rxData) {
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*(rxData++) = b;
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*(rxData++) = b;
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@ -326,65 +329,70 @@ void spiSequenceStart(const extDevice_t *dev)
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spi_enable(instance, TRUE);
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spi_enable(instance, TRUE);
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// Check that any there are no attempts to DMA to/from CCD SRAM
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// Count segments
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for (busSegment_t *checkSegment = (busSegment_t *)bus->curSegment; checkSegment->len; checkSegment++) {
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for (busSegment_t *checkSegment = (busSegment_t *)bus->curSegment; checkSegment->len; checkSegment++) {
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// Check there is no receive data as only transmit DMA is available
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if (((checkSegment->u.buffers.rxData) && (IS_CCM(checkSegment->u.buffers.rxData) ||
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(bus->dmaRx == (dmaChannelDescriptor_t *)NULL))) ||
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((checkSegment->u.buffers.txData) && IS_CCM(checkSegment->u.buffers.txData))) {
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dmaSafe = false;
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break;
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}
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// Note that these counts are only valid if dmaSafe is true
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// Note that these counts are only valid if dmaSafe is true
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segmentCount++;
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segmentCount++;
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xferLen += checkSegment->len;
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xferLen += checkSegment->len;
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}
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}
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// Use DMA if possible
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// Use DMA if possible
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// If there are more than one segments, or a single segment with negateCS negated then force DMA irrespective of length
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// If there are more than one segments, or a single segment with negateCS negated in the list terminator then force DMA irrespective of length
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if (bus->useDMA && dmaSafe && ((segmentCount > 1) || (xferLen >= 8) || !bus->curSegment->negateCS)) {
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if (bus->useDMA && dmaSafe && ((segmentCount > 1) ||
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(xferLen >= SPI_DMA_THRESHOLD) ||
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!bus->curSegment[segmentCount].negateCS)) {
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// Intialise the init structures for the first transfer
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spiInternalInitStream(dev, false);
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spiInternalInitStream(dev, false);
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// Assert Chip Select
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IOLo(dev->busType_u.spi.csnPin);
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IOLo(dev->busType_u.spi.csnPin);
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// Start the transfers
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spiInternalStartDMA(dev);
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spiInternalStartDMA(dev);
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} else {
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} else {
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busSegment_t *lastSegment = NULL;
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busSegment_t *lastSegment = NULL;
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bool segmentComplete;
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// Manually work through the segment list performing a transfer for each
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while (bus->curSegment->len) {
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while (bus->curSegment->len) {
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if (!lastSegment || lastSegment->negateCS) {
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if (!lastSegment || lastSegment->negateCS) {
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// Assert Chip Select if necessary - it's costly so only do so if necessary
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IOLo(dev->busType_u.spi.csnPin);
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IOLo(dev->busType_u.spi.csnPin);
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}
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}
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spiInternalReadWriteBufPolled(
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spiInternalReadWriteBufPolled(bus->busType_u.spi.instance,
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bus->busType_u.spi.instance,
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bus->curSegment->u.buffers.txData,
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bus->curSegment->u.buffers.txData,
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bus->curSegment->u.buffers.rxData,
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bus->curSegment->u.buffers.rxData,
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bus->curSegment->len
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bus->curSegment->len);
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);
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if (bus->curSegment->negateCS) {
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if (bus->curSegment->negateCS) {
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// Negate Chip Select
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IOHi(dev->busType_u.spi.csnPin);
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IOHi(dev->busType_u.spi.csnPin);
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}
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}
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segmentComplete = true;
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if (bus->curSegment->callback) {
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if (bus->curSegment->callback) {
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switch(bus->curSegment->callback(dev->callbackArg)) {
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switch(bus->curSegment->callback(dev->callbackArg)) {
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case BUS_BUSY:
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case BUS_BUSY:
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bus->curSegment--;
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// Repeat the last DMA segment
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segmentComplete = false;
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break;
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break;
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case BUS_ABORT:
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case BUS_ABORT:
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bus->curSegment = (busSegment_t *)BUS_SPI_FREE;
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bus->curSegment = (busSegment_t *)BUS_SPI_FREE;
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segmentComplete = false;
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return;
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return;
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case BUS_READY:
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case BUS_READY:
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default:
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default:
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// Advance to the next DMA segment
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break;
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break;
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}
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}
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}
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}
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if (segmentComplete) {
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lastSegment = (busSegment_t *)bus->curSegment;
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lastSegment = (busSegment_t *)bus->curSegment;
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bus->curSegment++;
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bus->curSegment++;
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}
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}
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if (lastSegment && !lastSegment->negateCS) {
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IOHi(dev->busType_u.spi.csnPin);
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}
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}
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// If a following transaction has been linked, start it
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// If a following transaction has been linked, start it
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@ -82,9 +82,9 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
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#define DEFAULT_CPU_OVERCLOCK 0
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#define DEFAULT_CPU_OVERCLOCK 0
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#define FAST_IRQ_HANDLER
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#define FAST_IRQ_HANDLER
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#define DMA_DATA_ZERO_INIT __attribute__ ((section(".dmaram_bss"), aligned(32)))
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#define DMA_DATA_ZERO_INIT
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#define DMA_DATA __attribute__ ((section(".dmaram_data"), aligned(32)))
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#define DMA_DATA
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#define STATIC_DMA_DATA_AUTO static DMA_DATA
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#define STATIC_DMA_DATA_AUTO static
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#define DMA_RAM
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#define DMA_RAM
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#define DMA_RW_AXI
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#define DMA_RW_AXI
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@ -381,6 +381,7 @@ void spiSequenceStart(const extDevice_t *dev)
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spiInternalStartDMA(dev);
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spiInternalStartDMA(dev);
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} else {
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} else {
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busSegment_t *lastSegment = NULL;
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busSegment_t *lastSegment = NULL;
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bool segmentComplete;
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// Manually work through the segment list performing a transfer for each
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// Manually work through the segment list performing a transfer for each
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while (bus->curSegment->len) {
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while (bus->curSegment->len) {
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@ -400,15 +401,17 @@ void spiSequenceStart(const extDevice_t *dev)
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IOHi(dev->busType_u.spi.csnPin);
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IOHi(dev->busType_u.spi.csnPin);
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}
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}
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segmentComplete = true;
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if (bus->curSegment->callback) {
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if (bus->curSegment->callback) {
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switch(bus->curSegment->callback(dev->callbackArg)) {
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switch(bus->curSegment->callback(dev->callbackArg)) {
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case BUS_BUSY:
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case BUS_BUSY:
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// Repeat the last DMA segment
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// Repeat the last DMA segment
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bus->curSegment--;
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segmentComplete = false;
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break;
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break;
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case BUS_ABORT:
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case BUS_ABORT:
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bus->curSegment = (busSegment_t *)BUS_SPI_FREE;
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bus->curSegment = (busSegment_t *)BUS_SPI_FREE;
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segmentComplete = false;
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return;
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return;
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case BUS_READY:
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case BUS_READY:
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@ -417,9 +420,11 @@ void spiSequenceStart(const extDevice_t *dev)
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break;
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break;
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}
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}
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}
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}
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if (segmentComplete) {
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lastSegment = (busSegment_t *)bus->curSegment;
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lastSegment = (busSegment_t *)bus->curSegment;
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bus->curSegment++;
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bus->curSegment++;
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}
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}
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}
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// If a following transaction has been linked, start it
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// If a following transaction has been linked, start it
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if (bus->curSegment->u.link.dev) {
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if (bus->curSegment->u.link.dev) {
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@ -72,18 +72,7 @@
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#undef USE_RX_SPI
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#undef USE_RX_SPI
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#undef USE_RX_CC2500
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#undef USE_RX_CC2500
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#undef USE_RX_EXPRESSLRS
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#undef USE_RX_EXPRESSLRS
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//#undef USE_CMS
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//#undef USE_OSD
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#undef USE_BLACKBOX
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//#undef USE_SDCARD
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//#undef USE_BARO
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//#undef USE_MAG
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#undef USE_SERIAL_4WAY_BLHELI_BOOTLOADER
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#undef USE_SERIAL_4WAY_BLHELI_BOOTLOADER
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#undef USE_SERIAL_4WAY_SK_BOOTLOADER
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#undef USE_SERIAL_4WAY_SK_BOOTLOADER
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// remove all flash
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#undef USE_FLASH
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#undef USE_FLASHFS
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#undef USE_FLASH_CHIP
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#define FLASH_PAGE_SIZE ((uint32_t)0x1000) // 4K sectors
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#define FLASH_PAGE_SIZE ((uint32_t)0x1000) // 4K sectors
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