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Add PB0 to AT32 SPI3 mosi pins (#14324)

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Mark Haslinghuis 2025-04-02 19:16:36 +02:00 • committed by GitHub
parent 472cc2b84a
commit ab5449c9b1
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2 changed files with 2 additions and 1 deletions
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2
src/platform/AT32/platform_mcu.h
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@ -139,7 +139,7 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define CHECK_SPI_RX_DATA_AVAILABLE(instance) LL_SPI_IsActiveFlag_RXNE(instance) #define CHECK_SPI_RX_DATA_AVAILABLE(instance) LL_SPI_IsActiveFlag_RXNE(instance)
#define SPI_RX_DATA_REGISTER(base) ((base)->DR) #define SPI_RX_DATA_REGISTER(base) ((base)->DR)
#define MAX_SPI_PIN_SEL 4 #define MAX_SPI_PIN_SEL 5
#define UART_TX_BUFFER_ATTRIBUTE // NONE #define UART_TX_BUFFER_ATTRIBUTE // NONE
#define UART_RX_BUFFER_ATTRIBUTE // NONE #define UART_RX_BUFFER_ATTRIBUTE // NONE

1
src/platform/common/stm32/bus_spi_pinconfig.c
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@ -403,6 +403,7 @@ const spiHardware_t spiHardware[] = {
{ DEFIO_TAG_E(PC11), GPIO_MUX_6}, { DEFIO_TAG_E(PC11), GPIO_MUX_6},
}, },
.mosiPins = { .mosiPins = {
{ DEFIO_TAG_E(PB0), GPIO_MUX_7},
{ DEFIO_TAG_E(PB2), GPIO_MUX_7}, { DEFIO_TAG_E(PB2), GPIO_MUX_7},
{ DEFIO_TAG_E(PB5), GPIO_MUX_6}, { DEFIO_TAG_E(PB5), GPIO_MUX_6},
{ DEFIO_TAG_E(PC12), GPIO_MUX_6}, { DEFIO_TAG_E(PC12), GPIO_MUX_6},