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Adjustable OC for F405 and F411

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This commit is contained in:
Andrey Mironov 2018-02-17 14:12:16 +03:00
parent e596f9a7d1
commit ac26c975dd
11 changed files with 93 additions and 47 deletions
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67
src/main/target/system_stm32f4xx.c
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@ -502,21 +502,74 @@ void SystemInit(void)
#endif
}
typedef struct pllConfig_s {
uint16_t n;
uint16_t p;
uint16_t q;
} pllConfig_t;
static const pllConfig_t overclockLevels[] = {
{ PLL_N, PLL_P, PLL_Q }, // default
#if defined(STM32F40_41xxx)
{ 384, 2, 8 }, // 192 MHz
{ 432, 2, 9 }, // 216 MHz
{ 480, 2, 10 } // 240 MHz
#elif defined(STM32F411xE)
{ 432, 4, 9 }, // 108 MHz
{ 480, 4, 10 }, // 120 MHz
#endif
// XXX Doesn't work for F446 with this configuration.
// XXX Need to use smaller M to reduce N?
};
// 8 bytes of memory located at the very end of RAM, expected to be unoccupied
#define REQUEST_OVERCLOCK (*(__IO uint32_t *) 0x2001FFF8)
#define CURRENT_OVERCLOCK_LEVEL (*(__IO uint32_t *) 0x2001FFF4)
#define REQUEST_OVERCLOCK_MAGIC_COOKIE 0xBABEFACE
void SystemInitOC(void)
{
#if !defined(STM32F446xxx)
// XXX Doesn't work for F446 with this configuration.
// XXX Need to use smaller M to reduce N?
#ifdef STM32F411xE
if (REQUEST_OVERCLOCK_MAGIC_COOKIE == REQUEST_OVERCLOCK) {
#endif
const uint32_t overclockLevel = CURRENT_OVERCLOCK_LEVEL;
/* PLL setting for overclocking */
pll_n = PLL_N_OC;
pll_p = PLL_P_OC;
pll_q = PLL_Q_OC;
/* PLL setting for overclocking */
if (overclockLevel < ARRAYLEN(overclockLevels)) {
const pllConfig_t * const pll = overclockLevels + overclockLevel;
pll_n = pll->n;
pll_p = pll->p;
pll_q = pll->q;
}
#ifdef STM32F411xE
REQUEST_OVERCLOCK = 0;
}
#endif
SystemInit();
}
void OverclockRebootIfNecessary(uint32_t overclockLevel)
{
if (overclockLevel >= ARRAYLEN(overclockLevels)) {
return;
}
const pllConfig_t * const pll = overclockLevels + overclockLevel;
// Reboot to adjust overclock frequency
if (SystemCoreClock != (pll->n / pll->p) * 1000000) {
REQUEST_OVERCLOCK = REQUEST_OVERCLOCK_MAGIC_COOKIE;
CURRENT_OVERCLOCK_LEVEL = overclockLevel;
__disable_irq();
NVIC_SystemReset();
}
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can