mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-15 04:15:44 +03:00
Reworked reboot flags for F4 partially (#5193)
This commit is contained in:
parent
07cce64572
commit
aede46288b
13 changed files with 118 additions and 171 deletions
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@ -45,9 +45,9 @@ void failureMode(failureMode_e mode);
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// bootloader/IAP
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void systemReset(void);
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void systemResetToBootloader(void);
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void checkForBootLoaderRequest(void);
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bool isMPUSoftReset(void);
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void cycleCounterInit(void);
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void checkForBootLoaderRequest(void);
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void enableGPIOPowerUsageAndNoiseReductions(void);
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// current crystal frequency - 8 or 12MHz
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@ -39,18 +39,43 @@ void systemReset(void)
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NVIC_SystemReset();
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}
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PERSISTENT uint32_t bootloaderRequest = 0;
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#define BOOTLOADER_REQUEST_COOKIE 0xDEADBEEF
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void systemResetToBootloader(void)
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{
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if (mpuResetFn) {
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mpuResetFn();
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}
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*((uint32_t *)0x2001FFFC) = 0xDEADBEEF; // 128KB SRAM STM32F4XX
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bootloaderRequest = BOOTLOADER_REQUEST_COOKIE;
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__disable_irq();
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NVIC_SystemReset();
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}
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typedef void resetHandler_t(void);
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typedef struct isrVector_s {
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__I uint32_t stackEnd;
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resetHandler_t *resetHandler;
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} isrVector_t;
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void checkForBootLoaderRequest(void)
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{
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if (bootloaderRequest != BOOTLOADER_REQUEST_COOKIE) {
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return;
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}
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bootloaderRequest = 0;
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extern isrVector_t system_isr_vector_table_base;
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__set_MSP(system_isr_vector_table_base.stackEnd);
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system_isr_vector_table_base.resetHandler();
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while (1);
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}
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void enableGPIOPowerUsageAndNoiseReductions(void)
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{
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@ -160,8 +185,6 @@ bool isMPUSoftReset(void)
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void systemInit(void)
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{
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checkForBootLoaderRequest();
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SetSysClock();
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// Configure NVIC preempt/priority groups
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@ -185,19 +208,3 @@ void systemInit(void)
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// SysTick
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SysTick_Config(SystemCoreClock / 1000);
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}
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void(*bootJump)(void);
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void checkForBootLoaderRequest(void)
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{
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if (*((uint32_t *)0x2001FFFC) == 0xDEADBEEF) {
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*((uint32_t *)0x2001FFFC) = 0x0;
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__enable_irq();
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__set_MSP(*((uint32_t *)0x1FFF0000));
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bootJump = (void(*)(void))(*((uint32_t *) 0x1FFF0004));
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bootJump();
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while (1);
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}
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}
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@ -79,21 +79,8 @@ Reset_Handler:
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str r1, [r0, #0x30]
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dsb
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// Check for bootloader reboot
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ldr r0, =0x2001FFFC // mj666
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ldr r1, =0xDEADBEEF // mj666
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ldr r2, [r0, #0] // mj666
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str r0, [r0, #0] // mj666
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cmp r2, r1 // mj666
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beq Reboot_Loader // mj666
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// Check for overclocking request
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ldr r0, =0x2001FFF8 // Faduf
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ldr r1, =0xBABEFACE // Faduf
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ldr r2, [r0, #0] // Faduf
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str r0, [r0, #0] // Faduf
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cmp r2, r1 // Faduf
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beq Boot_OC // Faduf
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// Defined in C code
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bl checkForBootLoaderRequest
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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@ -153,71 +140,6 @@ LoopMarkHeapStack:
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LoopForever:
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b LoopForever
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Boot_OC:
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInitOC
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CopyDataInitOC:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInitOC:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInitOC
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ldr r2, =_sbss
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b LoopFillZerobssOC
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/* Zero fill the bss segment. */
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FillZerobssOC:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobssOC:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobssOC
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/* Mark the heap and stack */
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ldr r2, =_heap_stack_begin
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b LoopMarkHeapStackOC
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MarkHeapStackOC:
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movs r3, 0xa5a5a5a5
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str r3, [r2], #4
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LoopMarkHeapStackOC:
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ldr r3, = _heap_stack_end
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cmp r2, r3
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bcc MarkHeapStackOC
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/*FPU settings*/
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ldr r0, =0xE000ED88 /* Enable CP10,CP11 */
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ldr r1,[r0]
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orr r1,r1,#(0xF << 20)
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str r1,[r0]
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/* Call the clock system intitialization function.*/
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/* Done in system_stm32f4xx.c */
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bl SystemInitOC
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/* Call the application's entry point.*/
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bl main
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bx lr
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Reboot_Loader: // mj666
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// Reboot to ROM // mj666
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ldr r0, =0x1FFF0000 // mj666
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ldr sp,[r0, #0] // mj666
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ldr r0,[r0, #4] // mj666
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bx r0 // mj666
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.size Reset_Handler, .-Reset_Handler
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/**
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@ -127,7 +127,7 @@ LoopMarkHeapStack:
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str r1,[r0]
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/* Call the clock system intitialization function.*/
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bl SystemInitOC
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bl SystemInit
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/* Call the application's entry point.*/
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bl main
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@ -102,6 +102,10 @@
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#define FAST_RAM
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#endif // USE_FAST_RAM
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#ifdef STM32F4
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// Data in RAM which is guaranteed to not be reset on hot reboot
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#define PERSISTENT __attribute__ ((section(".persistent_data"), aligned(4)))
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#endif
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#define USE_CLI
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#define USE_GYRO_REGISTER_DUMP // Adds gyroregisters command to cli to dump configured register values
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@ -26,6 +26,8 @@ MEMORY
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FLASH_CONFIG (r) : ORIGIN = 0x08004000, LENGTH = 16K
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FLASH1 (rx) : ORIGIN = 0x08008000, LENGTH = 992K
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SYSTEM_MEMORY (rx): ORIGIN = 0x1FFF0000, LENGTH = 29K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
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BACKUP_SRAM (rwx) : ORIGIN = 0x40024000, LENGTH = 4K
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@ -27,6 +27,8 @@ MEMORY
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FLASH_CONFIG (r): ORIGIN = 0x08008000, LENGTH = 16K
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FLASH1 (rx) : ORIGIN = 0x0800C000, LENGTH = 976K
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SYSTEM_MEMORY (rx): ORIGIN = 0x1FFF0000, LENGTH = 29K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
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MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
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@ -26,6 +26,8 @@ MEMORY
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FLASH_CONFIG (r) : ORIGIN = 0x08004000, LENGTH = 16K
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FLASH1 (rx) : ORIGIN = 0x08008000, LENGTH = 480K
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SYSTEM_MEMORY (rx): ORIGIN = 0x1FFF0000, LENGTH = 29K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
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}
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@ -27,6 +27,8 @@ MEMORY
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FLASH_CONFIG (r) : ORIGIN = 0x08008000, LENGTH = 16K
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FLASH1 (rx) : ORIGIN = 0x0800C000, LENGTH = 464K
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SYSTEM_MEMORY (rx): ORIGIN = 0x1FFF0000, LENGTH = 29K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
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}
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@ -26,6 +26,8 @@ MEMORY
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FLASH_CONFIG (r) : ORIGIN = 0x08004000, LENGTH = 16K
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FLASH1 (rx) : ORIGIN = 0x08008000, LENGTH = 480K
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SYSTEM_MEMORY (rx): ORIGIN = 0x1FFF0000, LENGTH = 29K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
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}
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@ -35,6 +35,15 @@ SECTIONS
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. = ALIGN(4);
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} >FLASH
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/* System memory (read-only bootloader) interrupt vector */
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.system_isr_vector (NOLOAD) :
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{
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. = ALIGN(4);
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PROVIDE (system_isr_vector_table_base = .);
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KEEP(*(.system_isr_vector)) /* Bootloader code */
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. = ALIGN(4);
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} >SYSTEM_MEMORY
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/* The program code and other data goes into FLASH */
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.text :
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{
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@ -113,7 +122,7 @@ SECTIONS
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/* Uninitialized data section */
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. = ALIGN(4);
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.bss :
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.bss (NOLOAD) :
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{
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/* This is used by the startup in order to initialize the .bss secion */
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_sbss = .; /* define a global symbol at bss start */
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@ -136,6 +145,14 @@ SECTIONS
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__fastram_bss_end__ = .;
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} >FASTRAM
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.persistent_data (NOLOAD) :
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{
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__persistent_data_start__ = .;
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*(.persistent_data)
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. = ALIGN(4);
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__persistent_data_end__ = .;
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} >RAM
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/* User_heap_stack section, used to check that there is enough RAM left */
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_heap_stack_end = ORIGIN(STACKRAM) + LENGTH(STACKRAM) - _Hot_Reboot_Flags_Size;
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_heap_stack_begin = _heap_stack_end - _Min_Stack_Size - _Min_Heap_Size;
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@ -458,8 +458,64 @@ static void SystemInit_ExtMemCtl(void);
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uint32_t SystemCoreClock;
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uint32_t pll_p = PLL_P, pll_n = PLL_N, pll_q = PLL_Q;
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typedef struct pllConfig_s {
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uint16_t n;
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uint16_t p;
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uint16_t q;
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} pllConfig_t;
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static const pllConfig_t overclockLevels[] = {
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{ PLL_N, PLL_P, PLL_Q }, // default
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#if defined(STM32F40_41xxx)
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{ 384, 2, 8 }, // 192 MHz
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{ 432, 2, 9 }, // 216 MHz
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{ 480, 2, 10 } // 240 MHz
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#elif defined(STM32F411xE)
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{ 432, 4, 9 }, // 108 MHz
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{ 480, 4, 10 }, // 120 MHz
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#endif
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// XXX Doesn't work for F446 with this configuration.
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// XXX Need to use smaller M to reduce N?
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};
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static PERSISTENT uint32_t currentOverclockLevel = 0;
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void SystemInitOC(void)
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{
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/* PLL setting for overclocking */
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if (currentOverclockLevel >= ARRAYLEN(overclockLevels)) {
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return;
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}
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const pllConfig_t * const pll = overclockLevels + currentOverclockLevel;
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pll_n = pll->n;
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pll_p = pll->p;
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pll_q = pll->q;
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}
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void OverclockRebootIfNecessary(uint32_t overclockLevel)
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{
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if (overclockLevel >= ARRAYLEN(overclockLevels)) {
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return;
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}
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const pllConfig_t * const pll = overclockLevels + overclockLevel;
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// Reboot to adjust overclock frequency
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if (SystemCoreClock != (pll->n / pll->p) * 1000000) {
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currentOverclockLevel = overclockLevel;
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__disable_irq();
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NVIC_SystemReset();
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}
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}
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void SystemInit(void)
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{
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SystemInitOC();
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/* core clock is simply a mhz of PLL_N / PLL_P */
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SystemCoreClock = (pll_n / pll_p) * 1000000;
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@ -502,74 +558,6 @@ void SystemInit(void)
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#endif
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}
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typedef struct pllConfig_s {
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uint16_t n;
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uint16_t p;
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uint16_t q;
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} pllConfig_t;
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static const pllConfig_t overclockLevels[] = {
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{ PLL_N, PLL_P, PLL_Q }, // default
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#if defined(STM32F40_41xxx)
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{ 384, 2, 8 }, // 192 MHz
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{ 432, 2, 9 }, // 216 MHz
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{ 480, 2, 10 } // 240 MHz
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#elif defined(STM32F411xE)
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{ 432, 4, 9 }, // 108 MHz
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{ 480, 4, 10 }, // 120 MHz
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#endif
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// XXX Doesn't work for F446 with this configuration.
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// XXX Need to use smaller M to reduce N?
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};
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// 8 bytes of memory located at the very end of RAM, expected to be unoccupied
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#define REQUEST_OVERCLOCK (*(__IO uint32_t *) 0x2001FFF8)
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#define CURRENT_OVERCLOCK_LEVEL (*(__IO uint32_t *) 0x2001FFF4)
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#define REQUEST_OVERCLOCK_MAGIC_COOKIE 0xBABEFACE
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void SystemInitOC(void)
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{
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#ifdef STM32F411xE
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if (REQUEST_OVERCLOCK_MAGIC_COOKIE == REQUEST_OVERCLOCK) {
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#endif
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const uint32_t overclockLevel = CURRENT_OVERCLOCK_LEVEL;
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/* PLL setting for overclocking */
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if (overclockLevel < ARRAYLEN(overclockLevels)) {
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const pllConfig_t * const pll = overclockLevels + overclockLevel;
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pll_n = pll->n;
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pll_p = pll->p;
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pll_q = pll->q;
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}
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#ifdef STM32F411xE
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REQUEST_OVERCLOCK = 0;
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}
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#endif
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SystemInit();
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}
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void OverclockRebootIfNecessary(uint32_t overclockLevel)
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{
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if (overclockLevel >= ARRAYLEN(overclockLevels)) {
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return;
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}
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const pllConfig_t * const pll = overclockLevels + overclockLevel;
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// Reboot to adjust overclock frequency
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if (SystemCoreClock != (pll->n / pll->p) * 1000000) {
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REQUEST_OVERCLOCK = REQUEST_OVERCLOCK_MAGIC_COOKIE;
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CURRENT_OVERCLOCK_LEVEL = overclockLevel;
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__disable_irq();
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NVIC_SystemReset();
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}
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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@ -34,7 +34,6 @@
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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extern void SystemInit(void);
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extern void SystemInitOC(void);
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extern void SystemCoreClockUpdate(void);
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extern void OverclockRebootIfNecessary(uint32_t overclockLevel);
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