mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-24 00:35:39 +03:00
STM32F4: Library update
This commit is contained in:
blckmn
parent
5d385d0019
commit
bca73007d6
179 changed files with 5024 additions and 32738 deletions
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file misc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the miscellaneous
|
||||
* firmware library functions (add-on to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -325,9 +325,9 @@ typedef struct
|
|||
#define ADC_Channel_17 ((uint8_t)0x11)
|
||||
#define ADC_Channel_18 ((uint8_t)0x12)
|
||||
|
||||
#if defined (STM32F40_41xxx)
|
||||
#if defined (STM32F40_41xxx) || defined(STM32F412xG)
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||
#endif /* STM32F40_41xxx */
|
||||
#endif /* STM32F40_41xxx || STM32F412xG */
|
||||
|
||||
#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18)
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the CAN firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_cec.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the CEC firmware
|
||||
* library, applicable only for STM32F466xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the CRC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_cryp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the Cryptographic
|
||||
* processor(CRYP) firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_dbgmcu.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the DBGMCU firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_dcmi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the DCMI firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
764
lib/main/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dfsdm.h
Normal file
764
lib/main/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dfsdm.h
Normal file
|
|
@ -0,0 +1,764 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_dfsdm.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the DFSDM
|
||||
* firmware library
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4XX_DFSDM_H
|
||||
#define __STM32F4XX_DFSDM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DFSDM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DFSDM Transceiver init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DFSDM_Interface; /*!< Selects the serial interface type and input clock phase.
|
||||
This parameter can be a value of @ref DFSDM_Interface_Selection */
|
||||
|
||||
uint32_t DFSDM_Clock; /*!< Specifies the clock source for the serial interface transceiver.
|
||||
This parameter can be a value of @ref DFSDM_Clock_Selection */
|
||||
|
||||
uint32_t DFSDM_Input; /*!< Specifies the Input mode for the serial interface transceiver.
|
||||
This parameter can be a value of @ref DFSDM_Input_Selection */
|
||||
|
||||
uint32_t DFSDM_Redirection; /*!< Specifies if the channel input is redirected from channel channel (y+1).
|
||||
This parameter can be a value of @ref DFSDM_Redirection_Selection */
|
||||
|
||||
uint32_t DFSDM_PackingMode; /*!< Specifies the packing mode for the serial interface transceiver.
|
||||
This parameter can be a value of @ref DFSDM_Pack_Selection */
|
||||
|
||||
uint32_t DFSDM_DataRightShift; /*!< Defines the final data right bit shift.
|
||||
This parameter can be a value between 0 and 31 */
|
||||
|
||||
uint32_t DFSDM_Offset; /*!< Sets the calibration offset.
|
||||
This parameter can be a value between 0 and 0xFFFFFF */
|
||||
|
||||
uint32_t DFSDM_CLKAbsenceDetector; /*!< Enables or disables the Clock Absence Detector.
|
||||
This parameter can be a value of @ref DFSDM_Clock_Absence_Detector_state */
|
||||
|
||||
uint32_t DFSDM_ShortCircuitDetector; /*!< Enables or disables the Short Circuit Detector.
|
||||
This parameter can be a value of @ref DFSDM_Short_Circuit_Detector_state */
|
||||
}DFSDM_TransceiverInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM filter analog parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DFSDM_SincOrder; /*!< Sets the Sinc Filter Order .
|
||||
This parameter can be a value of @ref DFSDM_Sinc_Order */
|
||||
|
||||
uint32_t DFSDM_FilterOversamplingRatio; /*!< Sets the Sinc Filter Oversampling Ratio.
|
||||
This parameter can be a value between 1 and 1024 */
|
||||
|
||||
uint32_t DFSDM_IntegratorOversamplingRatio;/*!< Sets the Integrator Oversampling Ratio.
|
||||
This parameter can be a value between 1 and 256 */
|
||||
}DFSDM_FilterInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DFSDM_Interface_Selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_Interface_SPI_RisingEdge ((uint32_t)0x00000000) /*!< DFSDM SPI interface with rising edge to strobe data */
|
||||
#define DFSDM_Interface_SPI_FallingEdge ((uint32_t)0x00000001) /*!< DFSDM SPI interface with falling edge to strobe data */
|
||||
#define DFSDM_Interface_Manchester1 ((uint32_t)0x00000002) /*!< DFSDM Manchester coded input, rising edge = logic 0, falling edge = logic 1 */
|
||||
#define DFSDM_Interface_Manchester2 ((uint32_t)0x00000003) /*!< DFSDM Manchester coded input, rising edge = logic 1, falling edge = logic 0 */
|
||||
|
||||
#define IS_DFSDM_INTERFACE(INTERFACE) (((INTERFACE) == DFSDM_Interface_SPI_RisingEdge) || \
|
||||
((INTERFACE) == DFSDM_Interface_SPI_FallingEdge) || \
|
||||
((INTERFACE) == DFSDM_Interface_Manchester1) || \
|
||||
((INTERFACE) == DFSDM_Interface_Manchester2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Clock_Selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_Clock_External ((uint32_t)0x00000000) /*!< DFSDM clock coming from external DFSDM_CKINy input */
|
||||
#define DFSDM_Clock_Internal ((uint32_t)0x00000004) /*!< DFSDM clock coming from internal DFSDM_CKOUT output */
|
||||
#define DFSDM_Clock_InternalDiv2_Mode1 ((uint32_t)0x00000008) /*!< DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
|
||||
and clock change is on every rising edge of DFSDM_CKOUT output signal */
|
||||
#define DFSDM_Clock_InternalDiv2_Mode2 ((uint32_t)0x0000000C) /*!< DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
|
||||
and clock change is on every falling edge of DFSDM_CKOUT output signal */
|
||||
|
||||
#define IS_DFSDM_CLOCK(CLOCK) (((CLOCK) == DFSDM_Clock_External) || \
|
||||
((CLOCK) == DFSDM_Clock_Internal) || \
|
||||
((CLOCK) == DFSDM_Clock_InternalDiv2_Mode1) || \
|
||||
((CLOCK) == DFSDM_Clock_InternalDiv2_Mode2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Input_Selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_Input_External ((uint32_t)0x00000000) /*!< DFSDM clock coming from external DFSDM_CKINy input */
|
||||
#define DFSDM_Input_ADC ((uint32_t)0x00001000) /*!< DFSDM clock coming from internal DFSDM_CKOUT output */
|
||||
#define DFSDM_Input_Internal ((uint32_t)0x00002000) /*!< DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
|
||||
and clock change is on every rising edge of DFSDM_CKOUT output signal */
|
||||
|
||||
#define IS_DFSDM_Input_MODE(INPUT) (((INPUT) == DFSDM_Input_External) || \
|
||||
((INPUT) == DFSDM_Input_ADC) || \
|
||||
((INPUT) == DFSDM_Input_Internal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Redirection_Selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_Redirection_Disabled ((uint32_t)0x00000000) /*!< DFSDM Channel serial inputs are taken from pins of the same channel y */
|
||||
#define DFSDM_Redirection_Enabled DFSDM_CHCFGR1_CHINSEL /*!< DFSDM Channel serial inputs are taken from pins of the channel (y+1) modulo 8 */
|
||||
|
||||
#define IS_DFSDM_Redirection_STATE(STATE) (((STATE) == DFSDM_Redirection_Disabled) || \
|
||||
((STATE) == DFSDM_Redirection_Enabled))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Pack_Selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_PackingMode_Standard ((uint32_t)0x00000000) /*!< DFSDM Input data in DFSDM_CHDATINyR register are stored only in INDAT0[15:0] */
|
||||
#define DFSDM_PackingMode_Interleaved ((uint32_t)0x00004000) /*!< DFSDM Input data in DFSDM_CHDATINyR register are stored as two samples:
|
||||
- first sample in INDAT0[15:0] - assigned to channel y
|
||||
- second sample INDAT1[15:0] - assigned to channel y */
|
||||
#define DFSDM_PackingMode_Dual ((uint32_t)0x00008000) /*!< DFSDM Input data in DFSDM_CHDATINyR register are stored as two samples:
|
||||
- first sample INDAT0[15:0] - assigned to channel y
|
||||
- second sample INDAT1[15:0] - assigned to channel (y+1) */
|
||||
|
||||
#define IS_DFSDM_PACK_MODE(MODE) (((MODE) == DFSDM_PackingMode_Standard) || \
|
||||
((MODE) == DFSDM_PackingMode_Interleaved) || \
|
||||
((MODE) == DFSDM_PackingMode_Dual))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Clock_Absence_Detector_state
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CLKAbsenceDetector_Enable DFSDM_CHCFGR1_CKABEN /*!< DFSDM Clock Absence Detector is Enabled */
|
||||
#define DFSDM_CLKAbsenceDetector_Disable ((uint32_t)0x00000000) /*!< DFSDM Clock Absence Detector is Disabled */
|
||||
|
||||
#define IS_DFSDM_CLK_DETECTOR_STATE(STATE) (((STATE) == DFSDM_CLKAbsenceDetector_Enable) || \
|
||||
((STATE) == DFSDM_CLKAbsenceDetector_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Short_Circuit_Detector_state
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_ShortCircuitDetector_Enable DFSDM_CHCFGR1_SCDEN /*!< DFSDM Short Circuit Detector is Enabled */
|
||||
#define DFSDM_ShortCircuitDetector_Disable ((uint32_t)0x00000000) /*!< DFSDM Short Circuit Detector is Disabled */
|
||||
|
||||
#define IS_DFSDM_SC_DETECTOR_STATE(STATE) (((STATE) == DFSDM_ShortCircuitDetector_Enable) || \
|
||||
((STATE) == DFSDM_ShortCircuitDetector_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Sinc_Order
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_SincOrder_FastSinc ((uint32_t)0x00000000) /*!< DFSDM Sinc filter order = Fast sinc */
|
||||
#define DFSDM_SincOrder_Sinc1 ((uint32_t)0x20000000) /*!< DFSDM Sinc filter order = 1 */
|
||||
#define DFSDM_SincOrder_Sinc2 ((uint32_t)0x40000000) /*!< DFSDM Sinc filter order = 2 */
|
||||
#define DFSDM_SincOrder_Sinc3 ((uint32_t)0x60000000) /*!< DFSDM Sinc filter order = 3 */
|
||||
#define DFSDM_SincOrder_Sinc4 ((uint32_t)0x80000000) /*!< DFSDM Sinc filter order = 4 */
|
||||
#define DFSDM_SincOrder_Sinc5 ((uint32_t)0xA0000000) /*!< DFSDM Sinc filter order = 5 */
|
||||
|
||||
#define IS_DFSDM_SINC_ORDER(ORDER) (((ORDER) == DFSDM_SincOrder_FastSinc) || \
|
||||
((ORDER) == DFSDM_SincOrder_Sinc1) || \
|
||||
((ORDER) == DFSDM_SincOrder_Sinc2) || \
|
||||
((ORDER) == DFSDM_SincOrder_Sinc3) || \
|
||||
((ORDER) == DFSDM_SincOrder_Sinc4) || \
|
||||
((ORDER) == DFSDM_SincOrder_Sinc5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Break_Signal_Assignment
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_SCDBreak_0 ((uint32_t)0x00001000) /*!< DFSDM Break 0 signal assigned to short circuit detector */
|
||||
#define DFSDM_SCDBreak_1 ((uint32_t)0x00002000) /*!< DFSDM Break 1 signal assigned to short circuit detector */
|
||||
#define DFSDM_SCDBreak_2 ((uint32_t)0x00004000) /*!< DFSDM Break 2 signal assigned to short circuit detector */
|
||||
#define DFSDM_SCDBreak_3 ((uint32_t)0x00008000) /*!< DFSDM Break 3 signal assigned to short circuit detector */
|
||||
|
||||
#define IS_DFSDM_SCD_BREAK_SIGNAL(RANK) (((RANK) == DFSDM_SCDBreak_0) || \
|
||||
((RANK) == DFSDM_SCDBreak_1) || \
|
||||
((RANK) == DFSDM_SCDBreak_2) || \
|
||||
((RANK) == DFSDM_SCDBreak_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_AWD_Sinc_Order
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_AWDSincOrder_Fast ((uint32_t)0x00000000) /*!< DFSDM Fast sinc filter */
|
||||
#define DFSDM_AWDSincOrder_Sinc1 ((uint32_t)0x00400000) /*!< DFSDM sinc1 filter */
|
||||
#define DFSDM_AWDSincOrder_Sinc2 ((uint32_t)0x00800000) /*!< DFSDM sinc2 filter */
|
||||
#define DFSDM_AWDSincOrder_Sinc3 ((uint32_t)0x00C00000) /*!< DFSDM sinc3 filter */
|
||||
|
||||
#define IS_DFSDM_AWD_SINC_ORDER(ORDER) (((ORDER) == DFSDM_AWDSincOrder_Fast) || \
|
||||
((ORDER) == DFSDM_AWDSincOrder_Sinc1) || \
|
||||
((ORDER) == DFSDM_AWDSincOrder_Sinc2) || \
|
||||
((ORDER) == DFSDM_AWDSincOrder_Sinc3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_AWD_CHANNEL
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_AWDChannel0 ((uint32_t)0x00010000) /*!< DFSDM AWDx guard channel 0 */
|
||||
#define DFSDM_AWDChannel1 ((uint32_t)0x00020000) /*!< DFSDM AWDx guard channel 1 */
|
||||
#define DFSDM_AWDChannel2 ((uint32_t)0x00040000) /*!< DFSDM AWDx guard channel 2 */
|
||||
#define DFSDM_AWDChannel3 ((uint32_t)0x00080000) /*!< DFSDM AWDx guard channel 3 */
|
||||
#define DFSDM_AWDChannel4 ((uint32_t)0x00100000) /*!< DFSDM AWDx guard channel 4 */
|
||||
#define DFSDM_AWDChannel5 ((uint32_t)0x00200000) /*!< DFSDM AWDx guard channel 5 */
|
||||
#define DFSDM_AWDChannel6 ((uint32_t)0x00400000) /*!< DFSDM AWDx guard channel 6 */
|
||||
#define DFSDM_AWDChannel7 ((uint32_t)0x00800000) /*!< DFSDM AWDx guard channel 7 */
|
||||
|
||||
#define IS_DFSDM_AWD_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_AWDChannel0) || \
|
||||
((CHANNEL) == DFSDM_AWDChannel1) || \
|
||||
((CHANNEL) == DFSDM_AWDChannel2) || \
|
||||
((CHANNEL) == DFSDM_AWDChannel3) || \
|
||||
((CHANNEL) == DFSDM_AWDChannel4) || \
|
||||
((CHANNEL) == DFSDM_AWDChannel5) || \
|
||||
((CHANNEL) == DFSDM_AWDChannel6) || \
|
||||
((CHANNEL) == DFSDM_AWDChannel7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Threshold_Selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_Threshold_Low ((uint8_t)0x00) /*!< DFSDM Low threshold */
|
||||
#define DFSDM_Threshold_High ((uint8_t)0x08) /*!< DFSDM High threshold */
|
||||
|
||||
#define IS_DFSDM_Threshold(THR) (((THR) == DFSDM_Threshold_Low) || \
|
||||
((THR) == DFSDM_Threshold_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_AWD_Fast_Mode_Selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_AWDFastMode_Disable ((uint32_t)0x00000000) /*!< DFSDM Fast mode for AWD is disabled */
|
||||
#define DFSDM_AWDFastMode_Enable ((uint32_t)0x40000000) /*!< DFSDM Fast mode for AWD is enabled */
|
||||
|
||||
#define IS_DFSDM_AWD_MODE(MODE) (((MODE) == DFSDM_AWDFastMode_Disable) || \
|
||||
((MODE) == DFSDM_AWDFastMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Clock_Output_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_ClkOutSource_SysClock ((uint32_t)0x00000000) /*!< DFSDM Source for output clock is comming from system clock */
|
||||
#define DFSDM_ClkOutSource_AudioClock DFSDM_CHCFGR1_CKOUTSRC /*!< DFSDM Source for output clock is comming from audio clock */
|
||||
|
||||
#define IS_DFSDM_CLOCK_OUT_SOURCE(SRC) (((SRC) == DFSDM_ClkOutSource_SysClock) || \
|
||||
((SRC) == DFSDM_ClkOutSource_AudioClock))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Conversion_Mode
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_DMAConversionMode_Regular ((uint32_t)0x00000010) /*!< DFSDM Regular mode */
|
||||
#define DFSDM_DMAConversionMode_Injected ((uint32_t)0x00000000) /*!< DFSDM Injected mode */
|
||||
|
||||
#define IS_DFSDM_CONVERSION_MODE(MODE) ((MODE) == DFSDM_DMAConversionMode_Regular || \
|
||||
((MODE) == DFSDM_DMAConversionMode_Injected))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Extremes_Channel_Selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_ExtremChannel0 ((uint32_t)0x00000100) /*!< DFSDM Extreme detector guard channel 0 */
|
||||
#define DFSDM_ExtremChannel1 ((uint32_t)0x00000200) /*!< DFSDM Extreme detector guard channel 1 */
|
||||
#define DFSDM_ExtremChannel2 ((uint32_t)0x00000400) /*!< DFSDM Extreme detector guard channel 2 */
|
||||
#define DFSDM_ExtremChannel3 ((uint32_t)0x00000800) /*!< DFSDM Extreme detector guard channel 3 */
|
||||
#define DFSDM_ExtremChannel4 ((uint32_t)0x00001000) /*!< DFSDM Extreme detector guard channel 4 */
|
||||
#define DFSDM_ExtremChannel5 ((uint32_t)0x00002000) /*!< DFSDM Extreme detector guard channel 5 */
|
||||
#define DFSDM_ExtremChannel6 ((uint32_t)0x00004000) /*!< DFSDM Extreme detector guard channel 6 */
|
||||
#define DFSDM_ExtremChannel7 ((uint32_t)0x00008000) /*!< DFSDM Extreme detector guard channel 7 */
|
||||
|
||||
#define IS_DFSDM_EXTREM_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_ExtremChannel0) || \
|
||||
((CHANNEL) == DFSDM_ExtremChannel1) || \
|
||||
((CHANNEL) == DFSDM_ExtremChannel2) || \
|
||||
((CHANNEL) == DFSDM_ExtremChannel3) || \
|
||||
((CHANNEL) == DFSDM_ExtremChannel4) || \
|
||||
((CHANNEL) == DFSDM_ExtremChannel5) || \
|
||||
((CHANNEL) == DFSDM_ExtremChannel6) || \
|
||||
((CHANNEL) == DFSDM_ExtremChannel7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Injected_Channel_Selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_InjectedChannel0 ((uint32_t)0x00000001) /*!< DFSDM channel 0 is selected as injected channel */
|
||||
#define DFSDM_InjectedChannel1 ((uint32_t)0x00000002) /*!< DFSDM channel 1 is selected as injected channel */
|
||||
#define DFSDM_InjectedChannel2 ((uint32_t)0x00000004) /*!< DFSDM channel 2 is selected as injected channel */
|
||||
#define DFSDM_InjectedChannel3 ((uint32_t)0x00000008) /*!< DFSDM channel 3 is selected as injected channel */
|
||||
#define DFSDM_InjectedChannel4 ((uint32_t)0x00000010) /*!< DFSDM channel 4 is selected as injected channel */
|
||||
#define DFSDM_InjectedChannel5 ((uint32_t)0x00000020) /*!< DFSDM channel 5 is selected as injected channel */
|
||||
#define DFSDM_InjectedChannel6 ((uint32_t)0x00000040) /*!< DFSDM channel 6 is selected as injected channel */
|
||||
#define DFSDM_InjectedChannel7 ((uint32_t)0x00000080) /*!< DFSDM channel 7 is selected as injected channel */
|
||||
|
||||
#define IS_DFSDM_INJECT_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_InjectedChannel0) || \
|
||||
((CHANNEL) == DFSDM_InjectedChannel1) || \
|
||||
((CHANNEL) == DFSDM_InjectedChannel2) || \
|
||||
((CHANNEL) == DFSDM_InjectedChannel3) || \
|
||||
((CHANNEL) == DFSDM_InjectedChannel4) || \
|
||||
((CHANNEL) == DFSDM_InjectedChannel5) || \
|
||||
((CHANNEL) == DFSDM_InjectedChannel6) || \
|
||||
((CHANNEL) == DFSDM_InjectedChannel7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Regular_Channel_Selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_RegularChannel0 ((uint32_t)0x00000000) /*!< DFSDM channel 0 is selected as regular channel */
|
||||
#define DFSDM_RegularChannel1 ((uint32_t)0x01000000) /*!< DFSDM channel 1 is selected as regular channel */
|
||||
#define DFSDM_RegularChannel2 ((uint32_t)0x02000000) /*!< DFSDM channel 2 is selected as regular channel */
|
||||
#define DFSDM_RegularChannel3 ((uint32_t)0x03000000) /*!< DFSDM channel 3 is selected as regular channel */
|
||||
#define DFSDM_RegularChannel4 ((uint32_t)0x04000000) /*!< DFSDM channel 4 is selected as regular channel */
|
||||
#define DFSDM_RegularChannel5 ((uint32_t)0x05000000) /*!< DFSDM channel 5 is selected as regular channel */
|
||||
#define DFSDM_RegularChannel6 ((uint32_t)0x06000000) /*!< DFSDM channel 6 is selected as regular channel */
|
||||
#define DFSDM_RegularChannel7 ((uint32_t)0x07000000) /*!< DFSDM channel 7 is selected as regular channel */
|
||||
|
||||
#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_RegularChannel0) || \
|
||||
((CHANNEL) == DFSDM_RegularChannel1) || \
|
||||
((CHANNEL) == DFSDM_RegularChannel2) || \
|
||||
((CHANNEL) == DFSDM_RegularChannel3) || \
|
||||
((CHANNEL) == DFSDM_RegularChannel4) || \
|
||||
((CHANNEL) == DFSDM_RegularChannel5) || \
|
||||
((CHANNEL) == DFSDM_RegularChannel6) || \
|
||||
((CHANNEL) == DFSDM_RegularChannel7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Injected_Trigger_signal
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_Trigger_TIM1_TRGO ((uint32_t)0x00000000) /*!< DFSDM Internal trigger 0 */
|
||||
#define DFSDM_Trigger_TIM1_TRGO2 ((uint32_t)0x00000100) /*!< DFSDM Internal trigger 1 */
|
||||
#define DFSDM_Trigger_TIM8_TRGO ((uint32_t)0x00000200) /*!< DFSDM Internal trigger 2 */
|
||||
#define DFSDM_Trigger_TIM8_TRGO2 ((uint32_t)0x00000300) /*!< DFSDM Internal trigger 3 */
|
||||
#define DFSDM_Trigger_TIM3_TRGO ((uint32_t)0x00000300) /*!< DFSDM Internal trigger 4 */
|
||||
#define DFSDM_Trigger_TIM4_TRGO ((uint32_t)0x00000400) /*!< DFSDM Internal trigger 5 */
|
||||
#define DFSDM_Trigger_TIM16_OC1 ((uint32_t)0x00000400) /*!< DFSDM Internal trigger 6 */
|
||||
#define DFSDM_Trigger_TIM6_TRGO ((uint32_t)0x00000500) /*!< DFSDM Internal trigger 7 */
|
||||
#define DFSDM_Trigger_TIM7_TRGO ((uint32_t)0x00000500) /*!< DFSDM Internal trigger 8 */
|
||||
#define DFSDM_Trigger_EXTI11 ((uint32_t)0x00000600) /*!< DFSDM External trigger 0 */
|
||||
#define DFSDM_Trigger_EXTI15 ((uint32_t)0x00000700) /*!< DFSDM External trigger 1 */
|
||||
|
||||
#define IS_DFSDM0_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_Trigger_TIM1_TRGO) || \
|
||||
((TRIG) == DFSDM_Trigger_TIM1_TRGO2) || \
|
||||
((TRIG) == DFSDM_Trigger_TIM8_TRGO) || \
|
||||
((TRIG) == DFSDM_Trigger_TIM8_TRGO2) || \
|
||||
((TRIG) == DFSDM_Trigger_TIM4_TRGO) || \
|
||||
((TRIG) == DFSDM_Trigger_TIM6_TRGO) || \
|
||||
((TRIG) == DFSDM_Trigger_TIM1_TRGO) || \
|
||||
((TRIG) == DFSDM_Trigger_EXTI15))
|
||||
|
||||
#define IS_DFSDM1_INJ_TRIGGER(TRIG) IS_DFSDM0_INJ_TRIGGER(TRIG)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Trigger_Edge_selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_TriggerEdge_Disabled ((uint32_t)0x00000000) /*!< DFSDM Trigger detection disabled */
|
||||
#define DFSDM_TriggerEdge_Rising ((uint32_t)0x00002000) /*!< DFSDM Each rising edge makes a request to launch an injected conversion */
|
||||
#define DFSDM_TriggerEdge_Falling ((uint32_t)0x00004000) /*!< DFSDM Each falling edge makes a request to launch an injected conversion */
|
||||
#define DFSDM_TriggerEdge_BothEdges ((uint32_t)0x00006000) /*!< DFSDM Both edges make a request to launch an injected conversion */
|
||||
|
||||
#define IS_DFSDM_TRIGGER_EDGE(EDGE) (((EDGE) == DFSDM_TriggerEdge_Disabled) || \
|
||||
((EDGE) == DFSDM_TriggerEdge_Rising) || \
|
||||
((EDGE) == DFSDM_TriggerEdge_Falling) || \
|
||||
((EDGE) == DFSDM_TriggerEdge_BothEdges))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Injected_Conversion_Mode_Selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_InjectConvMode_Single ((uint32_t)0x00000000) /*!< DFSDM Trigger detection disabled */
|
||||
#define DFSDM_InjectConvMode_Scan ((uint32_t)0x00000010) /*!< DFSDM Each rising edge makes a request to launch an injected conversion */
|
||||
|
||||
#define IS_DFSDM_INJ_CONV_MODE(MODE) (((MODE) == DFSDM_InjectConvMode_Single) || \
|
||||
((MODE) == DFSDM_InjectConvMode_Scan))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Interrupts_Definition
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_IT_JEOC DFSDM_FLTCR2_JEOCIE
|
||||
#define DFSDM_IT_REOC DFSDM_FLTCR2_REOCIE
|
||||
#define DFSDM_IT_JOVR DFSDM_FLTCR2_JOVRIE
|
||||
#define DFSDM_IT_ROVR DFSDM_FLTCR2_ROVRIE
|
||||
#define DFSDM_IT_AWD DFSDM_FLTCR2_AWDIE
|
||||
#define DFSDM_IT_SCD DFSDM_FLTCR2_SCDIE
|
||||
#define DFSDM_IT_CKAB DFSDM_FLTCR2_CKABIE
|
||||
|
||||
#define IS_DFSDM_IT(IT) (((IT) == DFSDM_IT_JEOC) || \
|
||||
((IT) == DFSDM_IT_REOC) || \
|
||||
((IT) == DFSDM_IT_JOVR) || \
|
||||
((IT) == DFSDM_IT_ROVR) || \
|
||||
((IT) == DFSDM_IT_AWD) || \
|
||||
((IT) == DFSDM_IT_SCD) || \
|
||||
((IT) == DFSDM_IT_CKAB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Flag_Definition
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_FLAG_JEOC DFSDM_FLTISR_JEOCF
|
||||
#define DFSDM_FLAG_REOC DFSDM_FLTISR_REOCF
|
||||
#define DFSDM_FLAG_JOVR DFSDM_FLTISR_JOVRF
|
||||
#define DFSDM_FLAG_ROVR DFSDM_FLTISR_ROVRF
|
||||
#define DFSDM_FLAG_AWD DFSDM_FLTISR_AWDF
|
||||
#define DFSDM_FLAG_JCIP DFSDM_FLTISR_JCIP
|
||||
#define DFSDM_FLAG_RCIP DFSDM_FLTISR_RCIP
|
||||
|
||||
#define IS_DFSDM_FLAG(FLAG) (((FLAG) == DFSDM_FLAG_JEOC) || \
|
||||
((FLAG) == DFSDM_FLAG_REOC) || \
|
||||
((FLAG) == DFSDM_FLAG_JOVR) || \
|
||||
((FLAG) == DFSDM_FLAG_ROVR) || \
|
||||
((FLAG) == DFSDM_FLAG_AWD) || \
|
||||
((FLAG) == DFSDM_FLAG_JCIP) || \
|
||||
((FLAG) == DFSDM_FLAG_RCIP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Clock_Absence_Flag_Definition
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_FLAG_CLKAbsence_Channel0 ((uint32_t)0x00010000)
|
||||
#define DFSDM_FLAG_CLKAbsence_Channel1 ((uint32_t)0x00020000)
|
||||
#define DFSDM_FLAG_CLKAbsence_Channel2 ((uint32_t)0x00040000)
|
||||
#define DFSDM_FLAG_CLKAbsence_Channel3 ((uint32_t)0x00080000)
|
||||
#define DFSDM_FLAG_CLKAbsence_Channel4 ((uint32_t)0x00100000)
|
||||
#define DFSDM_FLAG_CLKAbsence_Channel5 ((uint32_t)0x00200000)
|
||||
#define DFSDM_FLAG_CLKAbsence_Channel6 ((uint32_t)0x00400000)
|
||||
#define DFSDM_FLAG_CLKAbsence_Channel7 ((uint32_t)0x00800000)
|
||||
|
||||
#define IS_DFSDM_CLK_ABS_FLAG(FLAG) (((FLAG) == DFSDM_FLAG_CLKAbsence_Channel0) || \
|
||||
((FLAG) == DFSDM_FLAG_CLKAbsence_Channel1) || \
|
||||
((FLAG) == DFSDM_FLAG_CLKAbsence_Channel2) || \
|
||||
((FLAG) == DFSDM_FLAG_CLKAbsence_Channel3) || \
|
||||
((FLAG) == DFSDM_FLAG_CLKAbsence_Channel4) || \
|
||||
((FLAG) == DFSDM_FLAG_CLKAbsence_Channel5) || \
|
||||
((FLAG) == DFSDM_FLAG_CLKAbsence_Channel6) || \
|
||||
((FLAG) == DFSDM_FLAG_CLKAbsence_Channel7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_SCD_Flag_Definition
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_FLAG_SCD_Channel0 ((uint32_t)0x01000000)
|
||||
#define DFSDM_FLAG_SCD_Channel1 ((uint32_t)0x02000000)
|
||||
#define DFSDM_FLAG_SCD_Channel2 ((uint32_t)0x04000000)
|
||||
#define DFSDM_FLAG_SCD_Channel3 ((uint32_t)0x08000000)
|
||||
#define DFSDM_FLAG_SCD_Channel4 ((uint32_t)0x10000000)
|
||||
#define DFSDM_FLAG_SCD_Channel5 ((uint32_t)0x20000000)
|
||||
#define DFSDM_FLAG_SCD_Channel6 ((uint32_t)0x40000000)
|
||||
#define DFSDM_FLAG_SCD_Channel7 ((uint32_t)0x80000000)
|
||||
|
||||
#define IS_DFSDM_SCD_FLAG(FLAG) (((FLAG) == DFSDM_FLAG_SCD_Channel0) || \
|
||||
((FLAG) == DFSDM_FLAG_SCD_Channel1) || \
|
||||
((FLAG) == DFSDM_FLAG_SCD_Channel2) || \
|
||||
((FLAG) == DFSDM_FLAG_SCD_Channel3) || \
|
||||
((FLAG) == DFSDM_FLAG_SCD_Channel4) || \
|
||||
((FLAG) == DFSDM_FLAG_SCD_Channel5) || \
|
||||
((FLAG) == DFSDM_FLAG_SCD_Channel6) || \
|
||||
((FLAG) == DFSDM_FLAG_SCD_Channel7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Clear_Flag_Definition
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CLEARF_JOVR DFSDM_FLTICR_CLRJOVRF
|
||||
#define DFSDM_CLEARF_ROVR DFSDM_FLTICR_CLRROVRF
|
||||
|
||||
#define IS_DFSDM_CLEAR_FLAG(FLAG) (((FLAG) == DFSDM_CLEARF_JOVR) || \
|
||||
((FLAG) == DFSDM_CLEARF_ROVR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Clear_ClockAbs_Flag_Definition
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CLEARF_CLKAbsence_Channel0 ((uint32_t)0x00010000)
|
||||
#define DFSDM_CLEARF_CLKAbsence_Channel1 ((uint32_t)0x00020000)
|
||||
#define DFSDM_CLEARF_CLKAbsence_Channel2 ((uint32_t)0x00040000)
|
||||
#define DFSDM_CLEARF_CLKAbsence_Channel3 ((uint32_t)0x00080000)
|
||||
#define DFSDM_CLEARF_CLKAbsence_Channel4 ((uint32_t)0x00100000)
|
||||
#define DFSDM_CLEARF_CLKAbsence_Channel5 ((uint32_t)0x00200000)
|
||||
#define DFSDM_CLEARF_CLKAbsence_Channel6 ((uint32_t)0x00400000)
|
||||
#define DFSDM_CLEARF_CLKAbsence_Channel7 ((uint32_t)0x00800000)
|
||||
|
||||
#define IS_DFSDM_CLK_ABS_CLEARF(FLAG) (((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel0) || \
|
||||
((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel1) || \
|
||||
((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel2) || \
|
||||
((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel3) || \
|
||||
((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel4) || \
|
||||
((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel5) || \
|
||||
((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel6) || \
|
||||
((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Clear_Short_Circuit_Flag_Definition
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CLEARF_SCD_Channel0 ((uint32_t)0x01000000)
|
||||
#define DFSDM_CLEARF_SCD_Channel1 ((uint32_t)0x02000000)
|
||||
#define DFSDM_CLEARF_SCD_Channel2 ((uint32_t)0x04000000)
|
||||
#define DFSDM_CLEARF_SCD_Channel3 ((uint32_t)0x08000000)
|
||||
#define DFSDM_CLEARF_SCD_Channel4 ((uint32_t)0x10000000)
|
||||
#define DFSDM_CLEARF_SCD_Channel5 ((uint32_t)0x20000000)
|
||||
#define DFSDM_CLEARF_SCD_Channel6 ((uint32_t)0x40000000)
|
||||
#define DFSDM_CLEARF_SCD_Channel7 ((uint32_t)0x80000000)
|
||||
|
||||
#define IS_DFSDM_SCD_CHANNEL_FLAG(FLAG) (((FLAG) == DFSDM_CLEARF_SCD_Channel0) || \
|
||||
((FLAG) == DFSDM_CLEARF_SCD_Channel1) || \
|
||||
((FLAG) == DFSDM_CLEARF_SCD_Channel2) || \
|
||||
((FLAG) == DFSDM_CLEARF_SCD_Channel3) || \
|
||||
((FLAG) == DFSDM_CLEARF_SCD_Channel4) || \
|
||||
((FLAG) == DFSDM_CLEARF_SCD_Channel5) || \
|
||||
((FLAG) == DFSDM_CLEARF_SCD_Channel6) || \
|
||||
((FLAG) == DFSDM_CLEARF_SCD_Channel7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Clock_Absence_Interrupt_Definition
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_IT_CLKAbsence_Channel0 ((uint32_t)0x00010000)
|
||||
#define DFSDM_IT_CLKAbsence_Channel1 ((uint32_t)0x00020000)
|
||||
#define DFSDM_IT_CLKAbsence_Channel2 ((uint32_t)0x00040000)
|
||||
#define DFSDM_IT_CLKAbsence_Channel3 ((uint32_t)0x00080000)
|
||||
#define DFSDM_IT_CLKAbsence_Channel4 ((uint32_t)0x00100000)
|
||||
#define DFSDM_IT_CLKAbsence_Channel5 ((uint32_t)0x00200000)
|
||||
#define DFSDM_IT_CLKAbsence_Channel6 ((uint32_t)0x00400000)
|
||||
#define DFSDM_IT_CLKAbsence_Channel7 ((uint32_t)0x00800000)
|
||||
|
||||
#define IS_DFSDM_CLK_ABS_IT(IT) (((IT) == DFSDM_IT_CLKAbsence_Channel0) || \
|
||||
((IT) == DFSDM_IT_CLKAbsence_Channel1) || \
|
||||
((IT) == DFSDM_IT_CLKAbsence_Channel2) || \
|
||||
((IT) == DFSDM_IT_CLKAbsence_Channel3) || \
|
||||
((IT) == DFSDM_IT_CLKAbsence_Channel4) || \
|
||||
((IT) == DFSDM_IT_CLKAbsence_Channel5) || \
|
||||
((IT) == DFSDM_IT_CLKAbsence_Channel6) || \
|
||||
((IT) == DFSDM_IT_CLKAbsence_Channel7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_SCD_Interrupt_Definition
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_IT_SCD_Channel0 ((uint32_t)0x01000000)
|
||||
#define DFSDM_IT_SCD_Channel1 ((uint32_t)0x02000000)
|
||||
#define DFSDM_IT_SCD_Channel2 ((uint32_t)0x04000000)
|
||||
#define DFSDM_IT_SCD_Channel3 ((uint32_t)0x08000000)
|
||||
#define DFSDM_IT_SCD_Channel4 ((uint32_t)0x10000000)
|
||||
#define DFSDM_IT_SCD_Channel5 ((uint32_t)0x20000000)
|
||||
#define DFSDM_IT_SCD_Channel6 ((uint32_t)0x40000000)
|
||||
#define DFSDM_IT_SCD_Channel7 ((uint32_t)0x80000000)
|
||||
|
||||
#define IS_DFSDM_SCD_IT(IT) (((IT) == DFSDM_IT_SCD_Channel0) || \
|
||||
((IT) == DFSDM_IT_SCD_Channel1) || \
|
||||
((IT) == DFSDM_IT_SCD_Channel2) || \
|
||||
((IT) == DFSDM_IT_SCD_Channel3) || \
|
||||
((IT) == DFSDM_IT_SCD_Channel4) || \
|
||||
((IT) == DFSDM_IT_SCD_Channel5) || \
|
||||
((IT) == DFSDM_IT_SCD_Channel6) || \
|
||||
((IT) == DFSDM_IT_SCD_Channel7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_DFSDM_DATA_RIGHT_BIT_SHIFT(SHIFT) (SHIFT < 0x20 )
|
||||
|
||||
#define IS_DFSDM_OFFSET(OFFSET) (OFFSET < 0x01000000 )
|
||||
|
||||
#define IS_DFSDM_ALL_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM1_Channel0) || \
|
||||
((CHANNEL) == DFSDM1_Channel1) || \
|
||||
((CHANNEL) == DFSDM1_Channel2) || \
|
||||
((CHANNEL) == DFSDM1_Channel3))
|
||||
|
||||
#define IS_DFSDM_ALL_FILTER(FILTER) (((FILTER) == DFSDM0) || \
|
||||
((FILTER) == DFSDM1))
|
||||
|
||||
#define IS_DFSDM_SYNC_FILTER(FILTER) (((FILTER) == DFSDM1))
|
||||
|
||||
#define IS_DFSDM_SINC_OVRSMPL_RATIO(RATIO) ( RATIO < 0x401 ) & ( RATIO >= 0x001 )
|
||||
|
||||
#define IS_DFSDM_INTG_OVRSMPL_RATIO(RATIO) ( RATIO < 0x101 ) & ( RATIO >= 0x001 )
|
||||
|
||||
#define IS_DFSDM_CLOCK_OUT_DIVIDER(DIVIDER) ( DIVIDER < 0x101 )
|
||||
|
||||
#define IS_DFSDM_CSD_THRESHOLD_VALUE(VALUE) ( VALUE < 256 )
|
||||
|
||||
#define IS_DFSDM_AWD_OVRSMPL_RATIO(RATIO) ( RATIO < 33 ) & ( RATIO >= 0x001 )
|
||||
|
||||
#define IS_DFSDM_HIGH_THRESHOLD(VALUE) (VALUE < 0x1000000 )
|
||||
#define IS_DFSDM_LOW_THRESHOLD(VALUE) (VALUE < 0x1000000 )
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Initialization functions ***************************************************/
|
||||
void DFSDM_DeInit(void);
|
||||
void DFSDM_TransceiverInit(DFSDM_Channel_TypeDef* DFSDM_Channelx, DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct);
|
||||
void DFSDM_TransceiverStructInit(DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct);
|
||||
void DFSDM_FilterInit(DFSDM_TypeDef* DFSDMx, DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct);
|
||||
void DFSDM_FilterStructInit(DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct);
|
||||
|
||||
/* Configuration functions ****************************************************/
|
||||
void DFSDM_Cmd(FunctionalState NewState);
|
||||
void DFSDM_ChannelCmd(DFSDM_Channel_TypeDef* DFSDM_Channelx, FunctionalState NewState);
|
||||
void DFSDM_FilterCmd(DFSDM_TypeDef* DFSDMx, FunctionalState NewState);
|
||||
void DFSDM_ConfigClkOutputDivider(uint32_t DFSDM_ClkOutDivision);
|
||||
void DFSDM_ConfigClkOutputSource(uint32_t DFSDM_ClkOutSource);
|
||||
void DFSDM_SelectInjectedConversionMode(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_InjectConvMode);
|
||||
void DFSDM_SelectInjectedChannel(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_InjectedChannelx);
|
||||
void DFSDM_SelectRegularChannel(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_RegularChannelx);
|
||||
void DFSDM_StartSoftwareInjectedConversion(DFSDM_TypeDef* DFSDMx);
|
||||
void DFSDM_StartSoftwareRegularConversion(DFSDM_TypeDef* DFSDMx);
|
||||
void DFSDM_SynchronousFilter0InjectedStart(DFSDM_TypeDef* DFSDMx);
|
||||
void DFSDM_SynchronousFilter0RegularStart(DFSDM_TypeDef* DFSDMx);
|
||||
void DFSDM_RegularContinuousModeCmd(DFSDM_TypeDef* DFSDMx, FunctionalState NewState);
|
||||
void DFSDM_InjectedContinuousModeCmd(DFSDM_TypeDef* DFSDMx, FunctionalState NewState);
|
||||
void DFSDM_FastModeCmd(DFSDM_TypeDef* DFSDMx, FunctionalState NewState);
|
||||
void DFSDM_ConfigInjectedTrigger(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_Trigger, uint32_t DFSDM_TriggerEdge);
|
||||
void DFSDM_ConfigBRKShortCircuitDetector(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState);
|
||||
void DFSDM_ConfigBRKAnalogWatchDog(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState);
|
||||
void DFSDM_ConfigShortCircuitThreshold(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDThreshold);
|
||||
void DFSDM_ConfigAnalogWatchdog(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint32_t DFSDM_AWDFastMode);
|
||||
void DFSDM_ConfigAWDFilter(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t AWD_SincOrder, uint32_t AWD_SincOverSampleRatio);
|
||||
uint32_t DFSDM_GetAWDConversionValue(DFSDM_Channel_TypeDef* DFSDM_Channelx);
|
||||
void DFSDM_SetAWDThreshold(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_HighThreshold, uint32_t DFSDM_LowThreshold);
|
||||
void DFSDM_SelectExtremesDetectorChannel(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_ExtremChannelx);
|
||||
int32_t DFSDM_GetRegularConversionData(DFSDM_TypeDef* DFSDMx);
|
||||
int32_t DFSDM_GetInjectedConversionData(DFSDM_TypeDef* DFSDMx);
|
||||
int32_t DFSDM_GetMaxValue(DFSDM_TypeDef* DFSDMx);
|
||||
int32_t DFSDM_GetMinValue(DFSDM_TypeDef* DFSDMx);
|
||||
int32_t DFSDM_GetMaxValueChannel(DFSDM_TypeDef* DFSDMx);
|
||||
int32_t DFSDM_GetMinValueChannel(DFSDM_TypeDef* DFSDMx);
|
||||
uint32_t DFSDM_GetConversionTime(DFSDM_TypeDef* DFSDMx);
|
||||
void DFSDM_DMATransferConfig(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_DMAConversionMode, FunctionalState NewState);
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DFSDM_ITConfig(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_IT, FunctionalState NewState);
|
||||
void DFSDM_ITClockAbsenceCmd(FunctionalState NewState);
|
||||
void DFSDM_ITShortCircuitDetectorCmd(FunctionalState NewState);
|
||||
|
||||
FlagStatus DFSDM_GetFlagStatus(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_FLAG);
|
||||
FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t DFSDM_FLAG_CLKAbsence);
|
||||
FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t DFSDM_FLAG_SCD);
|
||||
FlagStatus DFSDM_GetWatchdogFlagStatus(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold);
|
||||
|
||||
void DFSDM_ClearFlag(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_CLEARF);
|
||||
void DFSDM_ClearClockAbsenceFlag(uint32_t DFSDM_CLEARF_CLKAbsence);
|
||||
void DFSDM_ClearShortCircuitFlag(uint32_t DFSDM_CLEARF_SCD);
|
||||
void DFSDM_ClearAnalogWatchdogFlag(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold);
|
||||
|
||||
ITStatus DFSDM_GetITStatus(DFSDM_TypeDef* DFSDMx, uint32_t DFSDM_IT);
|
||||
ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t DFSDM_IT_CLKAbsence);
|
||||
ITStatus DFSDM_GetGetShortCircuitITStatus(uint32_t DFSDM_IT_SCR);
|
||||
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4XX_DFSDM_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_dma2d.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the DMA2D firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_dsi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief Header file of DSI module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -164,10 +164,10 @@ typedef struct
|
|||
|
||||
uint32_t ColorCoding; /*!< Color coding for LTDC interface
|
||||
This parameter can be any value of @ref DSI_Color_Coding */
|
||||
|
||||
|
||||
uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
|
||||
pixels. This parameter can be any value between 0x00 and 0xFFFF */
|
||||
|
||||
|
||||
uint32_t TearingEffectSource; /*!< Tearing effect source
|
||||
This parameter can be any value of @ref DSI_TearingEffectSource */
|
||||
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the EXTI firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -171,10 +171,10 @@ typedef enum
|
|||
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
|
||||
#if defined (STM32F40_41xxx)
|
||||
#if defined (STM32F40_41xxx) || defined(STM32F412xG)
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\
|
||||
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
|
||||
#endif /* STM32F40_41xxx */
|
||||
#endif /* STM32F40_41xxx || STM32F412xG */
|
||||
|
||||
#if defined (STM32F401xx)
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_flash_ramfunc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief Header file of FLASH RAMFUNC driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_fmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the FMC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -1,15 +1,15 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_fmpi2c.h
|
||||
* @file stm32f4xx_fmpi2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the I2C Fast Mode
|
||||
* Plus firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
/** @addtogroup FMPI2C
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -350,7 +350,6 @@ typedef struct
|
|||
((IT) == FMPI2C_IT_ARLO) || ((IT) == FMPI2C_IT_OVR) || \
|
||||
((IT) == FMPI2C_IT_PECERR) || ((IT) == FMPI2C_IT_TIMEOUT) || \
|
||||
((IT) == FMPI2C_IT_ALERT))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -410,7 +409,6 @@ void FMPI2C_Cmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
|
|||
void FMPI2C_SoftwareResetCmd(FMPI2C_TypeDef* FMPI2Cx);
|
||||
void FMPI2C_ITConfig(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT, FunctionalState NewState);
|
||||
void FMPI2C_StretchClockCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
|
||||
void FMPI2C_StopModeCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
|
||||
void FMPI2C_DualAddressCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
|
||||
void FMPI2C_OwnAddress2Config(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address, uint8_t Mask);
|
||||
void FMPI2C_GeneralCallCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
|
||||
|
|
@ -458,7 +456,7 @@ void FMPI2C_ClearFlag(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_FLAG);
|
|||
ITStatus FMPI2C_GetITStatus(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT);
|
||||
void FMPI2C_ClearITPendingBit(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT);
|
||||
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_fsmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the FSMC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the GPIO firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -286,7 +286,7 @@ typedef struct
|
|||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
#define GPIO_AF_FMPI2C ((uint8_t)0x04) /* FMPI2C Alternate Function mapping */
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
|
||||
|
|
@ -309,6 +309,10 @@ typedef struct
|
|||
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
|
||||
#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
|
||||
#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
|
||||
#define GPIO_AF_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping (only for STM32F412xG Devices) */
|
||||
#if defined(STM32F412xG)
|
||||
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
|
|
@ -331,6 +335,11 @@ typedef struct
|
|||
#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
|
||||
#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
|
||||
#if defined(STM32F412xG)
|
||||
#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM Alternate Function mapping */
|
||||
#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */
|
||||
#endif /* STM32F412xG */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
|
||||
#define GPIO_AF_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
|
||||
|
|
@ -344,18 +353,18 @@ typedef struct
|
|||
#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F410xx/STM32F411xE Devices) */
|
||||
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
|
||||
#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F410xx/STM32F411xE/STM32F412xG Devices) */
|
||||
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE/STM32F412xG Devices) */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF9_SAI2 ((uint8_t)0x09) /* SAI2 Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QuadSPI Alternate Function mapping */
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#if defined(STM32F410xx)
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG)
|
||||
#define GPIO_AF9_FMPI2C ((uint8_t)0x09) /* FMPI2C Alternate Function mapping (Only for STM32F410xx Devices) */
|
||||
#endif /* STM32F410xx */
|
||||
#endif /* STM32F410xx || STM32F412xG */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
|
|
@ -365,9 +374,13 @@ typedef struct
|
|||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QuadSPI Alternate Function mapping */
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
#if defined(STM32F412xG)
|
||||
#define GPIO_AF10_FMC ((uint8_t)0xA) /* FMC Alternate Function mapping */
|
||||
#define GPIO_AF10_DFSDM ((uint8_t)0xA) /* DFSDM Alternate Function mapping */
|
||||
#endif /* STM32F412xG */
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
|
|
@ -376,9 +389,9 @@ typedef struct
|
|||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#if defined(STM32F40_41xxx)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F412xG)
|
||||
#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
|
||||
#endif /* STM32F40_41xxx */
|
||||
#endif /* STM32F40_41xxx || STM32F412xG */
|
||||
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
|
||||
|
|
@ -475,6 +488,10 @@ typedef struct
|
|||
((AF) == GPIO_AF_LTDC))
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
|
||||
#endif /* STM32F446xx */
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the HASH
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the I2C firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the IWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_lptim.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the LPTIM
|
||||
* firmware library
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_ltdc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the LTDC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -156,13 +156,15 @@ typedef struct
|
|||
/**
|
||||
* @brief LTDC Position structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LTDC_POSX; /*!< Current X Position */
|
||||
uint32_t LTDC_POSY; /*!< Current Y Position */
|
||||
} LTDC_PosTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LTDC RGB structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LTDC_BlueWidth; /*!< Blue width */
|
||||
|
|
@ -170,6 +172,9 @@ typedef struct
|
|||
uint32_t LTDC_RedWidth; /*!< Red width */
|
||||
} LTDC_RGBTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LTDC Color Keying structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LTDC_ColorKeyBlue; /*!< Configures the color key blue value.
|
||||
|
|
@ -182,6 +187,9 @@ typedef struct
|
|||
This parameter must range from 0x00 to 0xFF. */
|
||||
} LTDC_ColorKeying_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LTDC CLUT structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LTDC_CLUTAdress; /*!< Configures the CLUT address.
|
||||
|
|
@ -198,9 +206,8 @@ typedef struct
|
|||
} LTDC_CLUT_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup LTDC_Exported_Constants
|
||||
* @}
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_SYNC
|
||||
|
|
@ -218,11 +225,10 @@ typedef struct
|
|||
#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC)
|
||||
#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC)
|
||||
#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_HSPolarity
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -230,12 +236,11 @@ typedef struct
|
|||
#define LTDC_HSPolarity_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
|
||||
|
||||
#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \
|
||||
((HSPOL) == LTDC_HSPolarity_AH))
|
||||
|
||||
((HSPOL) == LTDC_HSPolarity_AH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_VSPolarity
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -244,11 +249,10 @@ typedef struct
|
|||
|
||||
#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \
|
||||
((VSPOL) == LTDC_VSPolarity_AH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_DEPolarity
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -257,7 +261,6 @@ typedef struct
|
|||
|
||||
#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_VSPolarity_AL) || \
|
||||
((DEPOL) == LTDC_DEPolarity_AH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -270,7 +273,6 @@ typedef struct
|
|||
|
||||
#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPolarity_IPC) || \
|
||||
((PCPOL) == LTDC_PCPolarity_IIPC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -283,71 +285,58 @@ typedef struct
|
|||
|
||||
#define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \
|
||||
((RELOAD) == LTDC_VBReload))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_Back_Color
|
||||
* @{
|
||||
*/
|
||||
|
||||
*/
|
||||
#define LTDC_Back_Color ((uint32_t)0x000000FF)
|
||||
|
||||
#define IS_LTDC_BackBlueValue(BBLUE) ((BBLUE) <= LTDC_Back_Color)
|
||||
#define IS_LTDC_BackGreenValue(BGREEN) ((BGREEN) <= LTDC_Back_Color)
|
||||
#define IS_LTDC_BackRedValue(BRED) ((BRED) <= LTDC_Back_Color)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_Position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LTDC_POS_CY LTDC_CPSR_CYPOS
|
||||
#define LTDC_POS_CX LTDC_CPSR_CXPOS
|
||||
|
||||
#define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_LIPosition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_CurrentStatus
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LTDC_CD_VDES LTDC_CDSR_VDES
|
||||
#define LTDC_CD_HDES LTDC_CDSR_HDES
|
||||
#define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS
|
||||
#define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS
|
||||
|
||||
|
||||
#define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \
|
||||
((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
*/
|
||||
#define LTDC_IT_LI LTDC_IER_LIE
|
||||
#define LTDC_IT_FU LTDC_IER_FUIE
|
||||
#define LTDC_IT_TERR LTDC_IER_TERRIE
|
||||
|
|
@ -358,24 +347,21 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LTDC_FLAG_LI LTDC_ISR_LIF
|
||||
#define LTDC_FLAG_FU LTDC_ISR_FUIF
|
||||
#define LTDC_FLAG_TERR LTDC_ISR_TERRIF
|
||||
#define LTDC_FLAG_RR LTDC_ISR_RRIF
|
||||
|
||||
|
||||
#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
|
||||
((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_Pixelformat
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -396,39 +382,32 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_BlendingFactor1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400)
|
||||
#define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600)
|
||||
|
||||
#define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_BlendingFactor2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005)
|
||||
#define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007)
|
||||
|
||||
#define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup LTDC_LAYER_Config
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LTDC_STOPPosition ((uint32_t)0x0000FFFF)
|
||||
#define LTDC_STARTPosition ((uint32_t)0x00000FFF)
|
||||
|
||||
|
|
@ -447,26 +426,20 @@ typedef struct
|
|||
#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer)
|
||||
|
||||
#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber)
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_colorkeying_Config
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LTDC_colorkeyingConfig ((uint32_t)0x000000FF)
|
||||
|
||||
#define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LTDC_CLUT_Config
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -477,7 +450,6 @@ typedef struct
|
|||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the LTDC configuration to the default reset state *****/
|
||||
void LTDC_DeInit(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the PWR firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -102,27 +102,27 @@
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/** @defgroup PWR_Wake_Up_Pin
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WakeUp_Pin1 ((uint32_t)0x00)
|
||||
#define PWR_WakeUp_Pin2 ((uint32_t)0x01)
|
||||
#if defined(STM32F410xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG)
|
||||
#define PWR_WakeUp_Pin3 ((uint32_t)0x02)
|
||||
#endif /* STM32F410xx */
|
||||
#endif /* STM32F410xx || STM32F412xG */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || \
|
||||
((PIN) == PWR_WakeUp_Pin2))
|
||||
#else /* STM32F410xx */
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3))
|
||||
#else /* STM32F410xx || STM32F412xG */
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || ((PIN) == PWR_WakeUp_Pin2) || \
|
||||
((PIN) == PWR_WakeUp_Pin3))
|
||||
#endif /* STM32F446xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry
|
||||
* @{
|
||||
|
|
@ -196,9 +196,9 @@ void PWR_PVDCmd(FunctionalState NewState);
|
|||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
|
||||
void PWR_WakeUpPinCmd(FunctionalState NewState);
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) ||defined(STM32F446xx)
|
||||
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState);
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
/* Main and Backup Regulators configuration functions *************************/
|
||||
void PWR_BackupRegulatorCmd(FunctionalState NewState);
|
||||
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
|
||||
|
|
@ -211,10 +211,10 @@ void PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState);
|
|||
void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState);
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
|
||||
|
||||
#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE)
|
||||
#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG)
|
||||
void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState);
|
||||
void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState);
|
||||
#endif /* STM32F401xx || STM32F410xx || STM32F411xE */
|
||||
#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG */
|
||||
|
||||
/* FLASH Power Down configuration functions ***********************************/
|
||||
void PWR_FlashPowerDownCmd(FunctionalState NewState);
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_qspi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the QSPI
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
/** @addtogroup QSPI
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -131,11 +131,10 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define QSPI_SShift_NoShift ((uint32_t)0x00000000)
|
||||
#define QSPI_SShift_HalfCycleShift ((uint32_t)QUADSPI_CR_SSHIFT_0)
|
||||
#define QSPI_SShift_OneCycleShift ((uint32_t)QUADSPI_CR_SSHIFT_1)
|
||||
#define QSPI_SShift_OneAndHalfCycleShift ((uint32_t)QUADSPI_CR_SSHIFT)
|
||||
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SShift_NoShift) || ((SSHIFT) == QSPI_SShift_HalfCycleShift) || \
|
||||
((SSHIFT) == QSPI_SShift_OneCycleShift) || ((SSHIFT) == QSPI_SShift_OneAndHalfCycleShift))
|
||||
#define QSPI_SShift_HalfCycleShift ((uint32_t)QUADSPI_CR_SSHIFT)
|
||||
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SShift_NoShift) || ((SSHIFT) == QSPI_SShift_HalfCycleShift))
|
||||
/* Legacy Defines */
|
||||
#define QUADSPI_CR_SSHIFT_0 QUADSPI_CR_SSHIFT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -476,7 +475,7 @@ ITStatus QSPI_GetITStatus(uint32_t QSPI_IT);
|
|||
void QSPI_ClearITPendingBit(uint32_t QSPI_IT);
|
||||
uint32_t QSPI_GetFMode(void);
|
||||
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @brief This file contains all the functions prototypes for the RCC firmware library.
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the RCC firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -108,17 +108,20 @@ typedef struct
|
|||
#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
#endif /* STM32F410xx || STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
|
||||
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F446xx)
|
||||
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
|
||||
#elif defined(STM32F412xG)
|
||||
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#else
|
||||
#endif /* STM32F446xx */
|
||||
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
|
|
@ -137,7 +140,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
|
||||
|
|
@ -313,8 +316,10 @@ typedef struct
|
|||
#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
|
||||
#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
|
||||
|
||||
#define IS_RCC_LPTIM1_SOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
|
||||
((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
|
||||
#define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
|
||||
((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
|
||||
/* Legacy Defines */
|
||||
#define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -325,13 +330,15 @@ typedef struct
|
|||
#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000)
|
||||
#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
|
||||
#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
|
||||
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \
|
||||
((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F410xx */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/** @defgroup RCC_I2S_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -355,7 +362,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
/** @defgroup RCC_SAI_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -380,6 +387,7 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
|
||||
/** @defgroup RCC_I2S_Clock_Source
|
||||
|
|
@ -446,7 +454,7 @@ typedef struct
|
|||
*/
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/** @defgroup RCC_SDIO_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -462,14 +470,22 @@ typedef struct
|
|||
/** @defgroup RCC_48MHZ_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define RCC_48MHZCLKSource_PLL ((uint8_t)0x00)
|
||||
#define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01)
|
||||
#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
|
||||
((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#if defined(STM32F412xG)
|
||||
#define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00)
|
||||
#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG Devices */
|
||||
#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \
|
||||
((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ))
|
||||
#endif /* STM32F412xG */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
/** @defgroup RCC_SPDIFRX_Clock_Source_Selection
|
||||
|
|
@ -512,7 +528,7 @@ typedef struct
|
|||
*/
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F4446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/** @defgroup RCC_FMPI2C1_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -521,11 +537,33 @@ typedef struct
|
|||
#define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
|
||||
|
||||
#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
|
||||
((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
|
||||
((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F410xx || STM32F4446xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
/** @defgroup RCC_DFSDM_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_DFSDM1CLKSource_APB ((uint8_t)0x00)
|
||||
#define RCC_DFSDM1CLKSource_SYS ((uint8_t)0x01)
|
||||
#define IS_RCC_DFSDM1CLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSource_APB) || ((SOURCE) == RCC_DFSDM1CLKSource_SYS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
|
||||
#define IS_RCC_DFSDMACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/** @defgroup RCC_AHB1_Peripherals
|
||||
* @{
|
||||
|
|
@ -574,7 +612,7 @@ typedef struct
|
|||
#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
|
||||
#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
|
||||
#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
|
||||
|
|
@ -602,6 +640,12 @@ typedef struct
|
|||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
|
||||
#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
|
||||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -634,7 +678,7 @@ typedef struct
|
|||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||
#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||
|
|
@ -679,9 +723,12 @@ typedef struct
|
|||
#if defined(STM32F469_479xx)
|
||||
#define RCC_APB2Periph_DSI ((uint32_t)0x08000000)
|
||||
#endif /* STM32F469_479xx */
|
||||
#if defined(STM32F412xG)
|
||||
#define RCC_APB2Periph_DFSDM ((uint32_t)0x01000000)
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF30880CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF30886CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF20880CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF20886CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -782,9 +829,9 @@ void RCC_LSICmd(FunctionalState NewState);
|
|||
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
|
||||
#endif /* STM32F410xx || STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
|
||||
|
|
@ -801,9 +848,9 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2S
|
|||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
void RCC_PLLSAICmd(FunctionalState NewState);
|
||||
#if defined(STM32F469_479xx)
|
||||
|
|
@ -833,10 +880,12 @@ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
|||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
|
||||
#if defined(STM32F446xx)
|
||||
void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
|
||||
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
|
||||
|
|
@ -879,11 +928,11 @@ void RCC_LSEModeConfig(uint8_t RCC_Mode);
|
|||
void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
/* Features available only for STM32F446xx/STM32F469_479xx devices */
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/* Features available only for STM32F412xG/STM32F446xx/STM32F469_479xx devices */
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
/* Features available only for STM32F446xx devices */
|
||||
#if defined(STM32F446xx)
|
||||
|
|
@ -892,10 +941,10 @@ void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
|
|||
void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
/* Features available only for STM32F410xx/STM32F446xx devices */
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
/* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
|
||||
/* Features available only for STM32F410xx devices */
|
||||
#if defined(STM32F410xx)
|
||||
|
|
@ -905,6 +954,10 @@ void RCC_MCO1Cmd(FunctionalState NewState);
|
|||
void RCC_MCO2Cmd(FunctionalState NewState);
|
||||
#endif /* STM32F410xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDM1CLKSource);
|
||||
void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource);
|
||||
#endif /* STM32F412xG */
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_rng.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the Random
|
||||
* Number Generator(RNG) firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
/** @addtogroup RNG
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
|
@ -102,7 +102,7 @@ FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
|
|||
void RNG_ClearFlag(uint8_t RNG_FLAG);
|
||||
ITStatus RNG_GetITStatus(uint8_t RNG_IT);
|
||||
void RNG_ClearITPendingBit(uint8_t RNG_IT);
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F429_439xx || STM32F469_479xx */
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F412xG || STM32F429_439xx || STM32F469_479xx */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the RTC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -591,8 +591,9 @@ typedef struct
|
|||
/** @defgroup RTC_Tamper_Pins_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Tamper_1 RTC_TAFCR_TAMP1E
|
||||
#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))
|
||||
#define RTC_Tamper_1 RTC_TAFCR_TAMP1E
|
||||
#define RTC_Tamper_2 RTC_TAFCR_TAMP2E
|
||||
#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1) || ((TAMPER) == RTC_Tamper_2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -601,10 +602,13 @@ typedef struct
|
|||
/** @defgroup RTC_Tamper_Pin_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperPin_PC13 ((uint32_t)0x00000000)
|
||||
#define RTC_TamperPin_PI8 ((uint32_t)0x00010000)
|
||||
#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \
|
||||
((PIN) == RTC_TamperPin_PI8))
|
||||
#define RTC_TamperPin_Default ((uint32_t)0x00000000)
|
||||
#define RTC_TamperPin_Pos1 ((uint32_t)0x00010000)
|
||||
#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_Default) || \
|
||||
((PIN) == RTC_TamperPin_Pos1))
|
||||
/* Legacy Defines */
|
||||
#define RTC_TamperPin_PC13 RTC_TamperPin_Default
|
||||
#define RTC_TamperPin_PI8 RTC_TamperPin_Pos1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -616,6 +620,7 @@ typedef struct
|
|||
#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000)
|
||||
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \
|
||||
((PIN) == RTC_TimeStampPin_PI8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -716,6 +721,7 @@ typedef struct
|
|||
*/
|
||||
#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
|
||||
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
|
||||
#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
|
||||
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
|
||||
#define RTC_FLAG_TSF ((uint32_t)0x00000800)
|
||||
#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
|
||||
|
|
@ -734,7 +740,7 @@ typedef struct
|
|||
((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
|
||||
((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
|
||||
((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \
|
||||
((FLAG) == RTC_FLAG_SHPF))
|
||||
((FLAG) == RTC_FLAG_TAMP2F) ||((FLAG) == RTC_FLAG_SHPF))
|
||||
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -749,12 +755,13 @@ typedef struct
|
|||
#define RTC_IT_ALRA ((uint32_t)0x00001000)
|
||||
#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
|
||||
#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
|
||||
#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
|
||||
|
||||
#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
|
||||
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
|
||||
((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
|
||||
((IT) == RTC_IT_TAMP1))
|
||||
#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))
|
||||
((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2))
|
||||
#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF90FFF) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_sai.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the SAI
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_sdio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the SDIO firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_spdifrx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the SPDIFRX firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the SPI
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_syscfg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the SYSCFG firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -132,9 +132,9 @@
|
|||
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
|
||||
#define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04)
|
||||
|
||||
#if defined (STM32F40_41xxx)
|
||||
#if defined (STM32F40_41xxx) || defined(STM32F412xG)
|
||||
#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
|
||||
#endif /* STM32F40_41xxx */
|
||||
#endif /* STM32F40_41xxx || STM32F412xG */
|
||||
|
||||
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
|
||||
#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02)
|
||||
|
|
@ -144,12 +144,12 @@
|
|||
#define SYSCFG_MemoryRemap_ExtMEM ((uint8_t)0x02)
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined (STM32F40_41xxx)
|
||||
#if defined (STM32F40_41xxx) || defined(STM32F412xG)
|
||||
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_FSMC))
|
||||
#endif /* STM32F40_41xxx */
|
||||
#endif /* STM32F40_41xxx || defined(STM32F412xG */
|
||||
|
||||
#if defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
|
||||
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
|
||||
|
|
@ -173,13 +173,13 @@
|
|||
((REMAP) == SYSCFG_MemoryRemap_SDRAM))
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F410xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG)
|
||||
#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVDL
|
||||
#define SYSCFG_Break_HardFault SYSCFG_CFGR2_CLL
|
||||
|
||||
#define IS_SYSCFG_LOCK_CONFIG(BREAK) (((BREAK) == SYSCFG_Break_PVD) || \
|
||||
((BREAK) == SYSCFG_Break_PVD))
|
||||
#endif /* STM32F410xx */
|
||||
((BREAK) == SYSCFG_Break_HardFault))
|
||||
#endif /* STM32F410xx || STM32F412xG */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -211,9 +211,9 @@ void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinS
|
|||
void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface);
|
||||
void SYSCFG_CompensationCellCmd(FunctionalState NewState);
|
||||
FlagStatus SYSCFG_GetCompensationCellStatus(void);
|
||||
#if defined(STM32F410xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG)
|
||||
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
|
||||
#endif /* STM32F410xx */
|
||||
#endif /* STM32F410xx || STM32F412xG */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_tim.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the TIM firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_usart.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the USART
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the WWDG firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file misc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides all the miscellaneous firmware functions (add-on
|
||||
* to CMSIS functions).
|
||||
*
|
||||
|
|
@ -55,7 +55,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_adc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
|
||||
* + Initialization and Configuration (in addition to ADC multi mode
|
||||
|
|
@ -85,7 +85,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_can.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Controller area network (CAN) peripheral:
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -63,7 +63,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_cec.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Consumer Electronics Control (CEC) peripheral
|
||||
* applicable only on STM32F446xx devices:
|
||||
|
|
@ -72,7 +72,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides all the CRC firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_cryp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Cryptographic processor (CRYP) peripheral:
|
||||
* + Initialization and Configuration functions
|
||||
|
|
@ -143,7 +143,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_cryp_aes.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides high level functions to encrypt and decrypt an
|
||||
* input message using AES in ECB/CBC/CTR/GCM/CCM modes.
|
||||
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
|
||||
|
|
@ -34,7 +34,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_cryp_des.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides high level functions to encrypt and decrypt an
|
||||
* input message using DES in ECB/CBC modes.
|
||||
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
|
||||
|
|
@ -27,7 +27,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_cryp_tdes.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides high level functions to encrypt and decrypt an
|
||||
* input message using TDES in ECB/CBC modes .
|
||||
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
|
||||
|
|
@ -27,7 +27,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
|
||||
* + DAC channels configuration: trigger, output buffer, data format
|
||||
|
|
@ -109,7 +109,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_dbgmcu.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides all the DBGMCU firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_dcmi.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the DCMI peripheral:
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -65,7 +65,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
1441
lib/main/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dfsdm.c
Normal file
1441
lib/main/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dfsdm.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access controller (DMA):
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -103,7 +103,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_dma2d.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the DMA2D controller (DMA2D) peripheral:
|
||||
* + Initialization and configuration
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_dsi.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Display Serial Interface (DSI):
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -23,7 +23,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_exti.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the EXTI peripheral:
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -47,7 +47,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_flash.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the FLASH peripheral:
|
||||
* + FLASH Interface configuration
|
||||
|
|
@ -51,7 +51,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -266,8 +266,8 @@
|
|||
* @arg FLASH_Latency_14: FLASH Fourteen Latency cycles
|
||||
* @arg FLASH_Latency_15: FLASH Fifteen Latency cycles
|
||||
*
|
||||
* @note For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx/411xE devices this parameter
|
||||
* can be a value between FLASH_Latency_0 and FLASH_Latency_7.
|
||||
* @note For STM32F405xx/407xx, STM32F415xx/417xx, STM32F401xx/411xE and STM32F412xG devices
|
||||
* this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7.
|
||||
*
|
||||
* @note For STM32F42xxx/43xxx devices this parameter can be a value between
|
||||
* FLASH_Latency_0 and FLASH_Latency_15.
|
||||
|
|
@ -449,7 +449,7 @@ void FLASH_Lock(void)
|
|||
* For STM32F401xx devices this parameter can be a value between
|
||||
* FLASH_Sector_0 and FLASH_Sector_5.
|
||||
*
|
||||
* For STM32F411xE devices this parameter can be a value between
|
||||
* For STM32F411xE and STM32F412xG devices this parameter can be a value between
|
||||
* FLASH_Sector_0 and FLASH_Sector_7.
|
||||
*
|
||||
* For STM32F410xx devices this parameter can be a value between
|
||||
|
|
@ -565,7 +565,7 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
|
|||
if(status == FLASH_COMPLETE)
|
||||
{
|
||||
/* if the previous operation is completed, proceed to erase all sectors */
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
FLASH->CR &= CR_PSIZE_MASK;
|
||||
FLASH->CR |= tmp_psize;
|
||||
FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2);
|
||||
|
|
@ -578,7 +578,7 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
|
|||
FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2);
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F446xx)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
FLASH->CR &= CR_PSIZE_MASK;
|
||||
FLASH->CR |= tmp_psize;
|
||||
FLASH->CR |= FLASH_CR_MER;
|
||||
|
|
@ -589,7 +589,7 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
|
|||
|
||||
/* if the erase operation is completed, disable the MER Bit */
|
||||
FLASH->CR &= (~FLASH_CR_MER);
|
||||
#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
|
||||
#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F446xx */
|
||||
|
||||
}
|
||||
/* Return the Erase Status */
|
||||
|
|
@ -1116,7 +1116,8 @@ void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
|
|||
* @brief Enables or disables the read/write protection (PCROP) of the desired
|
||||
* sectors, for the first 1 MB of the Flash.
|
||||
*
|
||||
* @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
|
||||
* @note This function can be used only for STM32F42xxx/43xxx , STM32F401xx/411xE
|
||||
* and STM32F412xG devices.
|
||||
*
|
||||
* @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
|
||||
* This parameter can be one of the following values:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_flash_ramfunc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief FLASH RAMFUNC module driver.
|
||||
* This file provides a FLASH firmware functions which should be
|
||||
* executed from internal SRAM
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_fmc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the FMC peripheral:
|
||||
* + Interface with SRAM, PSRAM, NOR and OneNAND memories
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -232,13 +232,13 @@ void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
|
|||
|
||||
/* NOR/SRAM Bank timing register configuration */
|
||||
FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] =
|
||||
(uint32_t)(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime |
|
||||
(uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime |
|
||||
(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) |
|
||||
(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) |
|
||||
(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) |
|
||||
(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision << 20) |
|
||||
(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency << 24) |
|
||||
FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode);
|
||||
FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode;
|
||||
|
||||
/* NOR/SRAM Bank timing register for write configuration, if extended mode is used */
|
||||
if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable)
|
||||
|
|
@ -248,7 +248,7 @@ void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
|
|||
assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime));
|
||||
assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_BusTurnAroundDuration));
|
||||
assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode));
|
||||
|
||||
|
||||
/* Get the BWTR register value */
|
||||
tmpbwr = FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank];
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_fmpi2c.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Inter-Integrated circuit Fast Mode Plus (FMPI2C):
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -58,7 +58,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -79,15 +79,15 @@
|
|||
#include "stm32f4xx_fmpi2c.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F40x_StdPeriph_Driver
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FMPI2C
|
||||
/** @defgroup FMPI2C FMPI2C
|
||||
* @brief FMPI2C driver modules
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
|
|
@ -368,31 +368,6 @@ void FMPI2C_StretchClockCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
|
|||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables FMPI2Cp from stop mode.
|
||||
* @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
|
||||
* @param NewState: new state of the FMPI2Cx stop mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FMPI2C_StopModeCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable wakeup from stop mode */
|
||||
FMPI2Cx->CR1 |= FMPI2C_CR1_WUPEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable wakeup from stop mode */
|
||||
FMPI2Cx->CR1 &= (uint32_t)~((uint32_t)FMPI2C_CR1_WUPEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the FMPI2C own address 2.
|
||||
* @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
|
||||
|
|
@ -1566,7 +1541,7 @@ void FMPI2C_ClearITPendingBit(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_fsmc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the FSMC peripheral:
|
||||
* + Interface with SRAM, PSRAM, NOR and OneNAND memories
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the GPIO peripheral:
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -63,7 +63,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hash.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the HASH / HMAC Processor (HASH) peripheral:
|
||||
* - Initialization and Configuration functions
|
||||
|
|
@ -102,7 +102,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hash_md5.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides high level functions to compute the HASH MD5 and
|
||||
* HMAC MD5 Digest of an input message.
|
||||
* It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
|
||||
|
|
@ -26,7 +26,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hash_sha1.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides high level functions to compute the HASH SHA1 and
|
||||
* HMAC SHA1 Digest of an input message.
|
||||
* It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
|
||||
|
|
@ -26,7 +26,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_i2c.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Inter-integrated circuit (I2C)
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -71,7 +71,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent watchdog (IWDG) peripheral:
|
||||
* + Prescaler and Counter configuration
|
||||
|
|
@ -64,7 +64,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_lptim.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Low Power Timer (LPT) peripheral:
|
||||
* + Initialization functions.
|
||||
|
|
@ -75,7 +75,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_ltdc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the LTDC controller (LTDC) peripheral:
|
||||
* + Initialization and configuration
|
||||
|
|
@ -55,7 +55,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Backup Domain Access
|
||||
|
|
@ -17,7 +17,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -89,7 +89,7 @@
|
|||
#define CR_LPUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPUDS_BitNumber * 4))
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
|
||||
|
||||
#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE)
|
||||
#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG)
|
||||
/* Alias word address of MRLVDS bit */
|
||||
#define MRLVDS_BitNumber 0x0B
|
||||
#define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4))
|
||||
|
|
@ -97,7 +97,7 @@
|
|||
/* Alias word address of LPLVDS bit */
|
||||
#define LPLVDS_BitNumber 0x0A
|
||||
#define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4))
|
||||
#endif /* STM32F401xx || STM32F410xx || STM32F411xE */
|
||||
#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG */
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
|
||||
|
|
@ -107,18 +107,18 @@
|
|||
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/* Alias word address of EWUP2 bit */
|
||||
#define CSR_OFFSET (PWR_OFFSET + 0x04)
|
||||
#define EWUP1_BitNumber 0x08
|
||||
#define CSR_EWUP1_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP1_BitNumber * 4))
|
||||
#define EWUP2_BitNumber 0x07
|
||||
#define CSR_EWUP2_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4))
|
||||
#if defined(STM32F410xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG)
|
||||
#define EWUP3_BitNumber 0x06
|
||||
#define CSR_EWUP3_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4))
|
||||
#endif /* STM32F410xx */
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#endif /* STM32F410xx || STM32F412xG */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
|
||||
/* Alias word address of BRE bit */
|
||||
#define BRE_BitNumber 0x09
|
||||
|
|
@ -297,14 +297,14 @@ void PWR_WakeUpPinCmd(FunctionalState NewState)
|
|||
}
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/**
|
||||
* @brief Enables or disables the WakeUp Pin functionality.
|
||||
* @param PWR_WakeUpPinx: specifies the WakeUp Pin.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WakeUp_Pin1: WKUP1 pin is used for wakeup from Standby mode.
|
||||
* @arg PWR_WakeUp_Pin2: WKUP2 pin is used for wakeup from Standby mode.
|
||||
* @arg PWR_WakeUp_Pin3: WKUP3 pin is used for wakeup from Standby mode.(only for STM32F410xx)
|
||||
* @arg PWR_WakeUp_Pin3: WKUP3 pin is used for wakeup from Standby mode.(only for STM32F410xx and STM32F412xG Devices)
|
||||
* @param NewState: new state of the WakeUp Pin functionality.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
|
|
@ -318,7 +318,7 @@ void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState)
|
|||
{
|
||||
*(__IO uint32_t *) CSR_EWUP1_BB = (uint32_t)NewState;
|
||||
}
|
||||
#if defined(STM32F410xx)
|
||||
#if defined(STM32F410xx)|| defined(STM32F412xG)
|
||||
else if(PWR_WakeUpPinx == PWR_WakeUp_Pin3) /* PWR_WakeUp_Pin3 */
|
||||
{
|
||||
*(__IO uint32_t *) CSR_EWUP3_BB = (uint32_t)NewState;
|
||||
|
|
@ -329,7 +329,7 @@ void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState)
|
|||
*(__IO uint32_t *) CSR_EWUP2_BB = (uint32_t)NewState;
|
||||
}
|
||||
}
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -589,11 +589,11 @@ void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState)
|
|||
}
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
|
||||
|
||||
#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE)
|
||||
#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG)
|
||||
/**
|
||||
* @brief Enables or disables the Main Regulator low voltage mode.
|
||||
*
|
||||
* @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
|
||||
* @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412xG devices.
|
||||
*
|
||||
* @param NewState: new state of the Main Regulator Low Voltage mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
|
|
@ -617,7 +617,7 @@ void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState)
|
|||
/**
|
||||
* @brief Enables or disables the Low Power Regulator low voltage mode.
|
||||
*
|
||||
* @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
|
||||
* @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412xG devices.
|
||||
*
|
||||
* @param NewState: new state of the Low Power Regulator Low Voltage mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
|
|
@ -637,7 +637,7 @@ void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState)
|
|||
*(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
|
||||
}
|
||||
}
|
||||
#endif /* STM32F401xx || STM32F410xx || STM32F411xE */
|
||||
#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1029,9 +1029,9 @@ void PWR_ClearFlag(uint32_t PWR_FLAG)
|
|||
}
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx */
|
||||
|
||||
#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
|
||||
#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE) || defined(STM32F412xG)
|
||||
PWR->CR |= PWR_FLAG << 2;
|
||||
#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE */
|
||||
#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG */
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_qspi.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Serial peripheral interface (QSPI):
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -61,7 +61,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -89,7 +89,7 @@
|
|||
* @brief QSPI driver modules
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define QSPI_CR_CLEAR_MASK 0x00FFFFCF
|
||||
|
|
@ -898,7 +898,7 @@ void QSPI_DualFlashMode_Cmd(FunctionalState NewState)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_rcc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Reset and clock control (RCC) peripheral:
|
||||
* + Internal/external clocks, PLL, CSS and MCO configuration
|
||||
|
|
@ -38,7 +38,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -445,7 +445,7 @@ void RCC_LSICmd(FunctionalState NewState)
|
|||
*(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/**
|
||||
* @brief Configures the main PLL clock source, multiplication and division factors.
|
||||
* @note This function must be used only when the main PLL is disabled.
|
||||
|
|
@ -498,7 +498,7 @@ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_
|
|||
RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
|
||||
(PLLQ << 24) | (PLLR << 28);
|
||||
}
|
||||
#endif /* STM32F410xx || STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
|
||||
/**
|
||||
|
|
@ -675,7 +675,7 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR)
|
|||
}
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F412xG ) || defined(STM32F446xx)
|
||||
/**
|
||||
* @brief Configures the PLLI2S clock multiplication and division factors.
|
||||
*
|
||||
|
|
@ -721,7 +721,7 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint
|
|||
|
||||
RCC->PLLI2SCFGR = PLLI2SM | (PLLI2SN << 6) | (((PLLI2SP >> 1) -1) << 16) | (PLLI2SQ << 24) | (PLLI2SR << 28);
|
||||
}
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the PLLI2S.
|
||||
|
|
@ -770,7 +770,7 @@ void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint
|
|||
assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ));
|
||||
assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR));
|
||||
|
||||
RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIP << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28);
|
||||
RCC->PLLSAICFGR = (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28);
|
||||
}
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
|
|
@ -1143,7 +1143,7 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
|
|||
* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
|
||||
* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
|
||||
* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source (RCC_SYSCLKSource_PLLPCLK for STM32F446xx devices)
|
||||
* @arg RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F446xx devices
|
||||
* @arg RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F412xG and STM32F446xx devices
|
||||
* @retval None
|
||||
*/
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
|
||||
|
|
@ -1173,7 +1173,7 @@ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
|
|||
* - 0x00: HSI used as system clock
|
||||
* - 0x04: HSE used as system clock
|
||||
* - 0x08: PLL used as system clock (PLL P for STM32F446xx devices)
|
||||
* - 0x0C: PLL R used as system clock (only for STM32F446xx devices)
|
||||
* - 0x0C: PLL R used as system clock (only for STM32F412xG and STM32F446xx devices)
|
||||
*/
|
||||
uint8_t RCC_GetSYSCLKSource(void)
|
||||
{
|
||||
|
|
@ -1317,9 +1317,9 @@ void RCC_PCLK2Config(uint32_t RCC_HCLK)
|
|||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
|
||||
{
|
||||
uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
uint32_t pllr = 2;
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
|
@ -1348,14 +1348,14 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
|
|||
else
|
||||
{
|
||||
/* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
|
||||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||||
RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
|
||||
break;
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
case 0x0C: /* PLL R used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
|
|
@ -1371,13 +1371,13 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
|
|||
else
|
||||
{
|
||||
/* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
|
||||
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
|
||||
RCC_Clocks->SYSCLK_Frequency = pllvco/pllr;
|
||||
break;
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
default:
|
||||
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
|
||||
|
|
@ -1523,7 +1523,7 @@ void RCC_BackupResetCmd(FunctionalState NewState)
|
|||
*(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#if defined (STM32F412xG) || defined(STM32F446xx)
|
||||
/**
|
||||
* @brief Configures the I2S clock source (I2SCLK).
|
||||
* @note This function must be called before enabling the I2S APB clock.
|
||||
|
|
@ -1563,7 +1563,7 @@ void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource)
|
|||
RCC->DCKCFGR |= (RCC_I2SCLKSource << 2);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
/**
|
||||
* @brief Configures the SAIx clock source (SAIxCLK).
|
||||
* @note This function must be called before enabling the SAIx APB clock.
|
||||
|
|
@ -1603,6 +1603,7 @@ void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource)
|
|||
}
|
||||
}
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F410xx)
|
||||
/**
|
||||
|
|
@ -1822,6 +1823,66 @@ void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
|
|||
RCC->DCKCFGR = tmpreg;
|
||||
}
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
/**
|
||||
* @brief Configures the DFSDM clock source (DFSDMCLK).
|
||||
* @note This function must be called before enabling the DFSDM APB clock.
|
||||
* @param RCC_DFSDMCLKSource: specifies the DFSDM clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_DFSDM1CLKSource_APB: APB clock used as DFSDM clock source.
|
||||
* @arg RCC_DFSDM1CLKSource_SYS: System clock used as DFSDM clock source.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDM1CLKSource)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_DFSDM1CLK_SOURCE(RCC_DFSDM1CLKSource));
|
||||
|
||||
tmpreg = RCC->DCKCFGR;
|
||||
|
||||
/* Clear CKDFSDM-SEL bit */
|
||||
tmpreg &= ~RCC_DCKCFGR_CKDFSDM1SEL;
|
||||
|
||||
/* Set CKDFSDM-SEL bit according to RCC_DFSDMCLKSource value */
|
||||
tmpreg |= (RCC_DFSDM1CLKSource << 31) ;
|
||||
|
||||
/* Store the new value */
|
||||
RCC->DCKCFGR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the DFSDM Audio clock source (DFSDMACLK).
|
||||
* @note This function must be called before enabling the DFSDM APB clock.
|
||||
* @param RCC_DFSDMACLKSource: specifies the DFSDM clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source.
|
||||
* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDMACLKSource)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_DFSDMACLK_SOURCE(RCC_DFSDMACLKSource));
|
||||
|
||||
tmpreg = RCC->DCKCFGR;
|
||||
|
||||
/* Clear CKDFSDMA SEL bit */
|
||||
tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL;
|
||||
|
||||
/* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */
|
||||
tmpreg |= RCC_DFSDMACLKSource;
|
||||
|
||||
/* Store the new value */
|
||||
RCC->DCKCFGR = tmpreg;
|
||||
}
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/**
|
||||
* @brief Configures the Timers clocks prescalers selection.
|
||||
*
|
||||
|
|
@ -1930,7 +1991,7 @@ void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
|
|||
}
|
||||
}
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/**
|
||||
* @brief Enables or disables the AHB3 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
|
|
@ -1938,8 +1999,8 @@ void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
|
|||
* using it.
|
||||
* @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
|
||||
* This parameter must be:
|
||||
* - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
|
||||
* - RCC_AHB3Periph_QSPI (STM32F446xx/STM32F469_479xx devices)
|
||||
* - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F429x/439x devices)
|
||||
* - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices)
|
||||
* @param NewState: new state of the specified peripheral clock.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
|
|
@ -1959,7 +2020,7 @@ void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
|
|||
RCC->AHB3ENR &= ~RCC_AHB3Periph;
|
||||
}
|
||||
}
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F40_41xxx || STM32F412xG || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
|
||||
|
|
@ -2043,7 +2104,8 @@ void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
|||
* @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx devices)
|
||||
* @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
|
||||
* @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
|
||||
* @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
|
||||
* @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
|
||||
* @arg RCC_APB2Periph_DFSDM: DFSDM Clock (STM32F412xG Devices)
|
||||
* @param NewState: new state of the specified peripheral clock.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
|
|
@ -2114,7 +2176,7 @@ void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
|
|||
* @arg RCC_AHB2Periph_DCMI: DCMI clock
|
||||
* @arg RCC_AHB2Periph_CRYP: CRYP clock
|
||||
* @arg RCC_AHB2Periph_HASH: HASH clock
|
||||
* @arg RCC_AHB2Periph_RNG: RNG clock for STM32F40_41xxx/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices
|
||||
* @arg RCC_AHB2Periph_RNG: RNG clock for STM32F40_41xxx/STM32F412xG/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices
|
||||
* @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
|
||||
* @param NewState: new state of the specified peripheral reset.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
|
|
@ -2136,13 +2198,13 @@ void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
|
|||
}
|
||||
}
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/**
|
||||
* @brief Forces or releases AHB3 peripheral reset.
|
||||
* @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
|
||||
* This parameter must be:
|
||||
* - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
|
||||
* - RCC_AHB3Periph_QSPI (STM32F446xx/STM32F469_479xx devices)
|
||||
* - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG and STM32F429x/439x devices)
|
||||
* - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices)
|
||||
* @param NewState: new state of the specified peripheral reset.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
|
|
@ -2162,7 +2224,7 @@ void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
|
|||
RCC->AHB3RSTR &= ~RCC_AHB3Periph;
|
||||
}
|
||||
}
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F40_41xxx || STM32F412xG || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
/**
|
||||
* @brief Forces or releases Low Speed APB (APB1) peripheral reset.
|
||||
|
|
@ -2340,7 +2402,7 @@ void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewSt
|
|||
}
|
||||
}
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/**
|
||||
* @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
|
|
@ -2349,8 +2411,8 @@ void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewSt
|
|||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
|
||||
* This parameter must be:
|
||||
* - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
|
||||
* - RCC_AHB3Periph_QSPI (STM32F446xx/STM32F469_479xx devices)
|
||||
* - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F429x/439x devices)
|
||||
* - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices)
|
||||
* @param NewState: new state of the specified peripheral clock.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
|
|
@ -2369,7 +2431,7 @@ void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewSt
|
|||
RCC->AHB3LPENR &= ~RCC_AHB3Periph;
|
||||
}
|
||||
}
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F40_41xxx || STM32F412xG || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
|
||||
|
|
@ -2548,7 +2610,7 @@ void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
}
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/**
|
||||
* @brief Configures the 48MHz clock Source.
|
||||
* @note This feature is only available for STM32F446xx/STM32F469_479xx devices.
|
||||
|
|
@ -2556,6 +2618,7 @@ void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
* This parameter can be one of the following values:
|
||||
* @arg RCC_48MHZCLKSource_PLL: 48MHz from PLL selected.
|
||||
* @arg RCC_48MHZCLKSource_PLLSAI: 48MHz from PLLSAI selected.
|
||||
* @arg RCC_CK48CLKSOURCE_PLLI2SQ : 48MHz from PLLI2SQ
|
||||
* @retval None
|
||||
*/
|
||||
void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
|
||||
|
|
@ -2571,7 +2634,7 @@ void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
{
|
||||
CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
|
||||
}
|
||||
#elif defined(STM32F446xx)
|
||||
#elif defined(STM32F446xx)
|
||||
if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
|
||||
{
|
||||
SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
|
||||
|
|
@ -2580,6 +2643,15 @@ void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
{
|
||||
CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
|
||||
}
|
||||
#elif defined(STM32F412xG)
|
||||
if(RCC_ClockSource == RCC_CK48CLKSOURCE_PLLI2SQ)
|
||||
{
|
||||
SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
|
||||
}
|
||||
#else
|
||||
#endif /* STM32F469_479xx */
|
||||
}
|
||||
|
|
@ -2606,7 +2678,7 @@ void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
{
|
||||
CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
|
||||
}
|
||||
#elif defined(STM32F446xx)
|
||||
#elif defined(STM32F412xG) || defined(STM32F446xx)
|
||||
if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
|
||||
{
|
||||
SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL);
|
||||
|
|
@ -2618,7 +2690,7 @@ void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
#else
|
||||
#endif /* STM32F469_479xx */
|
||||
}
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
/**
|
||||
|
|
@ -2702,7 +2774,7 @@ void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
}
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/**
|
||||
* @brief Configures the FMPI2C1 clock Source.
|
||||
* @note This feature is only available for STM32F446xx devices.
|
||||
|
|
@ -2723,7 +2795,7 @@ void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource)
|
|||
/* Set new FMPI2C1 clock source */
|
||||
RCC->DCKCFGR2 |= RCC_ClockSource;
|
||||
}
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_rng.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Random Number Generator (RNG) peripheral:
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -35,7 +35,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -64,7 +64,7 @@
|
|||
* @brief RNG driver modules
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
|
@ -393,7 +393,7 @@ void RNG_ClearITPendingBit(uint8_t RNG_IT)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F429_439xx || STM32F469_479xx */
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F412xG || STM32F429_439xx || STM32F469_479xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_rtc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Real-Time Clock (RTC) peripheral:
|
||||
* + Initialization
|
||||
|
|
@ -264,7 +264,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -305,7 +305,7 @@
|
|||
RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
|
||||
RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
|
||||
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
|
||||
RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
|
||||
RTC_FLAG_TAMP2F | RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
|
||||
|
||||
#define INITMODE_TIMEOUT ((uint32_t) 0x00010000)
|
||||
#define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000)
|
||||
|
|
@ -2092,7 +2092,7 @@ uint32_t RTC_GetTimeStampSubSecond(void)
|
|||
/**
|
||||
* @brief Configures the select Tamper pin edge.
|
||||
* @param RTC_Tamper: Selected tamper pin.
|
||||
* This parameter can be RTC_Tamper_1.
|
||||
* This parameter can be RTC_Tamper_1 or RTC_Tamper 2
|
||||
* @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that
|
||||
* stimulates tamper event.
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -2123,7 +2123,7 @@ void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
|
|||
/**
|
||||
* @brief Enables or Disables the Tamper detection.
|
||||
* @param RTC_Tamper: Selected tamper pin.
|
||||
* This parameter can be RTC_Tamper_1.
|
||||
* This parameter can be RTC_Tamper_1 or RTC_Tamper_2
|
||||
* @param NewState: new state of the tamper pin.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
|
|
@ -2356,8 +2356,8 @@ uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
|
|||
* @brief Selects the RTC Tamper Pin.
|
||||
* @param RTC_TamperPin: specifies the RTC Tamper Pin.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin.
|
||||
* @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin.
|
||||
* @arg RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper Pin.
|
||||
* @arg RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper Pin.
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_TamperPinSelection(uint32_t RTC_TamperPin)
|
||||
|
|
@ -2588,6 +2588,7 @@ void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
|
|||
* This parameter can be one of the following values:
|
||||
* @arg RTC_FLAG_RECALPF: RECALPF event flag.
|
||||
* @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
|
||||
* @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
|
||||
* @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
|
||||
* @arg RTC_FLAG_TSF: Time Stamp event flag
|
||||
* @arg RTC_FLAG_WUTF: WakeUp Timer flag
|
||||
|
|
@ -2630,6 +2631,7 @@ FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
|
|||
* @param RTC_FLAG: specifies the RTC flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
|
||||
* @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
|
||||
* @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag
|
||||
* @arg RTC_FLAG_TSF: Time Stamp event flag
|
||||
* @arg RTC_FLAG_WUTF: WakeUp Timer flag
|
||||
|
|
@ -2655,7 +2657,8 @@ void RTC_ClearFlag(uint32_t RTC_FLAG)
|
|||
* @arg RTC_IT_WUT: WakeUp Timer interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_TAMP1: Tamper 1 event interrupt
|
||||
* @arg RTC_IT_TAMP1: Tamper 1 event interrupt
|
||||
* @arg RTC_IT_TAMP2: Tamper 2 event interrupt
|
||||
* @retval The new state of RTC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus RTC_GetITStatus(uint32_t RTC_IT)
|
||||
|
|
@ -2670,7 +2673,7 @@ ITStatus RTC_GetITStatus(uint32_t RTC_IT)
|
|||
tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
|
||||
|
||||
/* Get the Interrupt enable Status */
|
||||
enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)));
|
||||
enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)) | (tmpreg & (RTC_IT >> 16)));
|
||||
|
||||
/* Get the Interrupt pending bit */
|
||||
tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
|
||||
|
|
@ -2695,7 +2698,8 @@ ITStatus RTC_GetITStatus(uint32_t RTC_IT)
|
|||
* @arg RTC_IT_WUT: WakeUp Timer interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_TAMP1: Tamper 1 event interrupt
|
||||
* @arg RTC_IT_TAMP1: Tamper 1 event interrupt
|
||||
* @arg RTC_IT_TAMP2: Tamper 2 event interrupt
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_ClearITPendingBit(uint32_t RTC_IT)
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_sai.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Serial Audio Interface (SAI):
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -105,7 +105,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_sdio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Secure digital input/output interface (SDIO)
|
||||
* peripheral:
|
||||
|
|
@ -135,7 +135,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_spdifrx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Serial Audio Interface (SPDIFRX):
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -13,7 +13,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_spi.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Serial peripheral interface (SPI):
|
||||
* + Initialization and Configuration
|
||||
|
|
@ -138,7 +138,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_syscfg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the SYSCFG peripheral.
|
||||
*
|
||||
@verbatim
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -225,7 +225,7 @@ FlagStatus SYSCFG_GetCompensationCellStatus(void)
|
|||
return bitstatus;
|
||||
}
|
||||
|
||||
#if defined(STM32F410xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG)
|
||||
/**
|
||||
* @brief Connects the selected parameter to the break input of TIM1.
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
|
|
@ -243,7 +243,7 @@ void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
|
|||
|
||||
SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
|
||||
}
|
||||
#endif /* STM32F410xx */
|
||||
#endif /* STM32F410xx || STM32F412xG */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_tim.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the TIM peripheral:
|
||||
* + TimeBase management
|
||||
|
|
@ -98,7 +98,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_usart.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Universal synchronous asynchronous receiver
|
||||
* transmitter (USART):
|
||||
|
|
@ -71,7 +71,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_wwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Window watchdog (WWDG) peripheral:
|
||||
* + Prescaler, Refresh window and Counter configuration
|
||||
|
|
@ -63,7 +63,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue