mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-15 04:15:44 +03:00
STM32F4: Library update
This commit is contained in:
blckmn
parent
5d385d0019
commit
bca73007d6
179 changed files with 5024 additions and 32738 deletions
|
|
@ -2,13 +2,13 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 21-October-2015
|
||||
* @brief This file contains all the functions prototypes for the RCC firmware library.
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the RCC firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
@ -108,17 +108,20 @@ typedef struct
|
|||
#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
#endif /* STM32F410xx || STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
|
||||
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F446xx)
|
||||
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
|
||||
#elif defined(STM32F412xG)
|
||||
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#else
|
||||
#endif /* STM32F446xx */
|
||||
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
|
|
@ -137,7 +140,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
|
||||
|
|
@ -313,8 +316,10 @@ typedef struct
|
|||
#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
|
||||
#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
|
||||
|
||||
#define IS_RCC_LPTIM1_SOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
|
||||
((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
|
||||
#define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
|
||||
((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
|
||||
/* Legacy Defines */
|
||||
#define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -325,13 +330,15 @@ typedef struct
|
|||
#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000)
|
||||
#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
|
||||
#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
|
||||
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \
|
||||
((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F410xx */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/** @defgroup RCC_I2S_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -355,7 +362,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
/** @defgroup RCC_SAI_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -380,6 +387,7 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
|
||||
/** @defgroup RCC_I2S_Clock_Source
|
||||
|
|
@ -446,7 +454,7 @@ typedef struct
|
|||
*/
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/** @defgroup RCC_SDIO_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -462,14 +470,22 @@ typedef struct
|
|||
/** @defgroup RCC_48MHZ_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define RCC_48MHZCLKSource_PLL ((uint8_t)0x00)
|
||||
#define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01)
|
||||
#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
|
||||
((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#if defined(STM32F412xG)
|
||||
#define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00)
|
||||
#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG Devices */
|
||||
#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \
|
||||
((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ))
|
||||
#endif /* STM32F412xG */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
/** @defgroup RCC_SPDIFRX_Clock_Source_Selection
|
||||
|
|
@ -512,7 +528,7 @@ typedef struct
|
|||
*/
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F4446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/** @defgroup RCC_FMPI2C1_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -521,11 +537,33 @@ typedef struct
|
|||
#define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
|
||||
|
||||
#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
|
||||
((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
|
||||
((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F410xx || STM32F4446xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
/** @defgroup RCC_DFSDM_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_DFSDM1CLKSource_APB ((uint8_t)0x00)
|
||||
#define RCC_DFSDM1CLKSource_SYS ((uint8_t)0x01)
|
||||
#define IS_RCC_DFSDM1CLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSource_APB) || ((SOURCE) == RCC_DFSDM1CLKSource_SYS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
|
||||
#define IS_RCC_DFSDMACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/** @defgroup RCC_AHB1_Peripherals
|
||||
* @{
|
||||
|
|
@ -574,7 +612,7 @@ typedef struct
|
|||
#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
|
||||
#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
|
||||
#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
|
||||
|
|
@ -602,6 +640,12 @@ typedef struct
|
|||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
|
||||
#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
|
||||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -634,7 +678,7 @@ typedef struct
|
|||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||
#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||
|
|
@ -679,9 +723,12 @@ typedef struct
|
|||
#if defined(STM32F469_479xx)
|
||||
#define RCC_APB2Periph_DSI ((uint32_t)0x08000000)
|
||||
#endif /* STM32F469_479xx */
|
||||
#if defined(STM32F412xG)
|
||||
#define RCC_APB2Periph_DFSDM ((uint32_t)0x01000000)
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF30880CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF30886CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF20880CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF20886CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -782,9 +829,9 @@ void RCC_LSICmd(FunctionalState NewState);
|
|||
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
|
||||
#endif /* STM32F410xx || STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
|
||||
|
|
@ -801,9 +848,9 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2S
|
|||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
void RCC_PLLSAICmd(FunctionalState NewState);
|
||||
#if defined(STM32F469_479xx)
|
||||
|
|
@ -833,10 +880,12 @@ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
|||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
|
||||
#if defined(STM32F446xx)
|
||||
void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
|
||||
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
|
||||
|
|
@ -879,11 +928,11 @@ void RCC_LSEModeConfig(uint8_t RCC_Mode);
|
|||
void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
/* Features available only for STM32F446xx/STM32F469_479xx devices */
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/* Features available only for STM32F412xG/STM32F446xx/STM32F469_479xx devices */
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
/* Features available only for STM32F446xx devices */
|
||||
#if defined(STM32F446xx)
|
||||
|
|
@ -892,10 +941,10 @@ void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
|
|||
void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
/* Features available only for STM32F410xx/STM32F446xx devices */
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
/* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
|
||||
/* Features available only for STM32F410xx devices */
|
||||
#if defined(STM32F410xx)
|
||||
|
|
@ -905,6 +954,10 @@ void RCC_MCO1Cmd(FunctionalState NewState);
|
|||
void RCC_MCO2Cmd(FunctionalState NewState);
|
||||
#endif /* STM32F410xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDM1CLKSource);
|
||||
void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource);
|
||||
#endif /* STM32F412xG */
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue