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STM32F4: Library update
This commit is contained in:
blckmn
parent
5d385d0019
commit
bca73007d6
179 changed files with 5024 additions and 32738 deletions
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f4xx_rcc.c
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* @author MCD Application Team
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* @version V1.6.1
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* @date 21-October-2015
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* @version V1.7.1
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* @date 20-May-2016
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* @brief This file provides firmware functions to manage the following
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* functionalities of the Reset and clock control (RCC) peripheral:
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* + Internal/external clocks, PLL, CSS and MCO configuration
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@ -38,7 +38,7 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
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* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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@ -445,7 +445,7 @@ void RCC_LSICmd(FunctionalState NewState)
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*(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
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}
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#if defined(STM32F410xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
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#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
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/**
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* @brief Configures the main PLL clock source, multiplication and division factors.
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* @note This function must be used only when the main PLL is disabled.
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@ -498,7 +498,7 @@ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_
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RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
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(PLLQ << 24) | (PLLR << 28);
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}
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#endif /* STM32F410xx || STM32F446xx || STM32F469_479xx */
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#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
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#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
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/**
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@ -675,7 +675,7 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR)
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}
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#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
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#if defined(STM32F446xx)
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#if defined(STM32F412xG ) || defined(STM32F446xx)
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/**
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* @brief Configures the PLLI2S clock multiplication and division factors.
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*
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@ -721,7 +721,7 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint
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RCC->PLLI2SCFGR = PLLI2SM | (PLLI2SN << 6) | (((PLLI2SP >> 1) -1) << 16) | (PLLI2SQ << 24) | (PLLI2SR << 28);
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}
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#endif /* STM32F446xx */
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#endif /* STM32F412xG || STM32F446xx */
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/**
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* @brief Enables or disables the PLLI2S.
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@ -770,7 +770,7 @@ void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint
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assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ));
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assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR));
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RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIP << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28);
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RCC->PLLSAICFGR = (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28);
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}
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#endif /* STM32F469_479xx */
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@ -1143,7 +1143,7 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
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* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
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* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
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* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source (RCC_SYSCLKSource_PLLPCLK for STM32F446xx devices)
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* @arg RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F446xx devices
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* @arg RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F412xG and STM32F446xx devices
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* @retval None
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*/
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void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
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@ -1173,7 +1173,7 @@ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
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* - 0x00: HSI used as system clock
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* - 0x04: HSE used as system clock
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* - 0x08: PLL used as system clock (PLL P for STM32F446xx devices)
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* - 0x0C: PLL R used as system clock (only for STM32F446xx devices)
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* - 0x0C: PLL R used as system clock (only for STM32F412xG and STM32F446xx devices)
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*/
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uint8_t RCC_GetSYSCLKSource(void)
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{
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@ -1317,9 +1317,9 @@ void RCC_PCLK2Config(uint32_t RCC_HCLK)
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void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
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{
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uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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#if defined(STM32F446xx)
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#if defined(STM32F412xG) || defined(STM32F446xx)
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uint32_t pllr = 2;
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#endif /* STM32F446xx */
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#endif /* STM32F412xG || STM32F446xx */
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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@ -1348,14 +1348,14 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
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else
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{
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/* HSI used as PLL clock source */
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pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
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RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
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break;
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#if defined(STM32F446xx)
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#if defined(STM32F412xG) || defined(STM32F446xx)
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case 0x0C: /* PLL R used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
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SYSCLK = PLL_VCO / PLLR
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@ -1371,13 +1371,13 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
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else
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{
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/* HSI used as PLL clock source */
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pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
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RCC_Clocks->SYSCLK_Frequency = pllvco/pllr;
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break;
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#endif /* STM32F446xx */
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#endif /* STM32F412xG || STM32F446xx */
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default:
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RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
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@ -1523,7 +1523,7 @@ void RCC_BackupResetCmd(FunctionalState NewState)
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*(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
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}
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#if defined(STM32F446xx)
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#if defined (STM32F412xG) || defined(STM32F446xx)
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/**
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* @brief Configures the I2S clock source (I2SCLK).
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* @note This function must be called before enabling the I2S APB clock.
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@ -1563,7 +1563,7 @@ void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource)
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RCC->DCKCFGR |= (RCC_I2SCLKSource << 2);
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}
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}
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#if defined(STM32F446xx)
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/**
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* @brief Configures the SAIx clock source (SAIxCLK).
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* @note This function must be called before enabling the SAIx APB clock.
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@ -1603,6 +1603,7 @@ void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource)
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}
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}
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#endif /* STM32F446xx */
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#endif /* STM32F412xG || STM32F446xx */
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#if defined(STM32F410xx)
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/**
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@ -1822,6 +1823,66 @@ void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
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RCC->DCKCFGR = tmpreg;
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}
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#if defined(STM32F412xG)
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/**
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* @brief Configures the DFSDM clock source (DFSDMCLK).
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* @note This function must be called before enabling the DFSDM APB clock.
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* @param RCC_DFSDMCLKSource: specifies the DFSDM clock source.
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* This parameter can be one of the following values:
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* @arg RCC_DFSDM1CLKSource_APB: APB clock used as DFSDM clock source.
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* @arg RCC_DFSDM1CLKSource_SYS: System clock used as DFSDM clock source.
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*
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* @retval None
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*/
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void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDM1CLKSource)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_RCC_DFSDM1CLK_SOURCE(RCC_DFSDM1CLKSource));
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tmpreg = RCC->DCKCFGR;
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/* Clear CKDFSDM-SEL bit */
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tmpreg &= ~RCC_DCKCFGR_CKDFSDM1SEL;
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/* Set CKDFSDM-SEL bit according to RCC_DFSDMCLKSource value */
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tmpreg |= (RCC_DFSDM1CLKSource << 31) ;
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/* Store the new value */
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RCC->DCKCFGR = tmpreg;
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}
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/**
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* @brief Configures the DFSDM Audio clock source (DFSDMACLK).
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* @note This function must be called before enabling the DFSDM APB clock.
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* @param RCC_DFSDMACLKSource: specifies the DFSDM clock source.
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* This parameter can be one of the following values:
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* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source.
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* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.
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*
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* @retval None
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*/
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void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDMACLKSource)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_RCC_DFSDMACLK_SOURCE(RCC_DFSDMACLKSource));
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tmpreg = RCC->DCKCFGR;
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/* Clear CKDFSDMA SEL bit */
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tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL;
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/* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */
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tmpreg |= RCC_DFSDMACLKSource;
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/* Store the new value */
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RCC->DCKCFGR = tmpreg;
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}
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#endif /* STM32F412xG */
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/**
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* @brief Configures the Timers clocks prescalers selection.
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*
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@ -1930,7 +1991,7 @@ void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
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}
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}
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#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
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#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
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/**
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* @brief Enables or disables the AHB3 peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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@ -1938,8 +1999,8 @@ void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
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* using it.
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* @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
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* This parameter must be:
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* - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
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* - RCC_AHB3Periph_QSPI (STM32F446xx/STM32F469_479xx devices)
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* - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F429x/439x devices)
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* - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices)
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* @param NewState: new state of the specified peripheral clock.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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@ -1959,7 +2020,7 @@ void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
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RCC->AHB3ENR &= ~RCC_AHB3Periph;
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}
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}
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#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
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#endif /* STM32F40_41xxx || STM32F412xG || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
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/**
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* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
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@ -2043,7 +2104,8 @@ void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
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* @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx devices)
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* @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
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* @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
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* @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
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* @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
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* @arg RCC_APB2Periph_DFSDM: DFSDM Clock (STM32F412xG Devices)
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* @param NewState: new state of the specified peripheral clock.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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@ -2114,7 +2176,7 @@ void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
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* @arg RCC_AHB2Periph_DCMI: DCMI clock
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* @arg RCC_AHB2Periph_CRYP: CRYP clock
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* @arg RCC_AHB2Periph_HASH: HASH clock
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* @arg RCC_AHB2Periph_RNG: RNG clock for STM32F40_41xxx/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices
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* @arg RCC_AHB2Periph_RNG: RNG clock for STM32F40_41xxx/STM32F412xG/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices
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* @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
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* @param NewState: new state of the specified peripheral reset.
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* This parameter can be: ENABLE or DISABLE.
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@ -2136,13 +2198,13 @@ void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
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}
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}
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#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
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#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
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/**
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* @brief Forces or releases AHB3 peripheral reset.
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* @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
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* This parameter must be:
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* - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
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* - RCC_AHB3Periph_QSPI (STM32F446xx/STM32F469_479xx devices)
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* - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG and STM32F429x/439x devices)
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* - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices)
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* @param NewState: new state of the specified peripheral reset.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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@ -2162,7 +2224,7 @@ void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
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RCC->AHB3RSTR &= ~RCC_AHB3Periph;
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}
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}
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#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
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#endif /* STM32F40_41xxx || STM32F412xG || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
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/**
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* @brief Forces or releases Low Speed APB (APB1) peripheral reset.
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@ -2340,7 +2402,7 @@ void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewSt
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}
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}
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#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
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#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
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/**
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* @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce
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@ -2349,8 +2411,8 @@ void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewSt
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* @note By default, all peripheral clocks are enabled during SLEEP mode.
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* @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
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* This parameter must be:
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* - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
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* - RCC_AHB3Periph_QSPI (STM32F446xx/STM32F469_479xx devices)
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* - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F429x/439x devices)
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* - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices)
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* @param NewState: new state of the specified peripheral clock.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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@ -2369,7 +2431,7 @@ void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewSt
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RCC->AHB3LPENR &= ~RCC_AHB3Periph;
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}
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}
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#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
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#endif /* STM32F40_41xxx || STM32F412xG || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
|
||||
|
|
@ -2548,7 +2610,7 @@ void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
}
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/**
|
||||
* @brief Configures the 48MHz clock Source.
|
||||
* @note This feature is only available for STM32F446xx/STM32F469_479xx devices.
|
||||
|
|
@ -2556,6 +2618,7 @@ void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
* This parameter can be one of the following values:
|
||||
* @arg RCC_48MHZCLKSource_PLL: 48MHz from PLL selected.
|
||||
* @arg RCC_48MHZCLKSource_PLLSAI: 48MHz from PLLSAI selected.
|
||||
* @arg RCC_CK48CLKSOURCE_PLLI2SQ : 48MHz from PLLI2SQ
|
||||
* @retval None
|
||||
*/
|
||||
void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
|
||||
|
|
@ -2571,7 +2634,7 @@ void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
{
|
||||
CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
|
||||
}
|
||||
#elif defined(STM32F446xx)
|
||||
#elif defined(STM32F446xx)
|
||||
if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
|
||||
{
|
||||
SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
|
||||
|
|
@ -2580,6 +2643,15 @@ void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
{
|
||||
CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
|
||||
}
|
||||
#elif defined(STM32F412xG)
|
||||
if(RCC_ClockSource == RCC_CK48CLKSOURCE_PLLI2SQ)
|
||||
{
|
||||
SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
|
||||
}
|
||||
#else
|
||||
#endif /* STM32F469_479xx */
|
||||
}
|
||||
|
|
@ -2606,7 +2678,7 @@ void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
{
|
||||
CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
|
||||
}
|
||||
#elif defined(STM32F446xx)
|
||||
#elif defined(STM32F412xG) || defined(STM32F446xx)
|
||||
if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
|
||||
{
|
||||
SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL);
|
||||
|
|
@ -2618,7 +2690,7 @@ void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
#else
|
||||
#endif /* STM32F469_479xx */
|
||||
}
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
/**
|
||||
|
|
@ -2702,7 +2774,7 @@ void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource)
|
|||
}
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/**
|
||||
* @brief Configures the FMPI2C1 clock Source.
|
||||
* @note This feature is only available for STM32F446xx devices.
|
||||
|
|
@ -2723,7 +2795,7 @@ void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource)
|
|||
/* Set new FMPI2C1 clock source */
|
||||
RCC->DCKCFGR2 |= RCC_ClockSource;
|
||||
}
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue