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Switch to cleaner way of detecting a soft-reset on STM32F103 based targets using RCC->CSR register.

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Konstantin Sharlaimov 2015-03-13 23:42:12 +10:00 • committed by Dominic Clifton
parent 11493cd01a
commit bd6297f0cc
4 changed files with 9 additions and 9 deletions
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4
src/main/drivers/system.c
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@ -76,6 +76,8 @@ void EXTI15_10_IRQHandler(void)
static uint32_t usTicks = 0;
// current uptime for 1kHz systick timer. will rollover after 49 days. hopefully we won't care.
static volatile uint32_t sysTickUptime = 0;
// cached value of RCC->CSR
uint32_t cachedRccCsrValue;
static void cycleCounterInit(void)
{
@ -123,6 +125,8 @@ void systemInit(void)
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
#endif
// cache RCC->CSR value to use it in isMPUSoftreset() and others
cachedRccCsrValue = RCC->CSR;
RCC_ClearFlag();