From be3b321d7a248c0c4bffdba35f2953eabc6fc194 Mon Sep 17 00:00:00 2001 From: jflyper Date: Mon, 22 Jun 2020 01:34:28 +0900 Subject: [PATCH] [G4] Add I2C pins overloaded with SWD pins --- src/main/drivers/bus_i2c_hal_init.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/main/drivers/bus_i2c_hal_init.c b/src/main/drivers/bus_i2c_hal_init.c index 71871fdb20..c677316a3f 100644 --- a/src/main/drivers/bus_i2c_hal_init.c +++ b/src/main/drivers/bus_i2c_hal_init.c @@ -149,8 +149,12 @@ const i2cHardware_t i2cHardware[I2CDEV_COUNT] = { { .device = I2CDEV_1, .reg = I2C1, - .sclPins = { I2CPINDEF(PA15, GPIO_AF4_I2C1), I2CPINDEF(PB6, GPIO_AF4_I2C1), I2CPINDEF(PB8, GPIO_AF4_I2C1), }, - .sdaPins = { I2CPINDEF(PB7, GPIO_AF4_I2C1), I2CPINDEF(PB9, GPIO_AF4_I2C1), }, + + // Some boards are overloading SWD pins with I2C1 for maximum pin utilization on 48-pin CE(U) packages. + // Be carefull when using SWD on these boards if I2C1 pins are defined by default. + + .sclPins = { I2CPINDEF(PA13, GPIO_AF4_I2C1), I2CPINDEF(PA15, GPIO_AF4_I2C1), I2CPINDEF(PB6, GPIO_AF4_I2C1), I2CPINDEF(PB8, GPIO_AF4_I2C1), }, + .sdaPins = { I2CPINDEF(PA14, GPIO_AF4_I2C1), I2CPINDEF(PB7, GPIO_AF4_I2C1), I2CPINDEF(PB9, GPIO_AF4_I2C1), }, .rcc = RCC_APB11(I2C1), .ev_irq = I2C1_EV_IRQn, .er_irq = I2C1_ER_IRQn, @@ -182,7 +186,11 @@ const i2cHardware_t i2cHardware[I2CDEV_COUNT] = { { .device = I2CDEV_4, .reg = I2C4, - .sclPins = { I2CPINDEF(PB6, GPIO_AF3_I2C4), I2CPINDEF(PC6, GPIO_AF8_I2C4), }, + + // Here, SWDIO(PA13) is overloaded with I2C4_SCL, too. + // See comment in the I2C1 section above. + + .sclPins = { I2CPINDEF(PA13, GPIO_AF3_I2C4), I2CPINDEF(PB6, GPIO_AF3_I2C4), I2CPINDEF(PC6, GPIO_AF8_I2C4), }, .sdaPins = { I2CPINDEF(PB7, GPIO_AF4_I2C4), I2CPINDEF(PC7, GPIO_AF8_I2C4), }, .rcc = RCC_APB12(I2C4), .ev_irq = I2C4_EV_IRQn,