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PICO: Initial SPI
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parent
e98f620687
commit
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5 changed files with 197 additions and 12 deletions
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@ -33,19 +33,114 @@
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#include "drivers/bus_spi_impl.h"
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#include "drivers/exti.h"
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#include "drivers/io.h"
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#include "drivers/io_def.h"
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#include "drivers/io_impl.h"
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#include "hardware/spi.h"
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#include "hardware/gpio.h"
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#include "hardware/clocks.h"
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#include "hardware/dma.h"
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#include "pg/bus_spi.h"
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#define SPI_SPEED_20MHZ 2000000
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const spiHardware_t spiHardware[] = {
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#ifdef RP2350B
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{
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.device = SPIDEV_0,
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.reg = SPI0,
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.sckPins = {
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{ DEFIO_TAG_E(P6) },
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{ DEFIO_TAG_E(P18) },
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{ DEFIO_TAG_E(P22) },
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},
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.misoPins = {
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{ DEFIO_TAG_E(P0) },
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{ DEFIO_TAG_E(P4) },
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{ DEFIO_TAG_E(P16) },
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{ DEFIO_TAG_E(P20) },
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},
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.mosiPins = {
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{ DEFIO_TAG_E(P3) },
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{ DEFIO_TAG_E(P7) },
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{ DEFIO_TAG_E(P19) },
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{ DEFIO_TAG_E(P23) },
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},
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},
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{
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.device = SPIDEV_1,
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.reg = SPI1,
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.sckPins = {
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{ DEFIO_TAG_E(P10) },
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{ DEFIO_TAG_E(P14) },
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},
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.misoPins = {
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{ DEFIO_TAG_E(P12) },
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{ DEFIO_TAG_E(P28) },
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},
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.mosiPins = {
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{ DEFIO_TAG_E(P11) },
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{ DEFIO_TAG_E(P15) },
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},
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},
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#endif
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};
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void spiPinConfigure(const struct spiPinConfig_s *pConfig)
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{
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UNUSED(pConfig);
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for (size_t hwindex = 0 ; hwindex < ARRAYLEN(spiHardware) ; hwindex++) {
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const spiHardware_t *hw = &spiHardware[hwindex];
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if (!hw->reg) {
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continue;
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}
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SPIDevice device = hw->device;
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spiDevice_t *pDev = &spiDevice[device];
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for (int pindex = 0 ; pindex < MAX_SPI_PIN_SEL ; pindex++) {
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if (pConfig[device].ioTagSck == hw->sckPins[pindex].pin) {
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pDev->sck = hw->sckPins[pindex].pin;
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}
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if (pConfig[device].ioTagMiso == hw->misoPins[pindex].pin) {
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pDev->miso = hw->misoPins[pindex].pin;
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}
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if (pConfig[device].ioTagMosi == hw->mosiPins[pindex].pin) {
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pDev->mosi = hw->mosiPins[pindex].pin;
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}
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}
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if (pDev->sck && pDev->miso && pDev->mosi) {
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pDev->dev = hw->reg;
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pDev->leadingEdge = false;
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}
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}
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}
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static spi_inst_t *getSpiInstanceByDevice(SPI0_Type *spi)
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{
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if (spi == SPI0) {
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return spi0;
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} else if (spi == SPI1) {
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return spi1;
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}
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return NULL;
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}
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void spiInitDevice(SPIDevice device)
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{
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//TODO: implement
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UNUSED(device);
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const spiDevice_t *spi = &spiDevice[device];
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if (!spi->dev) {
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return;
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}
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spi_init(getSpiInstanceByDevice(spi->dev), SPI_SPEED_20MHZ);
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gpio_set_function(IO_PINBYTAG(spi->miso), GPIO_FUNC_SPI);
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gpio_set_function(IO_PINBYTAG(spi->mosi), GPIO_FUNC_SPI);
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gpio_set_function(IO_PINBYTAG(spi->sck), GPIO_FUNC_SPI);
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}
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void spiInternalResetDescriptors(busDevice_t *bus)
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@ -62,15 +157,39 @@ void spiInternalResetStream(dmaChannelDescriptor_t *descriptor)
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void spiInternalInitStream(const extDevice_t *dev, bool preInit)
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{
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//TODO: implement
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UNUSED(dev);
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UNUSED(preInit);
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int dma_tx = dma_claim_unused_channel(true);
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int dma_rx = dma_claim_unused_channel(true);
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dev->bus->dmaTx->channel = dma_tx;
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dev->bus->dmaRx->channel = dma_rx;
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dev->bus->dmaTx->irqHandlerCallback = NULL;
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dev->bus->dmaRx->irqHandlerCallback = spiInternalResetStream;
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const spiDevice_t *spi = &spiDevice[spiDeviceByInstance(dev->bus->busType_u.spi.instance)];
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dma_channel_config config = dma_channel_get_default_config(dma_tx);
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channel_config_set_transfer_data_size(&config, DMA_SIZE_8);
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channel_config_set_dreq(&config, spi_get_dreq(spi, true));
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dma_channel_configure(dma_tx, &config, &spi_get_hw(spi)->dr, dev->txBuf, 0, false);
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config = dma_channel_get_default_config(dma_rx);
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channel_config_set_transfer_data_size(&config, DMA_SIZE_8);
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channel_config_set_dreq(&config, spi_get_dreq(spi, false));
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dma_channel_configure(dma_rx, &config, dev->rxBuf, &spi_get_hw(spi)->dr, 0, false);
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dev->
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}
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void spiInternalStartDMA(const extDevice_t *dev)
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{
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//TODO: implement
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UNUSED(dev);
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const spiDevice_t *spi = &spiDevice[spiDeviceByInstance(dev->bus->busType_u.spi.instance)];
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dma_channel_set_trans_count(dev->bus->dmaTx, dev->bus->curSegment->len + 1, false);
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dma_channel_set_trans_count(dev->bus->dmaRx, dev->bus->curSegment->len + 1, false);
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dma_channel_start(dev->bus->dmaTx);
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dma_channel_start(dev->bus->dmaRx);
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}
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void spiInternalStopDMA (const extDevice_t *dev)
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@ -88,7 +207,13 @@ void spiSequenceStart(const extDevice_t *dev)
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uint16_t spiCalculateDivider(uint32_t freq)
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{
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UNUSED(freq);
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return 0;
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/*
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Divider is probably not needed for the PICO as the baud rate on the
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SPI bus can be set directly.
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In anycase max SPI clock is half the system clock frequency.
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Therefore the minimum divider is 2.
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*/
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return MAX(2, (((clock_get_hz(clk_sys) + (freq / 2)) / freq) + 1) & ~1);
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}
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#endif
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36
src/platform/PICO/dma_pico.c
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36
src/platform/PICO/dma_pico.c
Normal file
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@ -0,0 +1,36 @@
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/*
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* This file is part of Betaflight.
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*
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* Betaflight is free software. You can redistribute this software
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* and/or modify this software under the terms of the GNU General
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* Public License as published by the Free Software Foundation,
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* either version 3 of the License, or (at your option) any later
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* version.
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*
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* Betaflight is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this software.
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*
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include "platform.h"
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#include "drivers/dma.h"
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#include "dma_pico.h"
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dmaChannelDescriptor_t dmaDescriptors[DMA_HANDLER_END-1] = {
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};
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void dmaSetHandler(dmaIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam)
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{
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}
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24
src/platform/PICO/dma_pico.h
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24
src/platform/PICO/dma_pico.h
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typedef enum {
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DMA_NONE = 0,
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DMA_CH1_HANDLER = 1,
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DMA_CH2_HANDLER,
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DMA_CH3_HANDLER,
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DMA_CH4_HANDLER,
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DMA_CH5_HANDLER,
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DMA_CH6_HANDLER,
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DMA_CH7_HANDLER,
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DMA_CH8_HANDLER,
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DMA_CH9_HANDLER,
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DMA_CH10_HANDLER,
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DMA_CH11_HANDLER,
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DMA_CH12_HANDLER,
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#ifdef RP2350
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DMA_CH13_HANDLER,
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DMA_CH14_HANDLER,
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DMA_CH15_HANDLER,
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DMA_CH16_HANDLER,
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#endif
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DMA_HANDLER_END
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} dmaIdentifier_e;
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@ -101,3 +101,5 @@ extern uint32_t systemUniqueId[3];
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#define UART_TX_BUFFER_ATTRIBUTE
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#define UART_RX_BUFFER_ATTRIBUTE
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#define MAX_SPI_PIN_SEL 4
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@ -224,5 +224,3 @@ SPARE3 P47
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#define UARTHARDWARE_MAX_PINS 4
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#define UART_TRAIT_AF_PORT 1
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#define MAX_SPI_PIN_SEL 4
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