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Allow custom H7 HSE freqs. Allow H7 HSI. Limit H723 speed to 520Mhz (#12291)
* Work * Removed deprecated unified cfg comments
This commit is contained in:
David O'Connor
GitHub
parent
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commit
c41b458e58
1 changed files with 32 additions and 50 deletions
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@ -1,3 +1,7 @@
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// This module contains initialization code specific to STM32H7 MCUs.
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// It configures the RCC peripheral (system clocks) including scalars, and
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// enables RCC clocks for peripherals.
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/**
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******************************************************************************
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* @file system_stm32h7xx.c
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@ -73,19 +77,23 @@
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#include "drivers/system.h"
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#define HSI_FREQ ((uint32_t)64000000) // Frequency of HSI is 64Mhz on all H7 variants.
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// If `HSE_VALUE` isn't specified, use HSI. This allows HSI to be selected as the PLL source
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// later in this file, and adjusts PLL scalers to use the HSI's frequency as the timing source.
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#define PLL_SRC RCC_PLLSOURCE_HSI
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#define PLL_SRC_FREQ HSI_FREQ
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#else
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#define PLL_SRC RCC_PLLSOURCE_HSE
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#define PLL_SRC_FREQ HSE_VALUE
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#endif
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#if !defined (CSI_VALUE)
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#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* CSI_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @}
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*/
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@ -215,8 +223,9 @@ typedef struct pllConfig_s {
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pllConfig_t pll1ConfigRevY = {
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.clockMhz = 400,
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.m = 4,
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.n = 400,
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.n = 800000000 / PLL_SRC_FREQ * 4, // Holds DIVN's output to DIVP at 800Mhz.
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.p = 2,
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// Dividing PLLQ here by 8 keeps PLLQ1, used for SPI, below 200Mhz, required per the spec.
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.q = 8,
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.r = 5,
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.vos = PWR_REGULATOR_VOLTAGE_SCALE1,
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@ -227,8 +236,9 @@ pllConfig_t pll1ConfigRevY = {
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pllConfig_t pll1ConfigRevV = {
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.clockMhz = 480,
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.m = 4,
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.n = 480,
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.n = 960000000 / PLL_SRC_FREQ * 4, // Holds DIVN's output to DIVP at 960Mhz.
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.p = 2,
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// Dividing PLLQ here by 8 keeps PLLQ1, used for SPI, below 200Mhz, required per the spec.
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.q = 8,
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.r = 5,
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.vos = PWR_REGULATOR_VOLTAGE_SCALE0,
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@ -265,8 +275,9 @@ pllConfig_t pll1ConfigRevV = {
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pllConfig_t pll1Config7A3 = {
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.clockMhz = 280,
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.m = 4,
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.n = 280,
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.n = 560000000 / PLL_SRC_FREQ * 4, // Holds DIVN's output to DIVP at 560Mhz.
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.p = 2,
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// Dividing PLLQ here by 8 keeps PLLQ1, used for SPI, below 200Mhz, required per the spec.
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.q = 8,
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.r = 5,
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.vos = PWR_REGULATOR_VOLTAGE_SCALE0,
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@ -284,30 +295,7 @@ pllConfig_t pll1Config7A3 = {
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// Source for CRS input
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#define MCU_RCC_CRS_SYNC_SOURCE RCC_CRS_SYNC_SOURCE_USB1
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#elif defined(STM32H723xx) || defined(STM32H725xx)
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// Nominal max 550MHz
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pllConfig_t pll1Config72x = {
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.clockMhz = 550,
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.m = 4,
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.n = 275,
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.p = 1,
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.q = 2,
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.r = 2,
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.vos = PWR_REGULATOR_VOLTAGE_SCALE0,
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.vciRange = RCC_PLL1VCIRANGE_1,
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};
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#define MCU_HCLK_DIVIDER RCC_HCLK_DIV2
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// RM0468 (Rev.2) Table 16.
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// 550MHz (AXI Interface clock) at VOS0 is 3WS
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#define MCU_FLASH_LATENCY FLASH_LATENCY_3
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#define MCU_RCC_CRS_SYNC_SOURCE RCC_CRS_SYNC_SOURCE_USB1
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#elif defined(STM32H730xx)
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#elif defined(STM32H723xx) || defined(STM32H725xx) || defined(STM32H730xx)
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// Nominal max 550MHz, but >520Mhz requires ECC to be disabled, CPUFREQ_BOOST set in option bytes and prevents OCTOSPI clock from running at the correct clock speed.
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// 4.9.24 FLASH option status register 2 (FLASH_OPTSR2_CUR)
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@ -315,11 +303,12 @@ pllConfig_t pll1Config72x = {
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// ...
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// So use 520Mhz so that OCTOSPI clk can be 200Mhz with OCTOPSI prescaler 2 via PLL2R or 130Mhz with OCTOPSI prescaler 1 via PLL1Q
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pllConfig_t pll1Config73x = {
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pllConfig_t pll1Config72x73x = {
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.clockMhz = 520,
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.m = 2,
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.n = 130,
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.m = 4,
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.n = 520000000 / PLL_SRC_FREQ * 4, // Holds DIVN's output to DIVP at 520Mhz.
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.p = 1,
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// Dividing PLLQ here by 4 keeps PLLQ1, used for SPI, below 200Mhz, required per the spec.
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.q = 4,
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.r = 2,
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.vos = PWR_REGULATOR_VOLTAGE_SCALE0,
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@ -365,10 +354,8 @@ static void SystemClockHSE_Config(void)
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pll1Config = (HAL_GetREVID() == REV_ID_V) ? &pll1ConfigRevV : &pll1ConfigRevY;
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#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
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pll1Config = &pll1Config7A3;
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#elif defined(STM32H723xx) || defined(STM32H725xx)
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pll1Config = &pll1Config72x;
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#elif defined(STM32H730xx)
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pll1Config = &pll1Config73x;
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#elif defined(STM32H723xx) || defined(STM32H725xx) || defined(STM32H730xx)
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pll1Config = &pll1Config72x73x;
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#else
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#error Unknown MCU type
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#endif
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@ -407,7 +394,7 @@ static void SystemClockHSE_Config(void)
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RCC_OscInitStruct.HSEState = RCC_HSE_ON; // Even Nucleo-H473ZI and Nucleo-H7A3ZI work without RCC_HSE_BYPASS
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLSource = PLL_SRC;
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RCC_OscInitStruct.PLL.PLLM = pll1Config->m;
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RCC_OscInitStruct.PLL.PLLN = pll1Config->n;
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RCC_OscInitStruct.PLL.PLLP = pll1Config->p;
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@ -630,13 +617,9 @@ void SystemClock_Config(void)
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RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC;
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# if (HSE_VALUE != 8000000)
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# error Unsupported external oscillator speed. The calculations below are based on 8Mhz resonators
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// if you are seeing this, then calculate the PLL2 settings for your resonator and add support as required.
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# else
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# if defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H723xx) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H725xx)
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RCC_PeriphClkInit.PLL2.PLL2M = 5;
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RCC_PeriphClkInit.PLL2.PLL2N = 500; // 8Mhz (Oscillator Frequency) / 5 (PLL2M) = 1.6 * 500 (PLL2N) = 800Mhz.
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RCC_PeriphClkInit.PLL2.PLL2N = 800000000 / PLL_SRC_FREQ * 5; // Oscillator Frequency / 5 (PLL2M) = 1.6 * this value (PLL2N) = 800Mhz.
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RCC_PeriphClkInit.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; // Wide VCO range:192 to 836 MHz
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RCC_PeriphClkInit.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_0; // PLL2 input between 1 and 2Mhz (1.6)
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RCC_PeriphClkInit.PLL2.PLL2FRACN = 0;
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@ -646,7 +629,7 @@ void SystemClock_Config(void)
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RCC_PeriphClkInit.PLL2.PLL2R = 4; // 800Mhz / 4 = 200Mhz // HAL LIBS REQUIRE 200MHZ SDMMC CLOCK, see HAL_SD_ConfigWideBusOperation, SDMMC_HSpeed_CLK_DIV, SDMMC_NSpeed_CLK_DIV
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# elif defined(STM32H730xx)
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RCC_PeriphClkInit.PLL2.PLL2M = 8;
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RCC_PeriphClkInit.PLL2.PLL2N = 400; // 8Mhz (Oscillator Frequency) / 8 (PLL2M) = 1.0 * 400 (PLL2N) = 400Mhz.
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RCC_PeriphClkInit.PLL2.PLL2N = 400000000 / PLL_SRC_FREQ * 8; // HSE frequency / 8 (PLL2M) * 400 (PLL2N) = 400Mhz.
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RCC_PeriphClkInit.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM; // Medium VCO range:150 to 420 MHz
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RCC_PeriphClkInit.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_0; // PLL2 input between 1 and 2Mhz (1.0)
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RCC_PeriphClkInit.PLL2.PLL2FRACN = 0;
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@ -659,7 +642,6 @@ void SystemClock_Config(void)
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# endif
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RCC_PeriphClkInit.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL2;
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HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit);
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# endif
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# endif
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RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
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