mirror of
https://github.com/betaflight/betaflight.git
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Normalize all the line endings
This commit is contained in:
Dominic Clifton
parent
4237370b60
commit
d60183d91d
396 changed files with 158300 additions and 158300 deletions
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@ -1,402 +1,402 @@
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/*
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* This file is part of Cleanflight.
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*
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* Cleanflight is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Cleanflight is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <platform.h>
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#include "build_config.h"
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#include "gpio.h"
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#include "system.h"
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#include "bus_i2c.h"
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#ifndef SOFT_I2C
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// I2C2
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// SCL PB10
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// SDA PB11
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// I2C1
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// SCL PB6
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// SDA PB7
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static void i2c_er_handler(void);
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static void i2c_ev_handler(void);
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static void i2cUnstick(void);
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typedef struct i2cDevice_t {
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I2C_TypeDef *dev;
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GPIO_TypeDef *gpio;
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uint16_t scl;
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uint16_t sda;
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uint8_t ev_irq;
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uint8_t er_irq;
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uint32_t peripheral;
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} i2cDevice_t;
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static const i2cDevice_t i2cHardwareMap[] = {
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{ I2C1, GPIOB, Pin_6, Pin_7, I2C1_EV_IRQn, I2C1_ER_IRQn, RCC_APB1Periph_I2C1 },
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{ I2C2, GPIOB, Pin_10, Pin_11, I2C2_EV_IRQn, I2C2_ER_IRQn, RCC_APB1Periph_I2C2 },
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};
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// Copy of peripheral address for IRQ routines
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static I2C_TypeDef *I2Cx;
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// Copy of device index for reinit, etc purposes
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static I2CDevice I2Cx_index;
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void I2C1_ER_IRQHandler(void)
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{
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i2c_er_handler();
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}
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void I2C1_EV_IRQHandler(void)
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{
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i2c_ev_handler();
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}
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void I2C2_ER_IRQHandler(void)
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{
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i2c_er_handler();
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}
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void I2C2_EV_IRQHandler(void)
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{
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i2c_ev_handler();
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}
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#define I2C_DEFAULT_TIMEOUT 30000
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static volatile uint16_t i2cErrorCount = 0;
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static volatile bool error = false;
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static volatile bool busy;
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static volatile uint8_t addr;
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static volatile uint8_t reg;
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static volatile uint8_t bytes;
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static volatile uint8_t writing;
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static volatile uint8_t reading;
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static volatile uint8_t* write_p;
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static volatile uint8_t* read_p;
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static bool i2cHandleHardwareFailure(void)
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{
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i2cErrorCount++;
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// reinit peripheral + clock out garbage
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i2cInit(I2Cx_index);
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return false;
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}
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bool i2cWriteBuffer(uint8_t addr_, uint8_t reg_, uint8_t len_, uint8_t *data)
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{
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uint32_t timeout = I2C_DEFAULT_TIMEOUT;
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addr = addr_ << 1;
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reg = reg_;
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writing = 1;
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reading = 0;
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write_p = data;
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read_p = data;
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bytes = len_;
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busy = 1;
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error = false;
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if (!(I2Cx->CR2 & I2C_IT_EVT)) { // if we are restarting the driver
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if (!(I2Cx->CR1 & 0x0100)) { // ensure sending a start
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while (I2Cx->CR1 & 0x0200 && --timeout > 0) { ; } // wait for any stop to finish sending
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if (timeout == 0) {
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return i2cHandleHardwareFailure();
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}
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I2C_GenerateSTART(I2Cx, ENABLE); // send the start for the new job
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}
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I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_ERR, ENABLE); // allow the interrupts to fire off again
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}
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timeout = I2C_DEFAULT_TIMEOUT;
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while (busy && --timeout > 0) { ; }
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if (timeout == 0) {
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return i2cHandleHardwareFailure();
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}
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return !error;
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}
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bool i2cWrite(uint8_t addr_, uint8_t reg_, uint8_t data)
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{
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return i2cWriteBuffer(addr_, reg_, 1, &data);
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}
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bool i2cRead(uint8_t addr_, uint8_t reg_, uint8_t len, uint8_t* buf)
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{
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uint32_t timeout = I2C_DEFAULT_TIMEOUT;
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addr = addr_ << 1;
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reg = reg_;
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writing = 0;
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reading = 1;
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read_p = buf;
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write_p = buf;
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bytes = len;
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busy = 1;
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error = false;
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if (!(I2Cx->CR2 & I2C_IT_EVT)) { // if we are restarting the driver
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if (!(I2Cx->CR1 & 0x0100)) { // ensure sending a start
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while (I2Cx->CR1 & 0x0200 && --timeout > 0) { ; } // wait for any stop to finish sending
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if (timeout == 0)
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return i2cHandleHardwareFailure();
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I2C_GenerateSTART(I2Cx, ENABLE); // send the start for the new job
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}
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I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_ERR, ENABLE); // allow the interrupts to fire off again
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}
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timeout = I2C_DEFAULT_TIMEOUT;
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while (busy && --timeout > 0) { ; }
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if (timeout == 0)
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return i2cHandleHardwareFailure();
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return !error;
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}
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static void i2c_er_handler(void)
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{
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// Read the I2Cx status register
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volatile uint32_t SR1Register = I2Cx->SR1;
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if (SR1Register & 0x0F00) { // an error
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error = true;
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}
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// If AF, BERR or ARLO, abandon the current job and commence new if there are jobs
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if (SR1Register & 0x0700) {
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(void)I2Cx->SR2; // read second status register to clear ADDR if it is set (note that BTF will not be set after a NACK)
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I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable the RXNE/TXE interrupt - prevent the ISR tailchaining onto the ER (hopefully)
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if (!(SR1Register & 0x0200) && !(I2Cx->CR1 & 0x0200)) { // if we dont have an ARLO error, ensure sending of a stop
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if (I2Cx->CR1 & 0x0100) { // We are currently trying to send a start, this is very bad as start, stop will hang the peripheral
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while (I2Cx->CR1 & 0x0100) { ; } // wait for any start to finish sending
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I2C_GenerateSTOP(I2Cx, ENABLE); // send stop to finalise bus transaction
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while (I2Cx->CR1 & 0x0200) { ; } // wait for stop to finish sending
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i2cInit(I2Cx_index); // reset and configure the hardware
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} else {
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I2C_GenerateSTOP(I2Cx, ENABLE); // stop to free up the bus
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I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_ERR, DISABLE); // Disable EVT and ERR interrupts while bus inactive
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}
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}
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}
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I2Cx->SR1 &= ~0x0F00; // reset all the error bits to clear the interrupt
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busy = 0;
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}
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void i2c_ev_handler(void)
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{
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static uint8_t subaddress_sent, final_stop; // flag to indicate if subaddess sent, flag to indicate final bus condition
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static int8_t index; // index is signed -1 == send the subaddress
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uint8_t SReg_1 = I2Cx->SR1; // read the status register here
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if (SReg_1 & 0x0001) { // we just sent a start - EV5 in ref manual
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I2Cx->CR1 &= ~0x0800; // reset the POS bit so ACK/NACK applied to the current byte
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I2C_AcknowledgeConfig(I2Cx, ENABLE); // make sure ACK is on
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index = 0; // reset the index
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if (reading && (subaddress_sent || 0xFF == reg)) { // we have sent the subaddr
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subaddress_sent = 1; // make sure this is set in case of no subaddress, so following code runs correctly
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if (bytes == 2)
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I2Cx->CR1 |= 0x0800; // set the POS bit so NACK applied to the final byte in the two byte read
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I2C_Send7bitAddress(I2Cx, addr, I2C_Direction_Receiver); // send the address and set hardware mode
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} else { // direction is Tx, or we havent sent the sub and rep start
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I2C_Send7bitAddress(I2Cx, addr, I2C_Direction_Transmitter); // send the address and set hardware mode
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if (reg != 0xFF) // 0xFF as subaddress means it will be ignored, in Tx or Rx mode
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index = -1; // send a subaddress
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}
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} else if (SReg_1 & 0x0002) { // we just sent the address - EV6 in ref manual
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// Read SR1,2 to clear ADDR
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__DMB(); // memory fence to control hardware
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if (bytes == 1 && reading && subaddress_sent) { // we are receiving 1 byte - EV6_3
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I2C_AcknowledgeConfig(I2Cx, DISABLE); // turn off ACK
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__DMB();
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(void)I2Cx->SR2; // clear ADDR after ACK is turned off
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I2C_GenerateSTOP(I2Cx, ENABLE); // program the stop
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final_stop = 1;
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I2C_ITConfig(I2Cx, I2C_IT_BUF, ENABLE); // allow us to have an EV7
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} else { // EV6 and EV6_1
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(void)I2Cx->SR2; // clear the ADDR here
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__DMB();
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if (bytes == 2 && reading && subaddress_sent) { // rx 2 bytes - EV6_1
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I2C_AcknowledgeConfig(I2Cx, DISABLE); // turn off ACK
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I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable TXE to allow the buffer to fill
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} else if (bytes == 3 && reading && subaddress_sent) // rx 3 bytes
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I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // make sure RXNE disabled so we get a BTF in two bytes time
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else // receiving greater than three bytes, sending subaddress, or transmitting
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I2C_ITConfig(I2Cx, I2C_IT_BUF, ENABLE);
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}
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} else if (SReg_1 & 0x004) { // Byte transfer finished - EV7_2, EV7_3 or EV8_2
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final_stop = 1;
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if (reading && subaddress_sent) { // EV7_2, EV7_3
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if (bytes > 2) { // EV7_2
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I2C_AcknowledgeConfig(I2Cx, DISABLE); // turn off ACK
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read_p[index++] = (uint8_t)I2Cx->DR; // read data N-2
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I2C_GenerateSTOP(I2Cx, ENABLE); // program the Stop
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final_stop = 1; // required to fix hardware
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read_p[index++] = (uint8_t)I2Cx->DR; // read data N - 1
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I2C_ITConfig(I2Cx, I2C_IT_BUF, ENABLE); // enable TXE to allow the final EV7
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} else { // EV7_3
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if (final_stop)
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I2C_GenerateSTOP(I2Cx, ENABLE); // program the Stop
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else
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I2C_GenerateSTART(I2Cx, ENABLE); // program a rep start
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read_p[index++] = (uint8_t)I2Cx->DR; // read data N - 1
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read_p[index++] = (uint8_t)I2Cx->DR; // read data N
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index++; // to show job completed
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}
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} else { // EV8_2, which may be due to a subaddress sent or a write completion
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if (subaddress_sent || (writing)) {
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if (final_stop)
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I2C_GenerateSTOP(I2Cx, ENABLE); // program the Stop
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else
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I2C_GenerateSTART(I2Cx, ENABLE); // program a rep start
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index++; // to show that the job is complete
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} else { // We need to send a subaddress
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I2C_GenerateSTART(I2Cx, ENABLE); // program the repeated Start
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subaddress_sent = 1; // this is set back to zero upon completion of the current task
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}
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}
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// we must wait for the start to clear, otherwise we get constant BTF
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while (I2Cx->CR1 & 0x0100) { ; }
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} else if (SReg_1 & 0x0040) { // Byte received - EV7
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read_p[index++] = (uint8_t)I2Cx->DR;
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if (bytes == (index + 3))
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I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable TXE to allow the buffer to flush so we can get an EV7_2
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if (bytes == index) // We have completed a final EV7
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index++; // to show job is complete
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} else if (SReg_1 & 0x0080) { // Byte transmitted EV8 / EV8_1
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if (index != -1) { // we dont have a subaddress to send
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I2Cx->DR = write_p[index++];
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if (bytes == index) // we have sent all the data
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I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable TXE to allow the buffer to flush
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} else {
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index++;
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I2Cx->DR = reg; // send the subaddress
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if (reading || !bytes) // if receiving or sending 0 bytes, flush now
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I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable TXE to allow the buffer to flush
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}
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}
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if (index == bytes + 1) { // we have completed the current job
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subaddress_sent = 0; // reset this here
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if (final_stop) // If there is a final stop and no more jobs, bus is inactive, disable interrupts to prevent BTF
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I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_ERR, DISABLE); // Disable EVT and ERR interrupts while bus inactive
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busy = 0;
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}
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}
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void i2cInit(I2CDevice index)
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{
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NVIC_InitTypeDef nvic;
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I2C_InitTypeDef i2c;
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if (index > I2CDEV_MAX)
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index = I2CDEV_MAX;
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// Turn on peripheral clock, save device and index
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I2Cx = i2cHardwareMap[index].dev;
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I2Cx_index = index;
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RCC_APB1PeriphClockCmd(i2cHardwareMap[index].peripheral, ENABLE);
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// clock out stuff to make sure slaves arent stuck
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// This will also configure GPIO as AF_OD at the end
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i2cUnstick();
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// Init I2C peripheral
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I2C_DeInit(I2Cx);
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I2C_StructInit(&i2c);
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I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_ERR, DISABLE); // Enable EVT and ERR interrupts - they are enabled by the first request
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i2c.I2C_Mode = I2C_Mode_I2C;
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i2c.I2C_DutyCycle = I2C_DutyCycle_2;
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i2c.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
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i2c.I2C_ClockSpeed = 400000;
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I2C_Cmd(I2Cx, ENABLE);
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I2C_Init(I2Cx, &i2c);
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// I2C ER Interrupt
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nvic.NVIC_IRQChannel = i2cHardwareMap[index].er_irq;
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nvic.NVIC_IRQChannelPreemptionPriority = 0;
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nvic.NVIC_IRQChannelSubPriority = 0;
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nvic.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&nvic);
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// I2C EV Interrupt
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nvic.NVIC_IRQChannel = i2cHardwareMap[index].ev_irq;
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nvic.NVIC_IRQChannelPreemptionPriority = 0;
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NVIC_Init(&nvic);
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}
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uint16_t i2cGetErrorCounter(void)
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{
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return i2cErrorCount;
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}
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static void i2cUnstick(void)
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{
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GPIO_TypeDef *gpio;
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gpio_config_t cfg;
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uint16_t scl, sda;
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int i;
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// prepare pins
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gpio = i2cHardwareMap[I2Cx_index].gpio;
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scl = i2cHardwareMap[I2Cx_index].scl;
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sda = i2cHardwareMap[I2Cx_index].sda;
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digitalHi(gpio, scl | sda);
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cfg.pin = scl | sda;
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cfg.speed = Speed_2MHz;
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cfg.mode = Mode_Out_OD;
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gpioInit(gpio, &cfg);
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for (i = 0; i < 8; i++) {
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// Wait for any clock stretching to finish
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while (!digitalIn(gpio, scl))
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delayMicroseconds(10);
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// Pull low
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digitalLo(gpio, scl); // Set bus low
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delayMicroseconds(10);
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// Release high again
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digitalHi(gpio, scl); // Set bus high
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delayMicroseconds(10);
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}
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// Generate a start then stop condition
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// SCL PB10
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// SDA PB11
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digitalLo(gpio, sda); // Set bus data low
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delayMicroseconds(10);
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digitalLo(gpio, scl); // Set bus scl low
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delayMicroseconds(10);
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digitalHi(gpio, scl); // Set bus scl high
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delayMicroseconds(10);
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digitalHi(gpio, sda); // Set bus sda high
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// Init pins
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cfg.pin = scl | sda;
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cfg.speed = Speed_2MHz;
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cfg.mode = Mode_AF_OD;
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gpioInit(gpio, &cfg);
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}
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#endif
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/*
|
||||
* This file is part of Cleanflight.
|
||||
*
|
||||
* Cleanflight is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* Cleanflight is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <platform.h>
|
||||
|
||||
#include "build_config.h"
|
||||
|
||||
#include "gpio.h"
|
||||
#include "system.h"
|
||||
|
||||
#include "bus_i2c.h"
|
||||
|
||||
#ifndef SOFT_I2C
|
||||
|
||||
// I2C2
|
||||
// SCL PB10
|
||||
// SDA PB11
|
||||
// I2C1
|
||||
// SCL PB6
|
||||
// SDA PB7
|
||||
|
||||
static void i2c_er_handler(void);
|
||||
static void i2c_ev_handler(void);
|
||||
static void i2cUnstick(void);
|
||||
|
||||
typedef struct i2cDevice_t {
|
||||
I2C_TypeDef *dev;
|
||||
GPIO_TypeDef *gpio;
|
||||
uint16_t scl;
|
||||
uint16_t sda;
|
||||
uint8_t ev_irq;
|
||||
uint8_t er_irq;
|
||||
uint32_t peripheral;
|
||||
} i2cDevice_t;
|
||||
|
||||
static const i2cDevice_t i2cHardwareMap[] = {
|
||||
{ I2C1, GPIOB, Pin_6, Pin_7, I2C1_EV_IRQn, I2C1_ER_IRQn, RCC_APB1Periph_I2C1 },
|
||||
{ I2C2, GPIOB, Pin_10, Pin_11, I2C2_EV_IRQn, I2C2_ER_IRQn, RCC_APB1Periph_I2C2 },
|
||||
};
|
||||
|
||||
// Copy of peripheral address for IRQ routines
|
||||
static I2C_TypeDef *I2Cx;
|
||||
// Copy of device index for reinit, etc purposes
|
||||
static I2CDevice I2Cx_index;
|
||||
|
||||
void I2C1_ER_IRQHandler(void)
|
||||
{
|
||||
i2c_er_handler();
|
||||
}
|
||||
|
||||
void I2C1_EV_IRQHandler(void)
|
||||
{
|
||||
i2c_ev_handler();
|
||||
}
|
||||
|
||||
void I2C2_ER_IRQHandler(void)
|
||||
{
|
||||
i2c_er_handler();
|
||||
}
|
||||
|
||||
void I2C2_EV_IRQHandler(void)
|
||||
{
|
||||
i2c_ev_handler();
|
||||
}
|
||||
|
||||
#define I2C_DEFAULT_TIMEOUT 30000
|
||||
static volatile uint16_t i2cErrorCount = 0;
|
||||
|
||||
static volatile bool error = false;
|
||||
static volatile bool busy;
|
||||
|
||||
static volatile uint8_t addr;
|
||||
static volatile uint8_t reg;
|
||||
static volatile uint8_t bytes;
|
||||
static volatile uint8_t writing;
|
||||
static volatile uint8_t reading;
|
||||
static volatile uint8_t* write_p;
|
||||
static volatile uint8_t* read_p;
|
||||
|
||||
static bool i2cHandleHardwareFailure(void)
|
||||
{
|
||||
i2cErrorCount++;
|
||||
// reinit peripheral + clock out garbage
|
||||
i2cInit(I2Cx_index);
|
||||
return false;
|
||||
}
|
||||
|
||||
bool i2cWriteBuffer(uint8_t addr_, uint8_t reg_, uint8_t len_, uint8_t *data)
|
||||
{
|
||||
uint32_t timeout = I2C_DEFAULT_TIMEOUT;
|
||||
|
||||
addr = addr_ << 1;
|
||||
reg = reg_;
|
||||
writing = 1;
|
||||
reading = 0;
|
||||
write_p = data;
|
||||
read_p = data;
|
||||
bytes = len_;
|
||||
busy = 1;
|
||||
error = false;
|
||||
|
||||
if (!(I2Cx->CR2 & I2C_IT_EVT)) { // if we are restarting the driver
|
||||
if (!(I2Cx->CR1 & 0x0100)) { // ensure sending a start
|
||||
while (I2Cx->CR1 & 0x0200 && --timeout > 0) { ; } // wait for any stop to finish sending
|
||||
if (timeout == 0) {
|
||||
return i2cHandleHardwareFailure();
|
||||
}
|
||||
I2C_GenerateSTART(I2Cx, ENABLE); // send the start for the new job
|
||||
}
|
||||
I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_ERR, ENABLE); // allow the interrupts to fire off again
|
||||
}
|
||||
|
||||
timeout = I2C_DEFAULT_TIMEOUT;
|
||||
while (busy && --timeout > 0) { ; }
|
||||
if (timeout == 0) {
|
||||
return i2cHandleHardwareFailure();
|
||||
}
|
||||
|
||||
return !error;
|
||||
}
|
||||
|
||||
bool i2cWrite(uint8_t addr_, uint8_t reg_, uint8_t data)
|
||||
{
|
||||
return i2cWriteBuffer(addr_, reg_, 1, &data);
|
||||
}
|
||||
|
||||
bool i2cRead(uint8_t addr_, uint8_t reg_, uint8_t len, uint8_t* buf)
|
||||
{
|
||||
uint32_t timeout = I2C_DEFAULT_TIMEOUT;
|
||||
|
||||
addr = addr_ << 1;
|
||||
reg = reg_;
|
||||
writing = 0;
|
||||
reading = 1;
|
||||
read_p = buf;
|
||||
write_p = buf;
|
||||
bytes = len;
|
||||
busy = 1;
|
||||
error = false;
|
||||
|
||||
if (!(I2Cx->CR2 & I2C_IT_EVT)) { // if we are restarting the driver
|
||||
if (!(I2Cx->CR1 & 0x0100)) { // ensure sending a start
|
||||
while (I2Cx->CR1 & 0x0200 && --timeout > 0) { ; } // wait for any stop to finish sending
|
||||
if (timeout == 0)
|
||||
return i2cHandleHardwareFailure();
|
||||
I2C_GenerateSTART(I2Cx, ENABLE); // send the start for the new job
|
||||
}
|
||||
I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_ERR, ENABLE); // allow the interrupts to fire off again
|
||||
}
|
||||
|
||||
timeout = I2C_DEFAULT_TIMEOUT;
|
||||
while (busy && --timeout > 0) { ; }
|
||||
if (timeout == 0)
|
||||
return i2cHandleHardwareFailure();
|
||||
|
||||
return !error;
|
||||
}
|
||||
|
||||
static void i2c_er_handler(void)
|
||||
{
|
||||
// Read the I2Cx status register
|
||||
volatile uint32_t SR1Register = I2Cx->SR1;
|
||||
|
||||
if (SR1Register & 0x0F00) { // an error
|
||||
error = true;
|
||||
}
|
||||
|
||||
// If AF, BERR or ARLO, abandon the current job and commence new if there are jobs
|
||||
if (SR1Register & 0x0700) {
|
||||
(void)I2Cx->SR2; // read second status register to clear ADDR if it is set (note that BTF will not be set after a NACK)
|
||||
I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable the RXNE/TXE interrupt - prevent the ISR tailchaining onto the ER (hopefully)
|
||||
if (!(SR1Register & 0x0200) && !(I2Cx->CR1 & 0x0200)) { // if we dont have an ARLO error, ensure sending of a stop
|
||||
if (I2Cx->CR1 & 0x0100) { // We are currently trying to send a start, this is very bad as start, stop will hang the peripheral
|
||||
while (I2Cx->CR1 & 0x0100) { ; } // wait for any start to finish sending
|
||||
I2C_GenerateSTOP(I2Cx, ENABLE); // send stop to finalise bus transaction
|
||||
while (I2Cx->CR1 & 0x0200) { ; } // wait for stop to finish sending
|
||||
i2cInit(I2Cx_index); // reset and configure the hardware
|
||||
} else {
|
||||
I2C_GenerateSTOP(I2Cx, ENABLE); // stop to free up the bus
|
||||
I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_ERR, DISABLE); // Disable EVT and ERR interrupts while bus inactive
|
||||
}
|
||||
}
|
||||
}
|
||||
I2Cx->SR1 &= ~0x0F00; // reset all the error bits to clear the interrupt
|
||||
busy = 0;
|
||||
}
|
||||
|
||||
void i2c_ev_handler(void)
|
||||
{
|
||||
static uint8_t subaddress_sent, final_stop; // flag to indicate if subaddess sent, flag to indicate final bus condition
|
||||
static int8_t index; // index is signed -1 == send the subaddress
|
||||
uint8_t SReg_1 = I2Cx->SR1; // read the status register here
|
||||
|
||||
if (SReg_1 & 0x0001) { // we just sent a start - EV5 in ref manual
|
||||
I2Cx->CR1 &= ~0x0800; // reset the POS bit so ACK/NACK applied to the current byte
|
||||
I2C_AcknowledgeConfig(I2Cx, ENABLE); // make sure ACK is on
|
||||
index = 0; // reset the index
|
||||
if (reading && (subaddress_sent || 0xFF == reg)) { // we have sent the subaddr
|
||||
subaddress_sent = 1; // make sure this is set in case of no subaddress, so following code runs correctly
|
||||
if (bytes == 2)
|
||||
I2Cx->CR1 |= 0x0800; // set the POS bit so NACK applied to the final byte in the two byte read
|
||||
I2C_Send7bitAddress(I2Cx, addr, I2C_Direction_Receiver); // send the address and set hardware mode
|
||||
} else { // direction is Tx, or we havent sent the sub and rep start
|
||||
I2C_Send7bitAddress(I2Cx, addr, I2C_Direction_Transmitter); // send the address and set hardware mode
|
||||
if (reg != 0xFF) // 0xFF as subaddress means it will be ignored, in Tx or Rx mode
|
||||
index = -1; // send a subaddress
|
||||
}
|
||||
} else if (SReg_1 & 0x0002) { // we just sent the address - EV6 in ref manual
|
||||
// Read SR1,2 to clear ADDR
|
||||
__DMB(); // memory fence to control hardware
|
||||
if (bytes == 1 && reading && subaddress_sent) { // we are receiving 1 byte - EV6_3
|
||||
I2C_AcknowledgeConfig(I2Cx, DISABLE); // turn off ACK
|
||||
__DMB();
|
||||
(void)I2Cx->SR2; // clear ADDR after ACK is turned off
|
||||
I2C_GenerateSTOP(I2Cx, ENABLE); // program the stop
|
||||
final_stop = 1;
|
||||
I2C_ITConfig(I2Cx, I2C_IT_BUF, ENABLE); // allow us to have an EV7
|
||||
} else { // EV6 and EV6_1
|
||||
(void)I2Cx->SR2; // clear the ADDR here
|
||||
__DMB();
|
||||
if (bytes == 2 && reading && subaddress_sent) { // rx 2 bytes - EV6_1
|
||||
I2C_AcknowledgeConfig(I2Cx, DISABLE); // turn off ACK
|
||||
I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable TXE to allow the buffer to fill
|
||||
} else if (bytes == 3 && reading && subaddress_sent) // rx 3 bytes
|
||||
I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // make sure RXNE disabled so we get a BTF in two bytes time
|
||||
else // receiving greater than three bytes, sending subaddress, or transmitting
|
||||
I2C_ITConfig(I2Cx, I2C_IT_BUF, ENABLE);
|
||||
}
|
||||
} else if (SReg_1 & 0x004) { // Byte transfer finished - EV7_2, EV7_3 or EV8_2
|
||||
final_stop = 1;
|
||||
if (reading && subaddress_sent) { // EV7_2, EV7_3
|
||||
if (bytes > 2) { // EV7_2
|
||||
I2C_AcknowledgeConfig(I2Cx, DISABLE); // turn off ACK
|
||||
read_p[index++] = (uint8_t)I2Cx->DR; // read data N-2
|
||||
I2C_GenerateSTOP(I2Cx, ENABLE); // program the Stop
|
||||
final_stop = 1; // required to fix hardware
|
||||
read_p[index++] = (uint8_t)I2Cx->DR; // read data N - 1
|
||||
I2C_ITConfig(I2Cx, I2C_IT_BUF, ENABLE); // enable TXE to allow the final EV7
|
||||
} else { // EV7_3
|
||||
if (final_stop)
|
||||
I2C_GenerateSTOP(I2Cx, ENABLE); // program the Stop
|
||||
else
|
||||
I2C_GenerateSTART(I2Cx, ENABLE); // program a rep start
|
||||
read_p[index++] = (uint8_t)I2Cx->DR; // read data N - 1
|
||||
read_p[index++] = (uint8_t)I2Cx->DR; // read data N
|
||||
index++; // to show job completed
|
||||
}
|
||||
} else { // EV8_2, which may be due to a subaddress sent or a write completion
|
||||
if (subaddress_sent || (writing)) {
|
||||
if (final_stop)
|
||||
I2C_GenerateSTOP(I2Cx, ENABLE); // program the Stop
|
||||
else
|
||||
I2C_GenerateSTART(I2Cx, ENABLE); // program a rep start
|
||||
index++; // to show that the job is complete
|
||||
} else { // We need to send a subaddress
|
||||
I2C_GenerateSTART(I2Cx, ENABLE); // program the repeated Start
|
||||
subaddress_sent = 1; // this is set back to zero upon completion of the current task
|
||||
}
|
||||
}
|
||||
// we must wait for the start to clear, otherwise we get constant BTF
|
||||
while (I2Cx->CR1 & 0x0100) { ; }
|
||||
} else if (SReg_1 & 0x0040) { // Byte received - EV7
|
||||
read_p[index++] = (uint8_t)I2Cx->DR;
|
||||
if (bytes == (index + 3))
|
||||
I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable TXE to allow the buffer to flush so we can get an EV7_2
|
||||
if (bytes == index) // We have completed a final EV7
|
||||
index++; // to show job is complete
|
||||
} else if (SReg_1 & 0x0080) { // Byte transmitted EV8 / EV8_1
|
||||
if (index != -1) { // we dont have a subaddress to send
|
||||
I2Cx->DR = write_p[index++];
|
||||
if (bytes == index) // we have sent all the data
|
||||
I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable TXE to allow the buffer to flush
|
||||
} else {
|
||||
index++;
|
||||
I2Cx->DR = reg; // send the subaddress
|
||||
if (reading || !bytes) // if receiving or sending 0 bytes, flush now
|
||||
I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable TXE to allow the buffer to flush
|
||||
}
|
||||
}
|
||||
if (index == bytes + 1) { // we have completed the current job
|
||||
subaddress_sent = 0; // reset this here
|
||||
if (final_stop) // If there is a final stop and no more jobs, bus is inactive, disable interrupts to prevent BTF
|
||||
I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_ERR, DISABLE); // Disable EVT and ERR interrupts while bus inactive
|
||||
busy = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void i2cInit(I2CDevice index)
|
||||
{
|
||||
NVIC_InitTypeDef nvic;
|
||||
I2C_InitTypeDef i2c;
|
||||
|
||||
if (index > I2CDEV_MAX)
|
||||
index = I2CDEV_MAX;
|
||||
|
||||
// Turn on peripheral clock, save device and index
|
||||
I2Cx = i2cHardwareMap[index].dev;
|
||||
I2Cx_index = index;
|
||||
RCC_APB1PeriphClockCmd(i2cHardwareMap[index].peripheral, ENABLE);
|
||||
|
||||
// clock out stuff to make sure slaves arent stuck
|
||||
// This will also configure GPIO as AF_OD at the end
|
||||
i2cUnstick();
|
||||
|
||||
// Init I2C peripheral
|
||||
I2C_DeInit(I2Cx);
|
||||
I2C_StructInit(&i2c);
|
||||
|
||||
I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_ERR, DISABLE); // Enable EVT and ERR interrupts - they are enabled by the first request
|
||||
i2c.I2C_Mode = I2C_Mode_I2C;
|
||||
i2c.I2C_DutyCycle = I2C_DutyCycle_2;
|
||||
i2c.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
|
||||
i2c.I2C_ClockSpeed = 400000;
|
||||
I2C_Cmd(I2Cx, ENABLE);
|
||||
I2C_Init(I2Cx, &i2c);
|
||||
|
||||
// I2C ER Interrupt
|
||||
nvic.NVIC_IRQChannel = i2cHardwareMap[index].er_irq;
|
||||
nvic.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
nvic.NVIC_IRQChannelSubPriority = 0;
|
||||
nvic.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&nvic);
|
||||
|
||||
// I2C EV Interrupt
|
||||
nvic.NVIC_IRQChannel = i2cHardwareMap[index].ev_irq;
|
||||
nvic.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
NVIC_Init(&nvic);
|
||||
}
|
||||
|
||||
uint16_t i2cGetErrorCounter(void)
|
||||
{
|
||||
return i2cErrorCount;
|
||||
}
|
||||
|
||||
static void i2cUnstick(void)
|
||||
{
|
||||
GPIO_TypeDef *gpio;
|
||||
gpio_config_t cfg;
|
||||
uint16_t scl, sda;
|
||||
int i;
|
||||
|
||||
// prepare pins
|
||||
gpio = i2cHardwareMap[I2Cx_index].gpio;
|
||||
scl = i2cHardwareMap[I2Cx_index].scl;
|
||||
sda = i2cHardwareMap[I2Cx_index].sda;
|
||||
|
||||
digitalHi(gpio, scl | sda);
|
||||
|
||||
cfg.pin = scl | sda;
|
||||
cfg.speed = Speed_2MHz;
|
||||
cfg.mode = Mode_Out_OD;
|
||||
gpioInit(gpio, &cfg);
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
// Wait for any clock stretching to finish
|
||||
while (!digitalIn(gpio, scl))
|
||||
delayMicroseconds(10);
|
||||
|
||||
// Pull low
|
||||
digitalLo(gpio, scl); // Set bus low
|
||||
delayMicroseconds(10);
|
||||
// Release high again
|
||||
digitalHi(gpio, scl); // Set bus high
|
||||
delayMicroseconds(10);
|
||||
}
|
||||
|
||||
// Generate a start then stop condition
|
||||
// SCL PB10
|
||||
// SDA PB11
|
||||
digitalLo(gpio, sda); // Set bus data low
|
||||
delayMicroseconds(10);
|
||||
digitalLo(gpio, scl); // Set bus scl low
|
||||
delayMicroseconds(10);
|
||||
digitalHi(gpio, scl); // Set bus scl high
|
||||
delayMicroseconds(10);
|
||||
digitalHi(gpio, sda); // Set bus sda high
|
||||
|
||||
// Init pins
|
||||
cfg.pin = scl | sda;
|
||||
cfg.speed = Speed_2MHz;
|
||||
cfg.mode = Mode_AF_OD;
|
||||
gpioInit(gpio, &cfg);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue