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Refactored UART pin config similarly to SPI to accomodate F765

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This commit is contained in:
Andrey Mironov 2018-09-07 23:21:17 +03:00
parent 8073cb8665
commit d6861b0842
6 changed files with 117 additions and 106 deletions
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12
src/main/drivers/serial_uart_stm32f10x.c
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@ -67,8 +67,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
.reg = USART1,
.rxDMAChannel = UART1_RX_DMA_CHANNEL,
.txDMAChannel = UART1_TX_DMA_CHANNEL,
.rxPins = { DEFIO_TAG_E(PA10), DEFIO_TAG_E(PB7), IO_TAG_NONE },
.txPins = { DEFIO_TAG_E(PA9), DEFIO_TAG_E(PB6), IO_TAG_NONE },
.rxPins = { { DEFIO_TAG_E(PA10) }, { DEFIO_TAG_E(PB7) } },
.txPins = { { DEFIO_TAG_E(PA9) }, { DEFIO_TAG_E(PB6) } },
//.af = GPIO_AF_USART1,
.rcc = RCC_APB2(USART1),
.irqn = USART1_IRQn,
@ -82,8 +82,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
.reg = USART2,
.rxDMAChannel = UART2_RX_DMA_CHANNEL,
.txDMAChannel = UART2_TX_DMA_CHANNEL,
.rxPins = { DEFIO_TAG_E(PA3), DEFIO_TAG_E(PD6), IO_TAG_NONE },
.txPins = { DEFIO_TAG_E(PA2), DEFIO_TAG_E(PD5), IO_TAG_NONE },
.rxPins = { { DEFIO_TAG_E(PA3) }, { DEFIO_TAG_E(PD6) } },
.txPins = { { DEFIO_TAG_E(PA2) }, { DEFIO_TAG_E(PD5) } },
//.af = GPIO_AF_USART2,
.rcc = RCC_APB1(USART2),
.irqn = USART2_IRQn,
@ -97,8 +97,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
.reg = USART3,
.rxDMAChannel = UART3_RX_DMA_CHANNEL,
.txDMAChannel = UART3_TX_DMA_CHANNEL,
.rxPins = { DEFIO_TAG_E(PB11), DEFIO_TAG_E(PD9), DEFIO_TAG_E(PC11) },
.txPins = { DEFIO_TAG_E(PB10), DEFIO_TAG_E(PD8), DEFIO_TAG_E(PC10) },
.rxPins = { { DEFIO_TAG_E(PB11) }, { DEFIO_TAG_E(PD9) }, { DEFIO_TAG_E(PC11) } },
.txPins = { { DEFIO_TAG_E(PB10) }, { DEFIO_TAG_E(PD8) }, { DEFIO_TAG_E(PC10) } },
//.af = GPIO_AF_USART3,
.rcc = RCC_APB1(USART3),
.irqn = USART3_IRQn,