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Minor code tidy

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This commit is contained in:
blckmn 2017-07-09 08:04:56 +10:00
parent 750bc6452a
commit df0a2b6a11
2 changed files with 75 additions and 94 deletions
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2
src/main/target/stm32f7xx_hal_conf.h
View file

@ -160,6 +160,8 @@
#define USE_RTOS 0U #define USE_RTOS 0U
#define PREFETCH_ENABLE 0U #define PREFETCH_ENABLE 0U
#define ART_ACCLERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ #define ART_ACCLERATOR_ENABLE 0U /* To enable instruction cache and prefetch */
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 0U
/* ########################## Assert Selection ############################## */ /* ########################## Assert Selection ############################## */
/** /**

61
src/main/target/system_stm32f7xx.c
View file

@ -167,16 +167,14 @@
RCC_OscInitStruct.PLL.PLLQ = PLL_Q; RCC_OscInitStruct.PLL.PLLQ = PLL_Q;
ret = HAL_RCC_OscConfig(&RCC_OscInitStruct); ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
if (ret != HAL_OK) if (ret != HAL_OK) {
{ while (1);
while (1) { ; }
} }
/* Activate the OverDrive to reach the 216 MHz Frequency */ /* Activate the OverDrive to reach the 216 MHz Frequency */
ret = HAL_PWREx_EnableOverDrive(); ret = HAL_PWREx_EnableOverDrive();
if (ret != HAL_OK) if (ret != HAL_OK) {
{ while (1);
while (1) { ; }
} }
/* Select PLLSAI output as USB clock source */ /* Select PLLSAI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
@ -184,9 +182,8 @@
PeriphClkInitStruct.PLLSAI.PLLSAIN = PLL_SAIN; PeriphClkInitStruct.PLLSAI.PLLSAIN = PLL_SAIN;
PeriphClkInitStruct.PLLSAI.PLLSAIQ = PLL_SAIQ; PeriphClkInitStruct.PLLSAI.PLLSAIQ = PLL_SAIQ;
PeriphClkInitStruct.PLLSAI.PLLSAIP = PLL_SAIP; PeriphClkInitStruct.PLLSAI.PLLSAIP = PLL_SAIP;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
{ while (1);
while (1) {};
} }
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
@ -197,9 +194,8 @@
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
if (ret != HAL_OK) if (ret != HAL_OK) {
{ while (1);
while (1) { ; }
} }
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2
@ -221,9 +217,8 @@
PeriphClkInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1; PeriphClkInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PCLK1; PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PCLK1;
ret = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); ret = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
if (ret != HAL_OK) if (ret != HAL_OK) {
{ while (1);
while (1) { ; }
} }
// Activating the timerprescalers while the APBx prescalers are 1/2/4 will connect the TIMxCLK to HCLK which has been configured to 216MHz // Activating the timerprescalers while the APBx prescalers are 1/2/4 will connect the TIMxCLK to HCLK which has been configured to 216MHz
@ -280,25 +275,24 @@ void SystemInit(void)
#endif #endif
/* Enable I-Cache */ /* Enable I-Cache */
if (INSTRUCTION_CACHE_ENABLE) {
SCB_EnableICache(); SCB_EnableICache();
}
/* Enable D-Cache */ /* Enable D-Cache */
//SCB_EnableDCache(); if (DATA_CACHE_ENABLE) {
SCB_EnableDCache();
}
/* Configure the system clock to 216 MHz */ /* Configure the system clock to 216 MHz */
SystemClock_Config(); SystemClock_Config();
if (SystemCoreClock != 216000000) if (SystemCoreClock != 216000000) {
{
while (1)
{
// There is a mismatch between the configured clock and the expected clock in portable.h // There is a mismatch between the configured clock and the expected clock in portable.h
while (1);
} }
} }
}
/** /**
* @brief Update SystemCoreClock variable according to Clock Register Values. * @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can * The SystemCoreClock variable contains the core clock (HCLK), it can
@ -342,8 +336,7 @@ void SystemCoreClockUpdate(void)
/* Get SYSCLK source -------------------------------------------------------*/ /* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS; tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp) switch (tmp) {
{
case 0x00: /* HSI used as system clock source */ case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
break; break;
@ -358,13 +351,10 @@ void SystemCoreClockUpdate(void)
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0) if (pllsource != 0) {
{
/* HSE used as PLL clock source */ /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
} } else {
else
{
/* HSI used as PLL clock source */ /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
} }
@ -383,15 +373,4 @@ void SystemCoreClockUpdate(void)
SystemCoreClock >>= tmp; SystemCoreClock >>= tmp;
} }
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/