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STM32F7 HAL Drivers V1.2.0
This commit is contained in:
Michael Jakob
parent
2e81bd0628
commit
e930261808
186 changed files with 71727 additions and 5749 deletions
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32_hal_legacy.h
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* @author MCD Application Team
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* @version V1.1.2
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* @date 23-September-2016
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* @version V1.2.0
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* @date 30-December-2016
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* @brief This file contains aliases definition for the STM32Cube HAL constants
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* macros and functions maintained for legacy purpose.
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******************************************************************************
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@ -241,9 +241,9 @@
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#define DAC1_CHANNEL_1 DAC_CHANNEL_1
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#define DAC1_CHANNEL_2 DAC_CHANNEL_2
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#define DAC2_CHANNEL_1 DAC_CHANNEL_1
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#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
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#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
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#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
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#define DAC_WAVE_NONE 0x00000000U
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#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
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#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
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#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
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#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
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#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
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@ -917,48 +917,45 @@
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#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
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#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
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#define ETH_MMCCR ((uint32_t)0x00000100U)
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#define ETH_MMCRIR ((uint32_t)0x00000104U)
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#define ETH_MMCTIR ((uint32_t)0x00000108U)
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#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
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#define ETH_MMCTIMR ((uint32_t)0x00000110U)
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#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
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#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
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#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
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#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
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#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
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#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
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#define ETH_MMCCR 0x00000100U
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#define ETH_MMCRIR 0x00000104U
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#define ETH_MMCTIR 0x00000108U
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#define ETH_MMCRIMR 0x0000010CU
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#define ETH_MMCTIMR 0x00000110U
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#define ETH_MMCTGFSCCR 0x0000014CU
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#define ETH_MMCTGFMSCCR 0x00000150U
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#define ETH_MMCTGFCR 0x00000168U
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#define ETH_MMCRFCECR 0x00000194U
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#define ETH_MMCRFAECR 0x00000198U
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#define ETH_MMCRGUFCR 0x000001C4U
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#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
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#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
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#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
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#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
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#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
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#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
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#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
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#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
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#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
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#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
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#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
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#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
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#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
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#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
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#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
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#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
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#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
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#if defined(STM32F1)
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#else
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#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
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#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
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#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
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#endif
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#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
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#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
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#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
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#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
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#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
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#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
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#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
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#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
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#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
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#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
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#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
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#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
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#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
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#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
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#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
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#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
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#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
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#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
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#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
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#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
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#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
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#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
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#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
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#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
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#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
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#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
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#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
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#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
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#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
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#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
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#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
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#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
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#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
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#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
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/**
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* @}
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@ -2231,26 +2228,26 @@
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#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
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#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
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#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
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#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
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#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
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#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
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#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
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#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
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#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
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#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
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#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
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#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
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#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
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#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
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#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
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#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
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#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
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#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
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#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
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#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
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#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
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#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
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#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
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#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
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#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
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#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
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#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
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#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
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#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
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#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
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#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
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#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
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#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
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#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
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#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
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#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
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#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
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#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
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#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
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#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
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#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
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#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
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#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
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#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
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#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
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#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
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@ -2784,11 +2781,14 @@
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#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
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#define DfsdmClockSelection Dfsdm1ClockSelection
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#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
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#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
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#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
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#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
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#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
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#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
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#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
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#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
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#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
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#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
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/**
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* @}
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*/
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@ -2918,6 +2918,14 @@
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#define SDIO_IRQn SDMMC1_IRQn
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#define SDIO_IRQHandler SDMMC1_IRQHandler
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#endif
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#if defined(STM32F7) || defined(STM32F4)
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#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
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#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
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#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
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#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
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#endif
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/**
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* @}
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*/
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75
lib/main/STM32F7xx_HAL_Driver/Inc/stm32_assert_template.h
Normal file
75
lib/main/STM32F7xx_HAL_Driver/Inc/stm32_assert_template.h
Normal file
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@ -0,0 +1,75 @@
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/**
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******************************************************************************
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* @file stm32_assert.h
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* @author MCD Application Team
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* @version V1.2.0
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* @date 30-December-2016
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* @brief STM32 assert template file.
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* This file should be copied to the application folder and renamed
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* to stm32_assert.h.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32_ASSERT_H
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#define __STM32_ASSERT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/* Includes ------------------------------------------------------------------*/
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/* Exported macro ------------------------------------------------------------*/
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#ifdef USE_FULL_ASSERT
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/**
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* @brief The assert_param macro is used for function's parameters check.
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* @param expr: If expr is false, it calls assert_failed function
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* which reports the name of the source file and the source
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* line number of the call that failed.
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* If expr is true, it returns no value.
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* @retval None
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*/
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#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
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/* Exported functions ------------------------------------------------------- */
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void assert_failed(uint8_t* file, uint32_t line);
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#else
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#define assert_param(expr) ((void)0U)
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#endif /* USE_FULL_ASSERT */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32_ASSERT_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f7xx_hal.h
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* @author MCD Application Team
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* @version V1.1.2
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* @date 23-September-2016
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* @version V1.2.0
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* @date 30-December-2016
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* @brief This file contains all the functions prototypes for the HAL
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* module driver.
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******************************************************************************
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f7xx_hal_adc.h
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* @author MCD Application Team
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* @version V1.1.2
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* @date 23-September-2016
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* @version V1.2.0
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* @date 30-December-2016
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* @brief Header file of ADC HAL extension module.
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******************************************************************************
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* @attention
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@ -88,6 +88,7 @@ typedef struct
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Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
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If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
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Scan direction is upward: from rank1 to rank 'n'.
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This parameter can be a value of @ref ADC_Scan_mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
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This parameter can be a value of @ref ADC_EOCSelection.
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|
@ -135,7 +136,8 @@ typedef struct
|
|||
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
|
||||
This parameter can be a value of @ref ADC_channels */
|
||||
uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 16
|
||||
This parameter can be a value of @ref ADC_regular_rank */
|
||||
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles
|
||||
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
|
||||
|
|
@ -337,6 +339,38 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */
|
||||
#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_rank ADC group regular sequencer rank
|
||||
* @{
|
||||
*/
|
||||
#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */
|
||||
#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */
|
||||
#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */
|
||||
#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */
|
||||
#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */
|
||||
#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */
|
||||
#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */
|
||||
#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */
|
||||
#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */
|
||||
#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */
|
||||
#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */
|
||||
#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */
|
||||
#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */
|
||||
#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */
|
||||
#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */
|
||||
#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels ADC Common Channels
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -707,6 +741,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
|||
#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
|
||||
((__ALIGN__) == ADC_DATAALIGN_LEFT))
|
||||
|
||||
|
||||
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \
|
||||
|
|
@ -730,9 +765,29 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
|||
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
|
||||
((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
|
||||
((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
|
||||
|
||||
#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_2 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_3 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_4 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_5 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_6 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_7 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_8 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_9 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_10) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_11) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_12) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_13) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_14) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_15) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_16))
|
||||
|
||||
#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
|
||||
((__SCAN_MODE__) == ADC_SCAN_ENABLE))
|
||||
|
||||
#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
|
||||
#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
|
||||
#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16)))
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
|
||||
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
|
||||
((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of ADC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -217,7 +217,7 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_injected_rank ADC Injected Rank
|
||||
/** @defgroup ADCEx_injected_rank ADC Injected Channel Rank
|
||||
* @{
|
||||
*/
|
||||
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U)
|
||||
|
|
@ -334,8 +334,11 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
|
|||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
|
||||
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
|
||||
#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) == ADC_INJECTED_RANK_1) || \
|
||||
((__RANK__) == ADC_INJECTED_RANK_2) || \
|
||||
((__RANK__) == ADC_INJECTED_RANK_3) || \
|
||||
((__RANK__) == ADC_INJECTED_RANK_4))
|
||||
#define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
|
||||
#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4)))
|
||||
|
||||
/**
|
||||
* @brief Set the selected injected Channel rank.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of CAN HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -232,8 +232,8 @@ typedef struct
|
|||
|
||||
HAL_LockTypeDef Lock; /*!< CAN locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CAN Error code */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CAN Error code
|
||||
This parameter can be a value of @ref CAN_Error_Code */
|
||||
}CAN_HandleTypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -245,7 +245,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code
|
||||
/** @defgroup CAN_Error_Code CAN Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CAN_ERROR_NONE 0x00U /*!< No error */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_cec.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of CEC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -43,11 +43,11 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (CEC)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (CEC)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_conf_template.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32f7xx_hal_conf.h.
|
||||
|
|
@ -97,6 +97,8 @@
|
|||
#define HAL_DSI_MODULE_ENABLED
|
||||
#define HAL_JPEG_MODULE_ENABLED
|
||||
#define HAL_MDIOS_MODULE_ENABLED
|
||||
#define HAL_SMBUS_MODULE_ENABLED
|
||||
#define HAL_MMC_MODULE_ENABLED
|
||||
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
|
|
@ -426,6 +428,14 @@
|
|||
#include "stm32f7xx_hal_mdios.h"
|
||||
#endif /* HAL_MDIOS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_crc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of CRC HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_cryp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of CRYP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -527,6 +527,638 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
|
|||
* @}
|
||||
*/
|
||||
|
||||
#if defined (AES)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Types CRYP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRYP Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
||||
This parameter can be a value of @ref CRYP_Data_Type */
|
||||
|
||||
uint32_t KeySize; /*!< 128 or 256-bit key length.
|
||||
This parameter can be a value of @ref CRYP_Key_Size */
|
||||
|
||||
uint32_t OperatingMode; /*!< AES operating mode.
|
||||
This parameter can be a value of @ref CRYP_AES_OperatingMode */
|
||||
|
||||
uint32_t ChainingMode; /*!< AES chaining mode.
|
||||
This parameter can be a value of @ref CRYP_AES_ChainingMode */
|
||||
|
||||
uint32_t KeyWriteFlag; /*!< Allows to bypass or not key write-up before decryption.
|
||||
This parameter can be a value of @ref CRYP_Key_Write */
|
||||
|
||||
uint32_t GCMCMACPhase; /*!< Indicates the processing phase of the Galois Counter Mode (GCM),
|
||||
Galois Message Authentication Code (GMAC) or Cipher Message
|
||||
Authentication Code (CMAC) or Counter with Cipher Mode (CCM) when
|
||||
the latter is applicable.
|
||||
This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */
|
||||
|
||||
uint8_t* pKey; /*!< Encryption/Decryption Key */
|
||||
|
||||
uint8_t* pInitVect; /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC,
|
||||
(and CCM when applicable) modes */
|
||||
|
||||
uint8_t* Header; /*!< Header used in GCM/GMAC, CMAC (and CCM when applicable) modes */
|
||||
|
||||
uint64_t HeaderSize; /*!< Header size in bytes */
|
||||
|
||||
}CRYP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CRYP State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */
|
||||
HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */
|
||||
HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */
|
||||
HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */
|
||||
HAL_CRYP_STATE_ERROR = 0x04, /*!< CRYP error state */
|
||||
HAL_CRYP_STATE_SUSPENDED = 0x05 /*!< CRYP suspended */
|
||||
}HAL_CRYP_STATETypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CRYP phase structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
|
||||
HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */
|
||||
HAL_CRYP_PHASE_START = 0x03, /*!< CRYP peripheral has been initialized but
|
||||
GCM/GMAC/CMAC(/CCM) initialization phase has not started */
|
||||
HAL_CRYP_PHASE_INIT_OVER = 0x04, /*!< GCM/GMAC/CMAC(/CCM) init phase has been carried out */
|
||||
HAL_CRYP_PHASE_HEADER_OVER = 0x05, /*!< GCM/GMAC/CMAC(/CCM) header phase has been carried out */
|
||||
HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06, /*!< GCM(/CCM) payload phase has been carried out */
|
||||
HAL_CRYP_PHASE_FINAL_OVER = 0x07, /*!< GCM/GMAC/CMAC(/CCM) final phase has been carried out */
|
||||
HAL_CRYP_PHASE_HEADER_SUSPENDED = 0x08, /*!< GCM/GMAC/CMAC(/CCM) header phase has been suspended */
|
||||
HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09, /*!< GCM(/CCM) payload phase has been suspended */
|
||||
HAL_CRYP_PHASE_NOT_USED = 0x0a /*!< Phase is irrelevant to the current chaining mode */
|
||||
}HAL_PhaseTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CRYP mode suspend definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_SUSPEND_NONE = 0x00, /*!< CRYP peripheral suspension not requested */
|
||||
HAL_CRYP_SUSPEND = 0x01 /*!< CRYP peripheral suspension requested */
|
||||
}HAL_SuspendTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL CRYP Error Codes definition
|
||||
*/
|
||||
#define HAL_CRYP_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
|
||||
#define HAL_CRYP_WRITE_ERROR ((uint32_t)0x00000001) /*!< Write error */
|
||||
#define HAL_CRYP_READ_ERROR ((uint32_t)0x00000002) /*!< Read error */
|
||||
#define HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004) /*!< DMA error */
|
||||
#define HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008) /*!< Busy flag error */
|
||||
|
||||
/**
|
||||
* @brief CRYP handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
AES_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CRYP_InitTypeDef Init; /*!< CRYP initialization parameters */
|
||||
|
||||
uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) input buffer */
|
||||
|
||||
uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */
|
||||
|
||||
uint32_t CrypInCount; /*!< Input data size in bytes or, after suspension, the remaining
|
||||
number of bytes to process */
|
||||
|
||||
uint32_t CrypOutCount; /*!< Output data size in bytes */
|
||||
|
||||
HAL_PhaseTypeDef Phase; /*!< CRYP peripheral processing phase for GCM, GMAC, CMAC
|
||||
(or CCM when applicable) modes.
|
||||
Indicates the last phase carried out to ease
|
||||
phase transitions */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< CRYP peripheral Input DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaout; /*!< CRYP peripheral Output DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRYP locking object */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
|
||||
|
||||
HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
|
||||
}CRYP_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Size Key size selection
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000) /*!< 128-bit long key */
|
||||
#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Type AES Data Type selection
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000) /*!< 32-bit data type (no swapping) */
|
||||
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
|
||||
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
|
||||
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_AES_State AES Enable state
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_AES_DISABLE ((uint32_t)0x00000000) /*!< Disable AES */
|
||||
#define CRYP_AES_ENABLE AES_CR_EN /*!< Enable AES */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_AES_OperatingMode AES operating mode
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_ALGOMODE_ENCRYPT ((uint32_t)0x00000000) /*!< Encryption mode */
|
||||
#define CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode */
|
||||
#define CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */
|
||||
#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption */
|
||||
#define CRYP_ALGOMODE_TAG_GENERATION ((uint32_t)0x00000000) /*!< GMAC or CMAC authentication tag generation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_AES_ChainingMode AES chaining mode
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_CHAINMODE_AES_ECB ((uint32_t)0x00000000) /*!< Electronic codebook chaining algorithm */
|
||||
#define CRYP_CHAINMODE_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
|
||||
#define CRYP_CHAINMODE_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
|
||||
#define CRYP_CHAINMODE_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
|
||||
#define CRYP_CHAINMODE_AES_CMAC AES_CR_CHMOD_2 /*!< Cipher message authentication code */
|
||||
#if defined(AES_CR_NPBLB)
|
||||
#define CRYP_CHAINMODE_AES_CCM_CMAC AES_CR_CHMOD_2 /*!< Counter with Cipher Mode - Cipher message authentication code */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Write AES decryption key write-up flag
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_KEY_WRITE_ENABLE ((uint32_t)0x00000000) /*!< Enable decryption key writing */
|
||||
#define CRYP_KEY_WRITE_DISABLE ((uint32_t)0x00000001) /*!< Disable decryption key writing */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_DMAIN DMA Input phase management enable state
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_DMAIN_DISABLE ((uint32_t)0x00000000) /*!< Disable DMA Input phase management */
|
||||
#define CRYP_DMAIN_ENABLE AES_CR_DMAINEN /*!< Enable DMA Input phase management */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_DMAOUT DMA Output phase management enable state
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_DMAOUT_DISABLE ((uint32_t)0x00000000) /*!< Disable DMA Output phase management */
|
||||
#define CRYP_DMAOUT_ENABLE AES_CR_DMAOUTEN /*!< Enable DMA Output phase management */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CMAC processing phase selection
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000) /*!< GCM/GMAC (or CCM) init phase */
|
||||
#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0 /*!< GCM/GMAC or (CCM/)CMAC header phase */
|
||||
#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
|
||||
#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH /*!< GCM/GMAC or (CCM/)CMAC final phase */
|
||||
/* Definitions duplication for code readibility's sake:
|
||||
supported or not supported chain modes are not specified for each phase */
|
||||
#define CRYP_INIT_PHASE ((uint32_t)0x00000000) /*!< Init phase */
|
||||
#define CRYP_HEADER_PHASE AES_CR_GCMPH_0 /*!< Header phase */
|
||||
#define CRYP_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< Payload phase */
|
||||
#define CRYP_FINAL_PHASE AES_CR_GCMPH /*!< Final phase */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Flags AES status flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
|
||||
#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */
|
||||
#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */
|
||||
#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Clear_Flags AES clearing flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */
|
||||
#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
|
||||
#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Interrupts_Flags AES Interrupts flags
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
|
||||
#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
|
||||
#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRYP handle state.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the CRYP AES peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_ENABLE() (AES->CR |= AES_CR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the CRYP AES peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_DISABLE() (AES->CR &= ~AES_CR_EN)
|
||||
|
||||
/**
|
||||
* @brief Set the algorithm operating mode.
|
||||
* @param __OPERATING_MODE__: specifies the operating mode
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_ALGOMODE_ENCRYPT encryption
|
||||
* @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation
|
||||
* @arg @ref CRYP_ALGOMODE_DECRYPT decryption
|
||||
* @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_SET_OPERATINGMODE(__OPERATING_MODE__) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the algorithm chaining mode.
|
||||
* @param __CHAINING_MODE__: specifies the chaining mode
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook
|
||||
* @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining
|
||||
* @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode
|
||||
* @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code
|
||||
* @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_SET_CHAININGMODE(__CHAINING_MODE__) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__))
|
||||
|
||||
|
||||
|
||||
/** @brief Check whether the specified CRYP status flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
|
||||
* @arg @ref CRYP_IT_WRERR Write Error
|
||||
* @arg @ref CRYP_IT_RDERR Read Error
|
||||
* @arg @ref CRYP_IT_CCF Computation Complete
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Clear the CRYP pending status flag.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
|
||||
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_CLEAR_FLAG(__FLAG__) SET_BIT(AES->CR, (__FLAG__))
|
||||
|
||||
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
|
||||
* @param __INTERRUPT__: CRYP interrupt source to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* @retval State of interruption (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CRYP_GET_IT_SOURCE(__INTERRUPT__) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt is set or not.
|
||||
* @param __INTERRUPT__: specifies the interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_IT_WRERR Write Error
|
||||
* @arg @ref CRYP_IT_RDERR Read Error
|
||||
* @arg @ref CRYP_IT_CCF Computation Complete
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
|
||||
|
||||
/** @brief Clear the CRYP pending interrupt.
|
||||
* @param __INTERRUPT__: specifies the IT to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
|
||||
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_CLEAR_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the CRYP interrupt.
|
||||
* @param __INTERRUPT__: CRYP Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the CRYP interrupt.
|
||||
* @param __INTERRUPT__: CRYP Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @addtogroup CRYP_Private_Macros CRYP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Verify the key size length.
|
||||
* @param __KEYSIZE__: Ciphering/deciphering algorithm key size.
|
||||
* @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)
|
||||
*/
|
||||
#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
|
||||
((__KEYSIZE__) == CRYP_KEYSIZE_256B))
|
||||
|
||||
/**
|
||||
* @brief Verify the input data type.
|
||||
* @param __DATATYPE__: Ciphering/deciphering algorithm input data type.
|
||||
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
|
||||
*/
|
||||
#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
|
||||
((__DATATYPE__) == CRYP_DATATYPE_16B) || \
|
||||
((__DATATYPE__) == CRYP_DATATYPE_8B) || \
|
||||
((__DATATYPE__) == CRYP_DATATYPE_1B))
|
||||
|
||||
/**
|
||||
* @brief Verify the CRYP AES IP running mode.
|
||||
* @param __MODE__: CRYP AES IP running mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \
|
||||
((__MODE__) == CRYP_AES_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Verify the selected CRYP algorithm.
|
||||
* @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
|
||||
* @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)
|
||||
*/
|
||||
#define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT) || \
|
||||
((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION) || \
|
||||
((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT) || \
|
||||
((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \
|
||||
((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT))
|
||||
|
||||
/**
|
||||
* @brief Verify the selected CRYP chaining algorithm.
|
||||
* @param __CHAINMODE__: Selected CRYP chaining algorithm.
|
||||
* @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)
|
||||
*/
|
||||
#if defined(AES_CR_NPBLB)
|
||||
#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \
|
||||
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \
|
||||
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \
|
||||
((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
|
||||
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM_CMAC))
|
||||
#else
|
||||
#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \
|
||||
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \
|
||||
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \
|
||||
((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
|
||||
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Verify the deciphering key write option.
|
||||
* @param __WRITE__: deciphering key write option.
|
||||
* @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)
|
||||
*/
|
||||
#define IS_CRYP_WRITE(__WRITE__) (((__WRITE__) == CRYP_KEY_WRITE_ENABLE) || \
|
||||
((__WRITE__) == CRYP_KEY_WRITE_DISABLE))
|
||||
|
||||
/**
|
||||
* @brief Verify the CRYP input data DMA mode.
|
||||
* @param __MODE__: CRYP input data DMA mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \
|
||||
((__MODE__) == CRYP_DMAIN_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Verify the CRYP output data DMA mode.
|
||||
* @param __MODE__: CRYP output data DMA mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \
|
||||
((__MODE__) == CRYP_DMAOUT_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.
|
||||
* @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase.
|
||||
* @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)
|
||||
*/
|
||||
#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE) || \
|
||||
((__PHASE__) == CRYP_GCMCMAC_HEADER_PHASE) || \
|
||||
((__PHASE__) == CRYP_GCM_PAYLOAD_PHASE) || \
|
||||
((__PHASE__) == CRYP_GCMCMAC_FINAL_PHASE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRYP HAL Extended module */
|
||||
#include "stm32f7xx_hal_cryp_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CRYP_Exported_Functions CRYP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/* MSP initialization/de-initialization functions ****************************/
|
||||
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AES encryption/decryption processing functions ****************************/
|
||||
|
||||
/* AES encryption/decryption using polling ***********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
|
||||
|
||||
/* AES encryption/decryption using interrupt *********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
|
||||
/* AES encryption/decryption using DMA ***************************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group3 Callback functions
|
||||
* @{
|
||||
*/
|
||||
/* CallBack functions ********************************************************/
|
||||
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AES interrupt handling function *******************************************/
|
||||
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
|
||||
uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* AES */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_cryp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of CRYP HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -209,6 +209,76 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
|
|||
|
||||
#endif /* CRYP */
|
||||
|
||||
#if defined (AES)
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* CallBack functions ********************************************************/
|
||||
void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AES encryption/decryption processing functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
|
||||
|
||||
/* AES encryption/decryption/authentication processing functions *************/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AES suspension/resumption functions ***************************************/
|
||||
void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
|
||||
void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
|
||||
void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
|
||||
void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
|
||||
void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize);
|
||||
void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize);
|
||||
void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
|
||||
void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
|
||||
void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions -----------------------------------------------------------*/
|
||||
/** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* AES */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of DAC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of DAC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dcmi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of DCMI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -43,11 +43,11 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (DCMI)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (DCMI)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dcmi_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of DCMI Extension HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dfsdm.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of DFSDM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dma2d.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of DMA2D HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -43,11 +43,11 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (DMA2D)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (DMA2D)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -93,7 +93,9 @@ typedef enum
|
|||
#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
|
||||
#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
|
||||
#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
|
||||
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
|
||||
defined (STM32F779xx)
|
||||
#define DMA_CHANNEL_8 ((uint32_t)0x10000000U) /*!< DMA Channel 8 */
|
||||
#define DMA_CHANNEL_9 ((uint32_t)0x12000000U) /*!< DMA Channel 9 */
|
||||
#define DMA_CHANNEL_10 ((uint32_t)0x14000000U) /*!< DMA Channel 10*/
|
||||
|
|
@ -102,7 +104,8 @@ typedef enum
|
|||
#define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) /*!< DMA Channel 13*/
|
||||
#define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) /*!< DMA Channel 14*/
|
||||
#define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) /*!< DMA Channel 15*/
|
||||
#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
|
||||
STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -140,7 +143,9 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
|
|||
* @brief DMAEx private macros
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
|
||||
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
|
||||
defined (STM32F779xx)
|
||||
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
|
||||
((CHANNEL) == DMA_CHANNEL_1) || \
|
||||
((CHANNEL) == DMA_CHANNEL_2) || \
|
||||
|
|
@ -166,7 +171,8 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
|
|||
((CHANNEL) == DMA_CHANNEL_5) || \
|
||||
((CHANNEL) == DMA_CHANNEL_6) || \
|
||||
((CHANNEL) == DMA_CHANNEL_7))
|
||||
#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
|
||||
STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dsi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of DSI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_eth.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of ETH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -43,11 +43,11 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (ETH)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (ETH)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of FLASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -111,6 +111,7 @@ typedef struct
|
|||
#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */
|
||||
#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */
|
||||
#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */
|
||||
#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000040U) /*!< Read Protection Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -138,9 +139,14 @@ typedef struct
|
|||
#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protection error flag */
|
||||
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
|
||||
FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR)
|
||||
#else
|
||||
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
|
||||
FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR)
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of FLASH HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -113,6 +113,14 @@ typedef struct
|
|||
uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1.
|
||||
This parameter can be a value of @ref FLASHEx_Boot_Address */
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
uint32_t PCROPSector; /*!< Set the PCROP sector.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */
|
||||
|
||||
uint32_t PCROPRdp; /*!< Set the PCROP_RDP option.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -162,6 +170,10 @@ typedef struct
|
|||
#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */
|
||||
#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */
|
||||
#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#define OPTIONBYTE_PCROP ((uint32_t)0x40U) /*!< PCROP configuration */
|
||||
#define OPTIONBYTE_PCROP_RDP ((uint32_t)0x80U) /*!< PCROP_RDP configuration */
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -275,7 +287,11 @@ typedef struct
|
|||
#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */
|
||||
#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */
|
||||
#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */
|
||||
#if (SRAM2_BASE == 0x2003C000U)
|
||||
#define OB_BOOTADDR_SRAM2 ((uint32_t)0x800FU) /*!< Boot from SRAM2 (0x2003C000) */
|
||||
#else
|
||||
#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */
|
||||
#endif /* SRAM2_BASE == 0x2003C000U */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -426,6 +442,33 @@ typedef struct
|
|||
*/
|
||||
#endif /* FLASH_SECTOR_TOTAL == 8 */
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */
|
||||
#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */
|
||||
#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */
|
||||
#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */
|
||||
#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4 */
|
||||
#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5 */
|
||||
#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6 */
|
||||
#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7 */
|
||||
#define OB_PCROP_SECTOR_All ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_RDP_ENABLE ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable */
|
||||
#define OB_PCROP_RDP_DISABLE ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -489,8 +532,14 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
|||
#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
|
||||
((VALUE) == OB_WRPSTATE_ENABLE))
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
|
||||
OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\
|
||||
OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP)))
|
||||
#else
|
||||
#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
|
||||
OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)
|
||||
|
||||
|
|
@ -530,8 +579,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
|||
((LATENCY) == FLASH_LATENCY_14) || \
|
||||
((LATENCY) == FLASH_LATENCY_15))
|
||||
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
|
||||
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
|
||||
(((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
|
||||
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 8)
|
||||
|
|
@ -574,6 +623,12 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
|||
((VALUE) == OB_DUAL_BOOT_ENABLE))
|
||||
#endif /* FLASH_OPTCR_nDBOOT */
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#define IS_OB_PCROP_SECTOR(SECTOR) (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U)
|
||||
#define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \
|
||||
((VALUE) == OB_PCROP_RDP_ENABLE))
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of GPIO HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -65,7 +65,7 @@
|
|||
* @{
|
||||
*/
|
||||
/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/
|
||||
#if defined (STM32F722xx) || defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\
|
||||
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\
|
||||
defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
|
|
@ -237,6 +237,122 @@
|
|||
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/
|
||||
#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx)
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */
|
||||
#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */
|
||||
#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */
|
||||
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
|
||||
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */
|
||||
#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_RNG ((uint8_t)0x0DU) /* RNG Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
|
||||
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -295,7 +411,7 @@
|
|||
/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F722xx) || defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
|
||||
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
|
||||
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
|
|
@ -309,6 +425,16 @@
|
|||
((__GPIOx__) == (GPIOJ))? 9U : 10U)
|
||||
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U :\
|
||||
((__GPIOx__) == (GPIOD))? 3U :\
|
||||
((__GPIOx__) == (GPIOE))? 4U :\
|
||||
((__GPIOx__) == (GPIOF))? 5U :\
|
||||
((__GPIOx__) == (GPIOG))? 6U :\
|
||||
((__GPIOx__) == (GPIOH))? 7U : 8U)
|
||||
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -359,7 +485,7 @@
|
|||
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
|
||||
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \
|
||||
((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC))
|
||||
#elif defined (STM32F722xx) || defined(STM32F745xx)
|
||||
#elif defined(STM32F745xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
|
|
@ -487,6 +613,33 @@
|
|||
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
|
||||
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
|
||||
((AF) == GPIO_AF10_OTG_FS))
|
||||
#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
|
||||
((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI3) || \
|
||||
((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF5_SPI5) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM14) || \
|
||||
((AF) == GPIO_AF9_QUADSPI) || ((AF) == GPIO_AF10_OTG_HS) || \
|
||||
((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QUADSPI) || \
|
||||
((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
|
||||
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
|
||||
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \
|
||||
((AF) == GPIO_AF10_OTG_FS))
|
||||
#endif /* STM32F756xx || STM32F746xx */
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_hash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of HASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_hash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of HASH HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_hcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of HCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -98,32 +98,31 @@ typedef struct
|
|||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : Abort (Abort user request on going)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
|
||||
* b4 (not used)
|
||||
* x : Should be set to 0
|
||||
* b3
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)
|
||||
* 1 : Listen (IP in Address Listen Mode)
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* @note HAL I2C State value coding follow below described bitmap :\n
|
||||
* b7-b6 Error information\n
|
||||
* 00 : No Error\n
|
||||
* 01 : Abort (Abort user request on going)\n
|
||||
* 10 : Timeout\n
|
||||
* 11 : Error\n
|
||||
* b5 IP initilisation status\n
|
||||
* 0 : Reset (IP not initialized)\n
|
||||
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
|
||||
* b4 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b3\n
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)\n
|
||||
* 1 : Listen (IP in Address Listen Mode)\n
|
||||
* b2 Intrinsic process state\n
|
||||
* 0 : Ready\n
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)\n
|
||||
* b1 Rx state\n
|
||||
* 0 : Ready (no Rx operation ongoing)\n
|
||||
* 1 : Busy (Rx operation ongoing)\n
|
||||
* b0 Tx state\n
|
||||
* 0 : Ready (no Tx operation ongoing)\n
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
|
|
@ -136,7 +135,7 @@ typedef enum
|
|||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
|
|
@ -148,19 +147,19 @@ typedef enum
|
|||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :
|
||||
* b7 (not used)
|
||||
* x : Should be set to 0
|
||||
* b6
|
||||
* 0 : None
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)
|
||||
* b5
|
||||
* 0 : None
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)
|
||||
* b4
|
||||
* 0 : None
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)
|
||||
* b3-b2-b1-b0 (not used)
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -181,15 +180,14 @@ typedef enum
|
|||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< ACKF error */
|
||||
#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
|
||||
#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040U) /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_ABORT ((uint32_t)0x00000080U) /*!< Abort user request */
|
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -259,8 +257,8 @@ typedef struct __I2C_HandleTypeDef
|
|||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U)
|
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -268,7 +266,7 @@ typedef struct __I2C_HandleTypeDef
|
|||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
|
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -292,7 +290,7 @@ typedef struct __I2C_HandleTypeDef
|
|||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
|
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -301,7 +299,7 @@ typedef struct __I2C_HandleTypeDef
|
|||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
|
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -310,17 +308,17 @@ typedef struct __I2C_HandleTypeDef
|
|||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U)
|
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XferDirection I2C Transfer Direction
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000000U)
|
||||
#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000001U)
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
||||
#define I2C_DIRECTION_RECEIVE (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -330,7 +328,7 @@ typedef struct __I2C_HandleTypeDef
|
|||
*/
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE ((uint32_t)0x00000000U)
|
||||
#define I2C_SOFTEND_MODE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -338,7 +336,7 @@ typedef struct __I2C_HandleTypeDef
|
|||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NO_STARTSTOP ((uint32_t)0x00000000U)
|
||||
#define I2C_NO_STARTSTOP (0x00000000U)
|
||||
#define I2C_GENERATE_STOP I2C_CR2_STOP
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE I2C_CR2_START
|
||||
|
|
@ -667,17 +665,17 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
|||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16)
|
||||
#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
|
||||
#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
|
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
|
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @brief Header file of I2C HAL Extension module.
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of I2C HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
|
|
@ -57,14 +57,14 @@
|
|||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
|
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -73,19 +73,41 @@
|
|||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
|
||||
#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP
|
||||
#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP
|
||||
#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP
|
||||
#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP
|
||||
|
||||
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP
|
||||
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP
|
||||
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP
|
||||
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP
|
||||
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
|
||||
#if defined(SYSCFG_PMC_I2C_PB6_FMP)
|
||||
#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
|
||||
#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_PB6 (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported */
|
||||
#define I2C_FASTMODEPLUS_PB7 (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported */
|
||||
#endif
|
||||
#if defined(SYSCFG_PMC_I2C_PB8_FMP)
|
||||
#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
|
||||
#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */
|
||||
#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */
|
||||
#endif
|
||||
#if defined(SYSCFG_PMC_I2C1_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */
|
||||
#endif
|
||||
#if defined(SYSCFG_PMC_I2C2_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
|
||||
#endif
|
||||
#if defined(SYSCFG_PMC_I2C3_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
|
||||
#endif
|
||||
#if defined(SYSCFG_PMC_I2C4_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -97,16 +119,25 @@
|
|||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Peripheral Control methods ************************************************/
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
#if defined(SYSCFG_PMC_I2C1_FMP)
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
#endif /* SYSCFG_PMC_I2C1_FMP */
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -115,7 +146,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
|
|
@ -157,15 +188,20 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -184,5 +220,4 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|||
|
||||
#endif /* __STM32F7xx_HAL_I2C_EX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_i2s.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of IRDA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -599,7 +599,7 @@ typedef struct
|
|||
#include "stm32f7xx_hal_irda_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Exported_Functions IrDA Exported Functions
|
||||
/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_irda_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of IRDA HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of IWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_jpeg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of JPEG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_lptim.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of LPTIM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_ltdc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of LTDC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_ltdc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of LTDC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_mdios.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of MDIOS HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -43,11 +43,11 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (MDIOS)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (MDIOS)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
|
|
|||
695
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h
Normal file
695
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h
Normal file
|
|
@ -0,0 +1,695 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_mmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of MMC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_MMC_H
|
||||
#define __STM32F7xx_HAL_MMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_ll_sdmmc.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup MMC_Exported_Types MMC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */
|
||||
HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */
|
||||
HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */
|
||||
HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */
|
||||
HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */
|
||||
HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
|
||||
HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */
|
||||
HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
|
||||
}HAL_MMC_StateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_MMC_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
|
||||
HAL_MMC_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
|
||||
HAL_MMC_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
|
||||
HAL_MMC_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
|
||||
HAL_MMC_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
|
||||
HAL_MMC_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
|
||||
HAL_MMC_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
|
||||
HAL_MMC_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
|
||||
HAL_MMC_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
|
||||
}HAL_MMC_CardStateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define MMC_InitTypeDef SDMMC_InitTypeDef
|
||||
#define MMC_TypeDef SDMMC_TypeDef
|
||||
|
||||
/**
|
||||
* @brief MMC Card Information Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CardType; /*!< Specifies the card Type */
|
||||
|
||||
uint32_t Class; /*!< Specifies the class of the card class */
|
||||
|
||||
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
|
||||
|
||||
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
|
||||
|
||||
uint32_t BlockSize; /*!< Specifies one block size in bytes */
|
||||
|
||||
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
|
||||
|
||||
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
|
||||
|
||||
}HAL_MMC_CardInfoTypeDef;
|
||||
|
||||
/**
|
||||
* @brief MMC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
MMC_TypeDef *Instance; /*!< MMC registers base address */
|
||||
|
||||
MMC_InitTypeDef Init; /*!< MMC required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< MMC locking object */
|
||||
|
||||
uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
|
||||
|
||||
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
|
||||
|
||||
uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
|
||||
|
||||
uint32_t RxXferSize; /*!< MMC Rx Transfer size */
|
||||
|
||||
__IO uint32_t Context; /*!< MMC transfer context */
|
||||
|
||||
__IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< MMC Card Error codes */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
|
||||
|
||||
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
|
||||
|
||||
uint32_t CSD[4]; /*!< MMC card specific data table */
|
||||
|
||||
uint32_t CID[4]; /*!< MMC card identification number table */
|
||||
|
||||
}MMC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t CSDStruct; /*!< CSD structure */
|
||||
__IO uint8_t SysSpecVersion; /*!< System specification version */
|
||||
__IO uint8_t Reserved1; /*!< Reserved */
|
||||
__IO uint8_t TAAC; /*!< Data read access time 1 */
|
||||
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
|
||||
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
|
||||
__IO uint16_t CardComdClasses; /*!< Card command classes */
|
||||
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
|
||||
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
|
||||
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
|
||||
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
|
||||
__IO uint8_t DSRImpl; /*!< DSR implemented */
|
||||
__IO uint8_t Reserved2; /*!< Reserved */
|
||||
__IO uint32_t DeviceSize; /*!< Device Size */
|
||||
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
|
||||
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
|
||||
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
|
||||
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
|
||||
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
|
||||
__IO uint8_t EraseGrSize; /*!< Erase group size */
|
||||
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
|
||||
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
|
||||
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
|
||||
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
|
||||
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
|
||||
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
|
||||
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
|
||||
__IO uint8_t Reserved3; /*!< Reserved */
|
||||
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
|
||||
__IO uint8_t FileFormatGrouop; /*!< File format group */
|
||||
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
|
||||
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
|
||||
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
|
||||
__IO uint8_t FileFormat; /*!< File format */
|
||||
__IO uint8_t ECC; /*!< ECC code */
|
||||
__IO uint8_t CSD_CRC; /*!< CSD CRC */
|
||||
__IO uint8_t Reserved4; /*!< Always 1 */
|
||||
|
||||
}HAL_MMC_CardCSDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
|
||||
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
|
||||
__IO uint32_t ProdName1; /*!< Product Name part1 */
|
||||
__IO uint8_t ProdName2; /*!< Product Name part2 */
|
||||
__IO uint8_t ProdRev; /*!< Product Revision */
|
||||
__IO uint32_t ProdSN; /*!< Product Serial Number */
|
||||
__IO uint8_t Reserved1; /*!< Reserved1 */
|
||||
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
|
||||
__IO uint8_t CID_CRC; /*!< CID CRC */
|
||||
__IO uint8_t Reserved2; /*!< Always 1 */
|
||||
|
||||
}HAL_MMC_CardCIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup MMC_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
|
||||
#define CAPACITY ((uint32_t)0x80000000U) /*!< 2 G bytes constant */
|
||||
|
||||
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
|
||||
#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
|
||||
#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
|
||||
#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
|
||||
#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
|
||||
#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
|
||||
#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
|
||||
#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
|
||||
#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
|
||||
number of transferred bytes does not match the block length */
|
||||
#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
|
||||
#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
|
||||
#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
|
||||
#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
|
||||
command or if there was an attempt to access a locked card */
|
||||
#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
|
||||
#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
|
||||
#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
|
||||
#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
|
||||
#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
|
||||
#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
|
||||
#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
|
||||
#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
|
||||
#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
|
||||
#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
|
||||
#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
|
||||
of erase sequence command was received */
|
||||
#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
|
||||
#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
|
||||
#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
|
||||
#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
|
||||
#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
|
||||
#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
|
||||
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
|
||||
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
|
||||
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
|
||||
* @{
|
||||
*/
|
||||
#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
|
||||
#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
|
||||
#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
|
||||
#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
|
||||
#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
|
||||
#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
|
||||
#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief
|
||||
*/
|
||||
#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
|
||||
#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
|
||||
#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
|
||||
#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
|
||||
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
|
||||
* @{
|
||||
*/
|
||||
#define MMC_HIGH_VOLTAGE_CARD ((uint32_t)0x00000000U)
|
||||
#define MMC_DUAL_VOLTAGE_CARD ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup MMC_Exported_macros MMC Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the MMC device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Disable the MMC device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Enable the SDMMC DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Disable the SDMMC DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Enable the MMC device interrupt.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the MMC device interrupt.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified MMC flag is set or not.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
|
||||
* @arg SDMMC_FLAG_TXACT: Data transmit in progress
|
||||
* @arg SDMMC_FLAG_RXACT: Data receive in progress
|
||||
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
||||
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
|
||||
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
|
||||
* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
|
||||
* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
|
||||
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
|
||||
* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
|
||||
* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
|
||||
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @retval The new state of MMC FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the MMC's pending flags.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified MMC interrupt has occurred or not.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval The new state of SD IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the MMC's interrupt pending bits.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup MMC_Exported_Functions MMC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
|
||||
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
|
||||
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
|
||||
/* Non-Blocking mode: IT */
|
||||
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
|
||||
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
|
||||
|
||||
/* Callback in non blocking modes (DMA) */
|
||||
void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
|
||||
* @{
|
||||
*/
|
||||
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
|
||||
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
|
||||
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
|
||||
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
|
||||
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
|
||||
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Types MMC Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Defines MMC Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Variables MMC Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Constants MMC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Macros MMC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Functions MMC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_MMC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_nand.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of NAND HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -94,7 +94,7 @@ typedef struct
|
|||
{
|
||||
uint16_t Page; /*!< NAND memory Page address */
|
||||
|
||||
uint16_t Zone; /*!< NAND memory Zone address */
|
||||
uint16_t Plane; /*!< NAND memory Zone address */
|
||||
|
||||
uint16_t Block; /*!< NAND memory Block address */
|
||||
|
||||
|
|
@ -105,16 +105,27 @@ typedef struct
|
|||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
|
||||
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
|
||||
for 8 bits adressing or words for 16 bits addressing */
|
||||
|
||||
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
|
||||
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
|
||||
for 8 bits adressing or words for 16 bits addressing */
|
||||
|
||||
uint32_t BlockSize; /*!< NAND memory block size number of pages */
|
||||
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
|
||||
|
||||
uint32_t BlockNbr; /*!< NAND memory number of blocks */
|
||||
uint32_t BlockNbr; /*!< NAND memory number of total blocks */
|
||||
|
||||
uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
|
||||
}NAND_InfoTypeDef;
|
||||
uint32_t PlaneNbr; /*!< NAND memory number of planes */
|
||||
|
||||
uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
|
||||
|
||||
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
|
||||
parameter is mandatory for some NAND parts after the read
|
||||
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
|
||||
Example: Toshiba THTH58BYG3S0HBAI6.
|
||||
This parameter could be ENABLE or DISABLE
|
||||
Please check the Read Mode sequnece in the NAND device datasheet */
|
||||
}NAND_DeviceConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND handle Structure definition
|
||||
|
|
@ -129,7 +140,8 @@ typedef struct
|
|||
|
||||
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
|
||||
|
||||
NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
|
||||
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
|
||||
|
||||
}NAND_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -163,6 +175,11 @@ typedef struct
|
|||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
|
||||
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
|
||||
|
||||
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
|
||||
|
|
@ -177,19 +194,21 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
|
|||
*/
|
||||
|
||||
/* IO operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
|
||||
|
||||
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
|
||||
/**
|
||||
|
|
@ -271,7 +290,9 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
|
|||
* @retval NAND Raw address value
|
||||
*/
|
||||
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
|
||||
(((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
|
||||
(((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
|
||||
|
||||
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
|
||||
|
||||
/**
|
||||
* @brief NAND memory address cycling.
|
||||
|
|
@ -282,6 +303,15 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
|
|||
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
|
||||
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
|
||||
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
|
||||
|
||||
/**
|
||||
* @brief NAND memory Columns cycling.
|
||||
* @param __ADDRESS__: NAND memory address.
|
||||
* @retval NAND Column address cycling value.
|
||||
*/
|
||||
#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
|
||||
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_nor.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of NOR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_pcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -91,8 +91,8 @@ typedef struct
|
|||
{
|
||||
PCD_TypeDef *Instance; /*!< Register base address */
|
||||
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||
PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
|
||||
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
|
||||
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||
|
|
@ -100,6 +100,9 @@ typedef struct
|
|||
uint32_t BESL;
|
||||
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
void *pData; /*!< Pointer to upper stack Handler */
|
||||
} PCD_HandleTypeDef;
|
||||
|
||||
|
|
@ -130,6 +133,7 @@ typedef struct
|
|||
*/
|
||||
#define PCD_PHY_ULPI 1U
|
||||
#define PCD_PHY_EMBEDDED 2U
|
||||
#define PCD_PHY_UTMI 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_pcd_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -60,6 +60,17 @@ typedef enum
|
|||
PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */
|
||||
}PCD_LPM_MsgTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PCD_BCD_ERROR = 0xFF,
|
||||
PCD_BCD_CONTACT_DETECTION = 0xFE,
|
||||
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
|
||||
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
|
||||
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
|
||||
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
|
||||
|
||||
}PCD_BCD_MsgTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
|
@ -73,7 +84,11 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
|
|||
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
|
||||
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of PWR HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_qspi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of QSPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -119,11 +119,11 @@ typedef struct
|
|||
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
|
||||
QSPI_InitTypeDef Init; /* QSPI communication parameters */
|
||||
uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
|
||||
__IO uint16_t TxXferSize; /* QSPI Tx Transfer size */
|
||||
__IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */
|
||||
__IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
|
||||
__IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
|
||||
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
|
||||
__IO uint16_t RxXferSize; /* QSPI Rx Transfer size */
|
||||
__IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */
|
||||
__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
|
||||
__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
|
||||
DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
|
||||
__IO HAL_LockTypeDef Lock; /* Locking object */
|
||||
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of RCC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_rng.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of RNG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of RTC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -202,8 +202,8 @@ typedef struct
|
|||
/** @defgroup RTC_Hour_Formats RTC Hour Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U)
|
||||
#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040U)
|
||||
#define RTC_HOURFORMAT_24 0x00000000U
|
||||
#define RTC_HOURFORMAT_12 0x00000040U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -212,8 +212,8 @@ typedef struct
|
|||
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U)
|
||||
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000U)
|
||||
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
|
||||
#define RTC_OUTPUT_POLARITY_LOW 0x00100000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -221,8 +221,8 @@ typedef struct
|
|||
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)
|
||||
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMTYPE) /* 0x00000008 */
|
||||
#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
|
||||
#define RTC_OUTPUT_TYPE_PUSHPULL RTC_OR_ALARMTYPE /* 0x00000008 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -239,9 +239,9 @@ typedef struct
|
|||
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000U)
|
||||
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000U)
|
||||
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U)
|
||||
#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U
|
||||
#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U
|
||||
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -249,8 +249,8 @@ typedef struct
|
|||
/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U)
|
||||
#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000U)
|
||||
#define RTC_STOREOPERATION_RESET 0x00000000U
|
||||
#define RTC_STOREOPERATION_SET 0x00040000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -258,8 +258,8 @@ typedef struct
|
|||
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FORMAT_BIN ((uint32_t)0x00000000U)
|
||||
#define RTC_FORMAT_BCD ((uint32_t)0x00000001U)
|
||||
#define RTC_FORMAT_BIN 0x00000000U
|
||||
#define RTC_FORMAT_BCD 0x00000001U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -301,8 +301,8 @@ typedef struct
|
|||
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000U)
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -310,12 +310,12 @@ typedef struct
|
|||
/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U)
|
||||
#define RTC_ALARMMASK_NONE 0x00000000U
|
||||
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
|
||||
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
|
||||
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
|
||||
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
|
||||
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080U)
|
||||
#define RTC_ALARMMASK_ALL 0x80808080U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -332,38 +332,38 @@ typedef struct
|
|||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U) /*!< All Alarm SS fields are masked.
|
||||
#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
|
||||
There is no comparison on sub seconds
|
||||
for Alarm */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000U) /*!< SS[14:1] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm
|
||||
comparison. Only SS[0] is compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000U) /*!< SS[14:2] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm
|
||||
comparison. Only SS[1:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000U) /*!< SS[14:3] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm
|
||||
comparison. Only SS[2:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000U) /*!< SS[14:4] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm
|
||||
comparison. Only SS[3:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000U) /*!< SS[14:5] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm
|
||||
comparison. Only SS[4:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000U) /*!< SS[14:6] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm
|
||||
comparison. Only SS[5:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000U) /*!< SS[14:7] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm
|
||||
comparison. Only SS[6:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000U) /*!< SS[14:8] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm
|
||||
comparison. Only SS[7:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000U) /*!< SS[14:9] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm
|
||||
comparison. Only SS[8:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000U) /*!< SS[14:10] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm
|
||||
comparison. Only SS[9:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000U) /*!< SS[14:11] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm
|
||||
comparison. Only SS[10:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000U) /*!< SS[14:12] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm
|
||||
comparison.Only SS[11:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000U) /*!< SS[14:13] are don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm
|
||||
comparison. Only SS[12:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000U) /*!< SS[14] is don't care in Alarm
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm
|
||||
comparison.Only SS[13:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000U) /*!< SS[14:0] are compared and must match
|
||||
#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match
|
||||
to activate alarm. */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -372,14 +372,14 @@ typedef struct
|
|||
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE)
|
||||
#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)
|
||||
#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)
|
||||
#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)
|
||||
#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */
|
||||
#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)
|
||||
#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)
|
||||
#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)
|
||||
#define RTC_IT_TS RTC_CR_TSIE
|
||||
#define RTC_IT_WUT RTC_CR_WUTIE
|
||||
#define RTC_IT_ALRA RTC_CR_ALRAIE
|
||||
#define RTC_IT_ALRB RTC_CR_ALRBIE
|
||||
#define RTC_IT_TAMP RTC_TAMPCR_TAMPIE /* Used only to Enable the Tamper Interrupt */
|
||||
#define RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE
|
||||
#define RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE
|
||||
#define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -387,23 +387,23 @@ typedef struct
|
|||
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
|
||||
#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)
|
||||
#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
|
||||
#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
|
||||
#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
|
||||
#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
|
||||
#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
|
||||
#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
|
||||
#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
|
||||
#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
|
||||
#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
|
||||
#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
|
||||
#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
|
||||
#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)
|
||||
#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)
|
||||
#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)
|
||||
#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)
|
||||
#define RTC_FLAG_RECALPF RTC_ISR_RECALPF
|
||||
#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F
|
||||
#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
|
||||
#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
|
||||
#define RTC_FLAG_TSOVF RTC_ISR_TSOVF
|
||||
#define RTC_FLAG_TSF RTC_ISR_TSF
|
||||
#define RTC_FLAG_ITSF RTC_ISR_ITSF
|
||||
#define RTC_FLAG_WUTF RTC_ISR_WUTF
|
||||
#define RTC_FLAG_ALRBF RTC_ISR_ALRBF
|
||||
#define RTC_FLAG_ALRAF RTC_ISR_ALRAF
|
||||
#define RTC_FLAG_INITF RTC_ISR_INITF
|
||||
#define RTC_FLAG_RSF RTC_ISR_RSF
|
||||
#define RTC_FLAG_INITS RTC_ISR_INITS
|
||||
#define RTC_FLAG_SHPF RTC_ISR_SHPF
|
||||
#define RTC_FLAG_WUTWF RTC_ISR_WUTWF
|
||||
#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF
|
||||
#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -430,9 +430,9 @@ typedef struct
|
|||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xCA; \
|
||||
(__HANDLE__)->Instance->WPR = 0x53; \
|
||||
} while(0)
|
||||
(__HANDLE__)->Instance->WPR = 0xCAU; \
|
||||
(__HANDLE__)->Instance->WPR = 0x53U; \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection for RTC registers.
|
||||
|
|
@ -441,8 +441,8 @@ typedef struct
|
|||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xFF; \
|
||||
} while(0)
|
||||
(__HANDLE__)->Instance->WPR = 0xFFU; \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMA peripheral.
|
||||
|
|
@ -503,7 +503,7 @@ typedef struct
|
|||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) & 0x0000FFFFU) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Alarm's flag status.
|
||||
|
|
@ -527,7 +527,7 @@ typedef struct
|
|||
* @arg RTC_FLAG_ALRBF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFFU)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
|
||||
|
|
@ -697,14 +697,14 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
|||
* @{
|
||||
*/
|
||||
/* Masks Definition */
|
||||
#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7FU)
|
||||
#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3FU)
|
||||
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
|
||||
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
|
||||
#define RTC_TR_RESERVED_MASK 0x007F7F7FU
|
||||
#define RTC_DR_RESERVED_MASK 0x00FFFF3FU
|
||||
#define RTC_INIT_MASK 0xFFFFFFFFU
|
||||
#define RTC_RSF_MASK 0xFFFFFF5FU
|
||||
|
||||
#define RTC_TIMEOUT_VALUE 1000
|
||||
#define RTC_TIMEOUT_VALUE 1000U
|
||||
|
||||
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_IM17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -723,12 +723,12 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
|||
((__POL__) == RTC_OUTPUT_POLARITY_LOW))
|
||||
#define IS_RTC_OUTPUT_TYPE(__TYPE__) (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
|
||||
((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL))
|
||||
#define IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7F)
|
||||
#define IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7FFF)
|
||||
#define IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > (uint32_t)0) && ((__HOUR__) <= (uint32_t)12))
|
||||
#define IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= (uint32_t)23)
|
||||
#define IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= (uint32_t)59)
|
||||
#define IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= (uint32_t)59)
|
||||
#define IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= 0x7FU)
|
||||
#define IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= 0x7FFFU)
|
||||
#define IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
|
||||
#define IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
|
||||
#define IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
|
||||
#define IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
|
||||
#define IS_RTC_HOURFORMAT12(__PM__) (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM))
|
||||
#define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \
|
||||
((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \
|
||||
|
|
@ -736,9 +736,9 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
|||
#define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || \
|
||||
((__OPERATION__) == RTC_STOREOPERATION_SET))
|
||||
#define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD))
|
||||
#define IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= (uint32_t)99)
|
||||
#define IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= (uint32_t)1) && ((__MONTH__) <= (uint32_t)12))
|
||||
#define IS_RTC_DATE(__DATE__) (((__DATE__) >= (uint32_t)1) && ((__DATE__) <= (uint32_t)31))
|
||||
#define IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
|
||||
#define IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
|
||||
#define IS_RTC_DATE(__DATE__) (((__DATE__) >= 1U) && ((__DATE__) <= 31U))
|
||||
#define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
|
|
@ -747,7 +747,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
|||
((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >(uint32_t) 0) && ((__DATE__) <= (uint32_t)31))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >0U) && ((__DATE__) <= 31U))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
|
|
@ -757,9 +757,9 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
|||
((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
|
||||
((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
|
||||
#define IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & 0x7F7F7F7F) == (uint32_t)RESET)
|
||||
#define IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & 0x7F7F7F7FU) == (uint32_t)RESET)
|
||||
#define IS_RTC_ALARM(__ALARM__) (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B))
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)0x00007FFF)
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= 0x00007FFFU)
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__) (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_rtc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of RTC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_sai.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of SAI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_sai_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of SAI Extension HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_sd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of SD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -60,46 +60,114 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition
|
||||
/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */
|
||||
HAL_SD_STATE_READY = ((uint32_t)0x00000001U), /*!< SD initialized and ready for use */
|
||||
HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< SD Timeout state */
|
||||
HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */
|
||||
HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */
|
||||
HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receinving State */
|
||||
HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */
|
||||
HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */
|
||||
}HAL_SD_StateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
|
||||
HAL_SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
|
||||
HAL_SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
|
||||
HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
|
||||
HAL_SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
|
||||
HAL_SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
|
||||
HAL_SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
|
||||
HAL_SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
|
||||
HAL_SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
|
||||
}HAL_SD_CardStateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define SD_InitTypeDef SDMMC_InitTypeDef
|
||||
#define SD_TypeDef SDMMC_TypeDef
|
||||
|
||||
/**
|
||||
* @brief SD Card Information Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
SD_TypeDef *Instance; /*!< SDMMC register base address */
|
||||
uint32_t CardType; /*!< Specifies the card Type */
|
||||
|
||||
uint32_t CardVersion; /*!< Specifies the card version */
|
||||
|
||||
uint32_t Class; /*!< Specifies the class of the card class */
|
||||
|
||||
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
|
||||
|
||||
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
|
||||
|
||||
uint32_t BlockSize; /*!< Specifies one block size in bytes */
|
||||
|
||||
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
|
||||
|
||||
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
|
||||
|
||||
}HAL_SD_CardInfoTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SD handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
SD_TypeDef *Instance; /*!< SD registers base address */
|
||||
|
||||
SD_InitTypeDef Init; /*!< SD required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SD locking object */
|
||||
|
||||
uint32_t CardType; /*!< SD card type */
|
||||
uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
|
||||
|
||||
uint32_t RCA; /*!< SD relative card address */
|
||||
uint32_t TxXferSize; /*!< SD Tx Transfer size */
|
||||
|
||||
uint32_t CSD[4]; /*!< SD card specific data table */
|
||||
uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
|
||||
|
||||
uint32_t CID[4]; /*!< SD card identification number table */
|
||||
uint32_t RxXferSize; /*!< SD Rx Transfer size */
|
||||
|
||||
__IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */
|
||||
__IO uint32_t Context; /*!< SD transfer context */
|
||||
|
||||
__IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */
|
||||
__IO HAL_SD_StateTypeDef State; /*!< SD card State */
|
||||
|
||||
__IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */
|
||||
|
||||
__IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */
|
||||
__IO uint32_t ErrorCode; /*!< SD Card Error codes */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
|
||||
|
||||
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
|
||||
|
||||
uint32_t CSD[4]; /*!< SD card specific data table */
|
||||
|
||||
uint32_t CID[4]; /*!< SD card identification number table */
|
||||
|
||||
}SD_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register
|
||||
/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
|
|
@ -142,12 +210,12 @@ typedef struct
|
|||
__IO uint8_t CSD_CRC; /*!< CSD CRC */
|
||||
__IO uint8_t Reserved4; /*!< Always 1 */
|
||||
|
||||
}HAL_SD_CSDTypedef;
|
||||
}HAL_SD_CardCSDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
|
||||
/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
|
|
@ -163,154 +231,28 @@ typedef struct
|
|||
__IO uint8_t CID_CRC; /*!< CID CRC */
|
||||
__IO uint8_t Reserved2; /*!< Always 1 */
|
||||
|
||||
}HAL_SD_CIDTypedef;
|
||||
}HAL_SD_CardCIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13
|
||||
/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */
|
||||
__IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */
|
||||
__IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */
|
||||
__IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */
|
||||
__IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */
|
||||
__IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */
|
||||
__IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */
|
||||
__IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */
|
||||
__IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */
|
||||
__IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */
|
||||
__IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
|
||||
__IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
|
||||
__IO uint16_t CardType; /*!< Carries information about card type */
|
||||
__IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
|
||||
__IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
|
||||
__IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
|
||||
__IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
|
||||
__IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
|
||||
__IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
|
||||
__IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
|
||||
|
||||
}HAL_SD_CardStatusTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group5 SD Card information structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */
|
||||
HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */
|
||||
uint64_t CardCapacity; /*!< Card capacity */
|
||||
uint32_t CardBlockSize; /*!< Card block size */
|
||||
uint16_t RCA; /*!< SD relative card address */
|
||||
uint8_t CardType; /*!< SD card type */
|
||||
|
||||
}HAL_SD_CardInfoTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/**
|
||||
* @brief SD specific error defines
|
||||
*/
|
||||
SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */
|
||||
SD_DATA_CRC_FAIL = (2), /*!< Data block sent/received (CRC check failed) */
|
||||
SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */
|
||||
SD_DATA_TIMEOUT = (4), /*!< Data timeout */
|
||||
SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */
|
||||
SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */
|
||||
SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */
|
||||
SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */
|
||||
SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */
|
||||
SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
|
||||
SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs. */
|
||||
SD_BAD_ERASE_PARAM = (12), /*!< An invalid selection for erase groups */
|
||||
SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */
|
||||
SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
|
||||
SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */
|
||||
SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */
|
||||
SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */
|
||||
SD_CC_ERROR = (18), /*!< Internal card controller error */
|
||||
SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or unknown error */
|
||||
SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */
|
||||
SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */
|
||||
SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */
|
||||
SD_WP_ERASE_SKIP = (23), /*!< Only partial address space was erased */
|
||||
SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */
|
||||
SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
|
||||
SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */
|
||||
SD_INVALID_VOLTRANGE = (27),
|
||||
SD_ADDR_OUT_OF_RANGE = (28),
|
||||
SD_SWITCH_ERROR = (29),
|
||||
SD_SDMMC_DISABLED = (30),
|
||||
SD_SDMMC_FUNCTION_BUSY = (31),
|
||||
SD_SDMMC_FUNCTION_FAILED = (32),
|
||||
SD_SDMMC_UNKNOWN_FUNCTION = (33),
|
||||
|
||||
/**
|
||||
* @brief Standard error defines
|
||||
*/
|
||||
SD_INTERNAL_ERROR = (34),
|
||||
SD_NOT_CONFIGURED = (35),
|
||||
SD_REQUEST_PENDING = (36),
|
||||
SD_REQUEST_NOT_APPLICABLE = (37),
|
||||
SD_INVALID_PARAMETER = (38),
|
||||
SD_UNSUPPORTED_FEATURE = (39),
|
||||
SD_UNSUPPORTED_HW = (40),
|
||||
SD_ERROR = (41),
|
||||
SD_OK = (0)
|
||||
|
||||
}HAL_SD_ErrorTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SD_TRANSFER_OK = 0, /*!< Transfer success */
|
||||
SD_TRANSFER_BUSY = 1, /*!< Transfer is occurring */
|
||||
SD_TRANSFER_ERROR = 2 /*!< Transfer failed */
|
||||
|
||||
}HAL_SD_TransferStateTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
|
||||
SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
|
||||
SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
|
||||
SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
|
||||
SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
|
||||
SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
|
||||
SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
|
||||
SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
|
||||
SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card is in error state */
|
||||
|
||||
}HAL_SD_CardStateTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SD_READ_SINGLE_BLOCK = 0U, /*!< Read single block operation */
|
||||
SD_READ_MULTIPLE_BLOCK = 1U, /*!< Read multiple blocks operation */
|
||||
SD_WRITE_SINGLE_BLOCK = 2U, /*!< Write single block operation */
|
||||
SD_WRITE_MULTIPLE_BLOCK = 3U /*!< Write multiple blocks operation */
|
||||
|
||||
}HAL_SD_OperationTypedef;
|
||||
}HAL_SD_CardStatusTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -320,109 +262,91 @@ typedef enum
|
|||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_Constants SD Exported Constants
|
||||
/** @defgroup SD_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SD Commands Index
|
||||
#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
|
||||
|
||||
/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define SD_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
|
||||
#define SD_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
|
||||
#define SD_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
|
||||
#define SD_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
|
||||
#define SD_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
|
||||
#define SD_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
|
||||
operating condition register (OCR) content in the response on the CMD line. */
|
||||
#define SD_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
|
||||
#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
|
||||
#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
|
||||
and asks the card whether card supports voltage. */
|
||||
#define SD_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
|
||||
#define SD_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
|
||||
#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */
|
||||
#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
|
||||
#define SD_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
|
||||
#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14U)
|
||||
#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
|
||||
#define SD_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
|
||||
(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
|
||||
for SDHS and SDXC. */
|
||||
#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
|
||||
fixed 512 bytes in case of SDHC and SDXC. */
|
||||
#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
|
||||
STOP_TRANSMISSION command. */
|
||||
#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
|
||||
#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
|
||||
#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
|
||||
#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
|
||||
fixed 512 bytes in case of SDHC and SDXC. */
|
||||
#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
|
||||
#define SD_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
|
||||
#define SD_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
|
||||
#define SD_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
|
||||
#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
|
||||
#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
|
||||
#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
|
||||
#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
|
||||
#define SD_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
|
||||
system set by switch function command (CMD6). */
|
||||
#define SD_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
|
||||
Reserved for each command system set by switch function command (CMD6). */
|
||||
#define SD_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
|
||||
#define SD_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
|
||||
#define SD_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
|
||||
#define SD_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
|
||||
the SET_BLOCK_LEN command. */
|
||||
#define SD_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
|
||||
than a standard command. */
|
||||
#define SD_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
|
||||
for general purpose/application specific commands. */
|
||||
#define SD_CMD_NO_CMD ((uint8_t)64U)
|
||||
#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
|
||||
#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
|
||||
#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
|
||||
#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
|
||||
#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
|
||||
#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
|
||||
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
|
||||
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
|
||||
#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
|
||||
number of transferred bytes does not match the block length */
|
||||
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
|
||||
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
|
||||
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
|
||||
#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
|
||||
command or if there was an attempt to access a locked card */
|
||||
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
|
||||
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
|
||||
#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
|
||||
#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
|
||||
#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
|
||||
#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
|
||||
#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
|
||||
#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
|
||||
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
|
||||
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
|
||||
#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
|
||||
of erase sequence command was received */
|
||||
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
|
||||
#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
|
||||
#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
|
||||
#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
|
||||
#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
|
||||
#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
|
||||
#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
|
||||
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
|
||||
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
|
||||
|
||||
/**
|
||||
* @brief Following commands are SD Card Specific commands.
|
||||
* SDMMC_APP_CMD should be sent before sending these commands.
|
||||
* @}
|
||||
*/
|
||||
#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
|
||||
widths are given in SCR register. */
|
||||
#define SD_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
|
||||
#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
|
||||
32bit+CRC data block. */
|
||||
#define SD_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
|
||||
send its operating condition register (OCR) content in the response on the CMD line. */
|
||||
#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
|
||||
#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
|
||||
#define SD_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
|
||||
#define SD_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
|
||||
|
||||
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
|
||||
* @{
|
||||
*/
|
||||
#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
|
||||
#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
|
||||
#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
|
||||
#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
|
||||
#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
|
||||
#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
|
||||
#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
|
||||
|
||||
/**
|
||||
* @brief Following commands are SD Card Specific security commands.
|
||||
* SD_CMD_APP_CMD should be sent before sending these commands.
|
||||
* @}
|
||||
*/
|
||||
#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_GET_MID ((uint8_t)44U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) /*!< For SD card only */
|
||||
|
||||
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
|
||||
* @{
|
||||
*/
|
||||
#define CARD_SDSC ((uint32_t)0x00000000U)
|
||||
#define CARD_SDHC_SDXC ((uint32_t)0x00000001U)
|
||||
#define CARD_SECURED ((uint32_t)0x00000003U)
|
||||
|
||||
/**
|
||||
* @brief Supported SD Memory Cards
|
||||
* @}
|
||||
*/
|
||||
#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000U)
|
||||
#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001U)
|
||||
#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002U)
|
||||
#define MULTIMEDIA_CARD ((uint32_t)0x00000003U)
|
||||
#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004U)
|
||||
#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005U)
|
||||
#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006U)
|
||||
#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007U)
|
||||
|
||||
/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
|
||||
* @{
|
||||
*/
|
||||
#define CARD_V1_X ((uint32_t)0x00000000U)
|
||||
#define CARD_V2_X ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -437,25 +361,25 @@ typedef enum
|
|||
* @brief Enable the SD device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDMMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
|
||||
#define __HAL_SD_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Disable the SD device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDMMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
|
||||
#define __HAL_SD_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Enable the SDMMC DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDMMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
|
||||
#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Disable the SDMMC DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDMMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
|
||||
#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Enable the SD device interrupt.
|
||||
|
|
@ -486,7 +410,7 @@ typedef enum
|
|||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDMMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the SD device interrupt.
|
||||
|
|
@ -517,7 +441,7 @@ typedef enum
|
|||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDMMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified SD flag is set or not.
|
||||
|
|
@ -548,7 +472,7 @@ typedef enum
|
|||
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @retval The new state of SD FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SD_SDMMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the SD's pending flags.
|
||||
|
|
@ -568,7 +492,7 @@ typedef enum
|
|||
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDMMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified SD interrupt has occurred or not.
|
||||
|
|
@ -599,7 +523,7 @@ typedef enum
|
|||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval The new state of SD IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SD_SDMMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the SD's interrupt pending bits.
|
||||
|
|
@ -618,7 +542,8 @@ typedef enum
|
|||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDMMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -631,7 +556,8 @@ typedef enum
|
|||
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
|
||||
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
|
||||
|
|
@ -643,26 +569,23 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
|
|||
* @{
|
||||
*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
|
||||
HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
|
||||
HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
|
||||
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
|
||||
/* Non-Blocking mode: IT */
|
||||
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
|
||||
|
||||
/* Callback in non blocking modes (DMA) */
|
||||
void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
|
||||
HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
|
||||
HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
|
||||
HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
|
||||
void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -670,25 +593,38 @@ HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Ti
|
|||
/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
|
||||
HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
|
||||
HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
|
||||
HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
|
||||
/** @defgroup SD_Exported_Functions_Group4 SD card related functions
|
||||
* @{
|
||||
*/
|
||||
HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
|
||||
HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
|
||||
HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
|
||||
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
|
||||
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
|
||||
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
|
||||
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
|
||||
uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -756,6 +692,7 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -764,6 +701,11 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_sdram.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of SDRAM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_smartcard.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of SMARTCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -687,9 +687,9 @@ typedef struct
|
|||
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
/** @brief Disables the specified SmartCard interrupt.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
|
|
@ -704,9 +704,9 @@ typedef struct
|
|||
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
|
||||
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
|
|
@ -724,7 +724,7 @@ typedef struct
|
|||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
|
||||
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U)))
|
||||
|
||||
/** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
|
|
@ -742,7 +742,7 @@ typedef struct
|
|||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
|
||||
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
|
||||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
|
||||
(((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
|
||||
|
||||
|
|
@ -815,10 +815,10 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -857,8 +857,8 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard
|
|||
* @{
|
||||
*/
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
|
||||
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_smartcard_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of SMARTCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
697
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smbus.h
Normal file
697
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smbus.h
Normal file
|
|
@ -0,0 +1,697 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_smbus.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of SMBUS HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_SMBUS_H
|
||||
#define __STM32F7xx_HAL_SMBUS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
|
||||
* @brief SMBUS Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
|
||||
This parameter calculated by referring to SMBUS initialization
|
||||
section in Reference manual */
|
||||
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
|
||||
This parameter can be a value of @ref SMBUS_Analog_Filter */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
|
||||
This parameter can be a value of @ref SMBUS_addressing_mode */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_dual_addressing_mode */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref SMBUS_own_address2_masks. */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_nostretch_mode */
|
||||
|
||||
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_packet_error_check_mode */
|
||||
|
||||
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
|
||||
This parameter can be a value of @ref SMBUS_peripheral_mode */
|
||||
|
||||
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
|
||||
(Enable bits and different timeout values)
|
||||
This parameter calculated by referring to SMBUS initialization
|
||||
section in Reference manual */
|
||||
} SMBUS_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_definition HAL state definition
|
||||
* @brief HAL State definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
|
||||
#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
|
||||
#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
|
||||
#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
|
||||
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
|
||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
|
||||
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
|
||||
* @brief SMBUS Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
|
||||
#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
|
||||
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
|
||||
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
|
||||
* @brief SMBUS handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
|
||||
|
||||
SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< SMBUS transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< SMBUS transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< SMBUS transfer options */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
|
||||
|
||||
__IO uint32_t State; /*!< SMBUS communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
|
||||
|
||||
}SMBUS_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
|
||||
#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_PEC_DISABLE (0x00000000U)
|
||||
#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
|
||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
|
||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_SOFTEND_MODE (0x00000000U)
|
||||
#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_NO_STARTSTOP (0x00000000U)
|
||||
#define SMBUS_GENERATE_STOP I2C_CR2_STOP
|
||||
#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define SMBUS_GENERATE_START_WRITE I2C_CR2_START
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition when direction change
|
||||
* 2- No Restart condition in other use cases
|
||||
*/
|
||||
#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
|
||||
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
|
||||
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
||||
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
||||
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
|
||||
#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
|
||||
#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
|
||||
#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
|
||||
* @brief SMBUS Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_IT_ERRI I2C_CR1_ERRIE
|
||||
#define SMBUS_IT_TCI I2C_CR1_TCIE
|
||||
#define SMBUS_IT_STOPI I2C_CR1_STOPIE
|
||||
#define SMBUS_IT_NACKI I2C_CR1_NACKIE
|
||||
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define SMBUS_IT_RXI I2C_CR1_RXIE
|
||||
#define SMBUS_IT_TXI I2C_CR1_TXIE
|
||||
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
|
||||
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
|
||||
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
|
||||
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
|
||||
* @brief Flag definition
|
||||
* Elements values convention: 0xXXXXYYYY
|
||||
* - XXXXXXXX : Flag mask
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_FLAG_TXE I2C_ISR_TXE
|
||||
#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define SMBUS_FLAG_AF I2C_ISR_NACKF
|
||||
#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define SMBUS_FLAG_TC I2C_ISR_TC
|
||||
#define SMBUS_FLAG_TCR I2C_ISR_TCR
|
||||
#define SMBUS_FLAG_BERR I2C_ISR_BERR
|
||||
#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define SMBUS_FLAG_OVR I2C_ISR_OVR
|
||||
#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define SMBUS_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SMBUS handle state.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
|
||||
|
||||
/** @brief Enable the specified SMBUS interrupts.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
||||
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified SMBUS interrupts.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
||||
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
||||
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SMBUS flag is set or not.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMBUS_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref SMBUS_FLAG_AF NACK received flag
|
||||
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref SMBUS_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref SMBUS_FLAG_BERR Bus error
|
||||
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
|
||||
* @arg @ref SMBUS_FLAG_BUSY Bus busy
|
||||
* @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define SMBUS_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
|
||||
|
||||
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref SMBUS_FLAG_AF NACK received flag
|
||||
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref SMBUS_FLAG_BERR Bus error
|
||||
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/** @brief Enable the specified SMBUS peripheral.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified SMBUS peripheral.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
|
||||
((MASK) == SMBUS_OA2_MASK01) || \
|
||||
((MASK) == SMBUS_OA2_MASK02) || \
|
||||
((MASK) == SMBUS_OA2_MASK03) || \
|
||||
((MASK) == SMBUS_OA2_MASK04) || \
|
||||
((MASK) == SMBUS_OA2_MASK05) || \
|
||||
((MASK) == SMBUS_OA2_MASK06) || \
|
||||
((MASK) == SMBUS_OA2_MASK07))
|
||||
|
||||
#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
|
||||
((CALL) == SMBUS_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
|
||||
((PEC) == SMBUS_PEC_ENABLE))
|
||||
|
||||
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
|
||||
|
||||
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
|
||||
((MODE) == SMBUS_AUTOEND_MODE) || \
|
||||
((MODE) == SMBUS_SOFTEND_MODE) || \
|
||||
((MODE) == SMBUS_SENDPEC_MODE) || \
|
||||
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
|
||||
|
||||
|
||||
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_READ) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == SMBUS_NO_STARTSTOP))
|
||||
|
||||
|
||||
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
|
||||
((REQUEST) == SMBUS_NEXT_FRAME) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \
|
||||
IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
|
||||
|
||||
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
|
||||
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
|
||||
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
|
||||
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
|
||||
#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
|
||||
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
|
||||
|
||||
#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
|
||||
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
|
||||
|
||||
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
|
||||
* @{
|
||||
*/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
|
||||
* @{
|
||||
*/
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
|
||||
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
|
||||
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Errors functions **************************************************/
|
||||
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
|
||||
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f7xx_hal_smbus.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_SMBUS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_spdifrx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of SPDIFRX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -43,11 +43,11 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (SPDIFRX)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (SPDIFRX)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of SPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_sram.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of SRAM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_tim.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of TIM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -85,6 +85,10 @@ typedef struct
|
|||
- the number of half PWM period in center-aligned mode
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
|
||||
@note This parameter is valid only for TIM1 and TIM8. */
|
||||
|
||||
uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
|
||||
This parameter can be a value of @ref TIM_AutoReloadPreload */
|
||||
|
||||
} TIM_Base_InitTypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -363,6 +367,16 @@ typedef struct
|
|||
#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U)
|
||||
#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
|
||||
* @{
|
||||
*/
|
||||
#define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /*!< TIMx_ARR register is not buffered */
|
||||
#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1285,6 +1299,9 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
|
|||
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
|
||||
((__DIV__) == TIM_CLOCKDIVISION_DIV4))
|
||||
|
||||
#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
|
||||
((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
|
||||
|
||||
#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
|
||||
((__STATE__) == TIM_OCFAST_ENABLE))
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_tim_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of TIM HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -201,7 +201,6 @@ typedef struct {
|
|||
* @{
|
||||
*/
|
||||
#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U)
|
||||
#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002U)
|
||||
#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U)
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -356,6 +355,48 @@ typedef struct {
|
|||
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
|
||||
((__HANDLE__)->Instance->CCR6))
|
||||
|
||||
/**
|
||||
* @brief Sets the TIM Output compare preload.
|
||||
* @param __HANDLE__: TIM handle.
|
||||
* @param __CHANNEL__: TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
||||
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
|
||||
((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM Output compare preload.
|
||||
* @param __HANDLE__: TIM handle.
|
||||
* @param __CHANNEL__: TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
||||
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
|
||||
((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -536,7 +577,6 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
|
|||
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
|
||||
#define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)
|
||||
#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
|
||||
((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
|
||||
((MODE) == TIM_CLEARINPUTSOURCE_NONE))
|
||||
#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
|
||||
((STATE) == TIM_BREAK2_DISABLE))
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_uart.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of UART HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_uart_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of UART HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_usart.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of USART HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_usart_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of USART HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of WWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
4767
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h
Normal file
4767
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h
Normal file
File diff suppressed because it is too large
Load diff
1994
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h
Normal file
1994
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h
Normal file
File diff suppressed because it is too large
Load diff
657
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h
Normal file
657
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h
Normal file
|
|
@ -0,0 +1,657 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of CORTEX LL module.
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The LL CORTEX driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
|
||||
functions
|
||||
(+) Low power mode configuration (SCB register of Cortex-MCU)
|
||||
(+) MPU API to configure and enable regions
|
||||
(+) API to access to MCU info (CPUID register)
|
||||
(+) API to enable fault handler (SHCSR accesses)
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_CORTEX_H
|
||||
#define __STM32F7xx_LL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL CORTEX
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
|
||||
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
|
||||
* @{
|
||||
*/
|
||||
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
|
||||
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
|
||||
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if __MPU_PRESENT
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
|
||||
#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
|
||||
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
|
||||
#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
|
||||
#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
|
||||
#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
|
||||
#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
|
||||
#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
|
||||
#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
|
||||
#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
|
||||
#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
|
||||
#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
|
||||
#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
|
||||
#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
|
||||
#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
|
||||
#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
|
||||
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
|
||||
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
|
||||
#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
|
||||
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
|
||||
#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
|
||||
#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
|
||||
#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function checks if the Systick counter flag is active or not.
|
||||
* @note It can be used in timeout function on application side.
|
||||
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
|
||||
{
|
||||
return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source
|
||||
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
|
||||
* @param Source This parameter can be one of the following values:
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
|
||||
{
|
||||
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the SysTick clock source
|
||||
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
|
||||
{
|
||||
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable SysTick exception request
|
||||
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
|
||||
{
|
||||
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SysTick exception request
|
||||
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
|
||||
{
|
||||
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
|
||||
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
|
||||
{
|
||||
return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Processor uses sleep as its low power mode
|
||||
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableSleep(void)
|
||||
{
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Processor uses deep sleep as its low power mode
|
||||
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
|
||||
{
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
|
||||
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
|
||||
* empty main application.
|
||||
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Do not sleep when returning to Thread mode.
|
||||
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
|
||||
* processor.
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
|
||||
{
|
||||
/* Set SEVEONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
|
||||
* excluded
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
|
||||
{
|
||||
/* Clear SEVEONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable a fault in System handler control register (SHCSR)
|
||||
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
|
||||
* @param Fault This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_HANDLER_FAULT_USG
|
||||
* @arg @ref LL_HANDLER_FAULT_BUS
|
||||
* @arg @ref LL_HANDLER_FAULT_MEM
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
|
||||
{
|
||||
/* Enable the system handler fault */
|
||||
SET_BIT(SCB->SHCSR, Fault);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a fault in System handler control register (SHCSR)
|
||||
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
|
||||
* @param Fault This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_HANDLER_FAULT_USG
|
||||
* @arg @ref LL_HANDLER_FAULT_BUS
|
||||
* @arg @ref LL_HANDLER_FAULT_MEM
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
|
||||
{
|
||||
/* Disable the system handler fault */
|
||||
CLEAR_BIT(SCB->SHCSR, Fault);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Implementer code
|
||||
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
|
||||
* @retval Value should be equal to 0x41 for ARM
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Variant number (The r value in the rnpn product revision identifier)
|
||||
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
|
||||
* @retval Value between 0 and 255 (0x0: revision 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Constant number
|
||||
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
|
||||
* @retval Value should be equal to 0xF for Cortex-M7 devices
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Part number
|
||||
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
|
||||
* @retval Value should be equal to 0xC27 for Cortex-M7
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
|
||||
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
|
||||
* @retval Value between 0 and 255 (0x1: patch 1)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if __MPU_PRESENT
|
||||
/** @defgroup CORTEX_LL_EF_MPU MPU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable MPU with input options
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
|
||||
* @param Options This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
|
||||
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
|
||||
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
|
||||
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
|
||||
{
|
||||
/* Enable the MPU*/
|
||||
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
|
||||
/* Ensure MPU settings take effects */
|
||||
__DSB();
|
||||
/* Sequence instruction fetches using update settings */
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable MPU
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_Disable(void)
|
||||
{
|
||||
/* Make sure outstanding transfers are done */
|
||||
__DMB();
|
||||
/* Disable MPU*/
|
||||
WRITE_REG(MPU->CTRL, 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if MPU is enabled or not
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
|
||||
{
|
||||
return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable a MPU region
|
||||
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Enable the MPU region */
|
||||
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure and enable a region
|
||||
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
|
||||
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
|
||||
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR XN LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR AP LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR S LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR C LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR B LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR SIZE LL_MPU_ConfigRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @param Address Value of region base address
|
||||
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
|
||||
* @param Attributes This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
|
||||
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
|
||||
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
|
||||
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
|
||||
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
|
||||
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
|
||||
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
|
||||
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
|
||||
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
|
||||
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
|
||||
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
|
||||
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
|
||||
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Set base address */
|
||||
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
|
||||
/* Configure MPU */
|
||||
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a region
|
||||
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
|
||||
* MPU_RASR ENABLE LL_MPU_DisableRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Disable the MPU region */
|
||||
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_CORTEX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
479
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_crc.h
Normal file
479
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_crc.h
Normal file
|
|
@ -0,0 +1,479 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of CRC LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_CRC_H
|
||||
#define __STM32F7xx_LL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CRC)
|
||||
|
||||
/** @defgroup CRC_LL CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */
|
||||
#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */
|
||||
#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */
|
||||
#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */
|
||||
#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */
|
||||
#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */
|
||||
#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */
|
||||
#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
|
||||
* @brief Normal representation of this polynomial value is
|
||||
* X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in CRC register
|
||||
* @param __INSTANCE__ CRC Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in CRC register
|
||||
* @param __INSTANCE__ CRC Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reset the CRC calculation unit.
|
||||
* @note If Programmable Initial CRC value feature
|
||||
* is available, also set the Data Register to the value stored in the
|
||||
* CRC_INIT register, otherwise, reset Data Register to its default value.
|
||||
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
|
||||
* @param CRCx CRC Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
|
||||
{
|
||||
SET_BIT(CRCx->CR, CRC_CR_RESET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure size of the polynomial.
|
||||
* @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
|
||||
* @param CRCx CRC Instance
|
||||
* @param PolySize This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRC_POLYLENGTH_32B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_16B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_8B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_7B
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return size of the polynomial.
|
||||
* @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRC_POLYLENGTH_32B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_16B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_8B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_7B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the reversal of the bit order of the input data
|
||||
* @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode
|
||||
* @param CRCx CRC Instance
|
||||
* @param ReverseMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return type of reversal for input data bit order
|
||||
* @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the reversal of the bit order of the Output data
|
||||
* @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode
|
||||
* @param CRCx CRC Instance
|
||||
* @param ReverseMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the reversal of the bit order of the Output data
|
||||
* @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the Programmable initial CRC value.
|
||||
* @note If the CRC size is less than 32 bits, the least significant bits
|
||||
* are used to write the correct value
|
||||
* @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
|
||||
* @rmtoll INIT INIT LL_CRC_SetInitialData
|
||||
* @param CRCx CRC Instance
|
||||
* @param InitCrc Value to be programmed in Programmable initial CRC value register
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
|
||||
{
|
||||
WRITE_REG(CRCx->INIT, InitCrc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Initial CRC value.
|
||||
* @note If the CRC size is less than 32 bits, the least significant bits
|
||||
* are used to read the correct value
|
||||
* @rmtoll INIT INIT LL_CRC_GetInitialData
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value programmed in Programmable initial CRC value register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->INIT));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the Programmable polynomial value
|
||||
* (coefficients of the polynomial to be used for CRC calculation).
|
||||
* @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
|
||||
* @note Please check Reference Manual and existing Errata Sheets,
|
||||
* regarding possible limitations for Polynomial values usage.
|
||||
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
|
||||
* @rmtoll POL POL LL_CRC_SetPolynomialCoef
|
||||
* @param CRCx CRC Instance
|
||||
* @param PolynomCoef Value to be programmed in Programmable Polynomial value register
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
|
||||
{
|
||||
WRITE_REG(CRCx->POL, PolynomCoef);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Programmable polynomial value
|
||||
* @note Please check Reference Manual and existing Errata Sheets,
|
||||
* regarding possible limitations for Polynomial values usage.
|
||||
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
|
||||
* @rmtoll POL POL LL_CRC_GetPolynomialCoef
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value programmed in Programmable Polynomial value register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->POL));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EF_Data_Management Data_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write given 32-bit data to the CRC calculator
|
||||
* @rmtoll DR DR LL_CRC_FeedData32
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
{
|
||||
WRITE_REG(CRCx->DR, InData);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write given 16-bit data to the CRC calculator
|
||||
* @rmtoll DR DR LL_CRC_FeedData16
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
|
||||
{
|
||||
*(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write given 8-bit data to the CRC calculator
|
||||
* @rmtoll DR DR LL_CRC_FeedData8
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
|
||||
{
|
||||
*(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 32 bits value is returned.
|
||||
* @rmtoll DR DR LL_CRC_ReadData32
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->DR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 16 bits value is returned.
|
||||
* @note This function is expected to be used in a 16 bits CRC polynomial size context.
|
||||
* @rmtoll DR DR LL_CRC_ReadData16
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint16_t)READ_REG(CRCx->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 8 bits value is returned.
|
||||
* @note This function is expected to be used in a 8 bits CRC polynomial size context.
|
||||
* @rmtoll DR DR LL_CRC_ReadData8
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint8_t)READ_REG(CRCx->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 7 bits value is returned.
|
||||
* @note This function is expected to be used in a 7 bits CRC polynomial size context.
|
||||
* @rmtoll DR DR LL_CRC_ReadData7
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return data stored in the Independent Data(IDR) register.
|
||||
* @note This register can be used as a temporary storage location for one byte.
|
||||
* @rmtoll IDR IDR LL_CRC_Read_IDR
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->IDR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data(IDR) register.
|
||||
* @note This register can be used as a temporary storage location for one byte.
|
||||
* @rmtoll IDR IDR LL_CRC_Write_IDR
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
{
|
||||
*((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(CRC) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_CRC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
1316
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dac.h
Normal file
1316
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dac.h
Normal file
File diff suppressed because it is too large
Load diff
2911
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h
Normal file
2911
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h
Normal file
File diff suppressed because it is too large
Load diff
2070
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma2d.h
Normal file
2070
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma2d.h
Normal file
File diff suppressed because it is too large
Load diff
968
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h
Normal file
968
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h
Normal file
|
|
@ -0,0 +1,968 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of EXTI LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_EXTI_H
|
||||
#define __STM32F7xx_LL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (EXTI)
|
||||
|
||||
/** @defgroup EXTI_LL EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private Macros ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
|
||||
This parameter can be any combination of @ref EXTI_LL_EC_LINE */
|
||||
|
||||
FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
|
||||
uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTI_LL_EC_MODE. */
|
||||
|
||||
uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
|
||||
} LL_EXTI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EC_LINE LINE
|
||||
* @{
|
||||
*/
|
||||
#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
|
||||
#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
|
||||
#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
|
||||
#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
|
||||
#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
|
||||
#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
|
||||
#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
|
||||
#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
|
||||
#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
|
||||
#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
|
||||
#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
|
||||
#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
|
||||
#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
|
||||
#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
|
||||
#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
|
||||
#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
|
||||
#if defined(EXTI_IMR_IM16)
|
||||
#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
|
||||
#endif
|
||||
#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
|
||||
#if defined(EXTI_IMR_IM18)
|
||||
#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
|
||||
#endif
|
||||
#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
|
||||
#if defined(EXTI_IMR_IM20)
|
||||
#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM21)
|
||||
#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM22)
|
||||
#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
|
||||
#endif
|
||||
#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
|
||||
#if defined(EXTI_IMR_IM24)
|
||||
#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM25)
|
||||
#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM26)
|
||||
#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM27)
|
||||
#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM28)
|
||||
#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM29)
|
||||
#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM30)
|
||||
#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM31)
|
||||
#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
|
||||
#endif
|
||||
#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
|
||||
|
||||
|
||||
#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/** @defgroup EXTI_LL_EC_MODE Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
|
||||
#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
|
||||
#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
|
||||
* @{
|
||||
*/
|
||||
#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
|
||||
#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
|
||||
#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
|
||||
#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in EXTI register
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in EXTI register
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup EXTI_LL_EF_IT_Management IT_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
|
||||
* @note The reset value for the direct or internal lines (see RM)
|
||||
* is set to 1 in order to enable the interrupt by default.
|
||||
* Bits are set automatically at Power on.
|
||||
* @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23
|
||||
* @arg @ref LL_EXTI_LINE_24(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->IMR, ExtiLine);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
|
||||
* @note The reset value for the direct or internal lines (see RM)
|
||||
* is set to 1 in order to enable the interrupt by default.
|
||||
* Bits are set automatically at Power on.
|
||||
* @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23
|
||||
* @arg @ref LL_EXTI_LINE_24(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
CLEAR_BIT(EXTI->IMR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
|
||||
* @note The reset value for the direct or internal lines (see RM)
|
||||
* is set to 1 in order to enable the interrupt by default.
|
||||
* Bits are set automatically at Power on.
|
||||
* @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23
|
||||
* @arg @ref LL_EXTI_LINE_24(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Event_Management Event_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ExtiLine Event request for Lines in range 0 to 31
|
||||
* @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23
|
||||
* @arg @ref LL_EXTI_LINE_24(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->EMR, ExtiLine);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable ExtiLine Event request for Lines in range 0 to 31
|
||||
* @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23
|
||||
* @arg @ref LL_EXTI_LINE_24(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
CLEAR_BIT(EXTI->EMR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
|
||||
* @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23
|
||||
* @arg @ref LL_EXTI_LINE_24(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
|
||||
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||
* generated on these lines. If a rising edge on a configurable interrupt
|
||||
* line occurs during a write operation in the EXTI_RTSR register, the
|
||||
* pending bit is not set.
|
||||
* Rising and falling edge triggers can be set for
|
||||
* the same interrupt line. In this case, both generate a trigger
|
||||
* condition.
|
||||
* @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->RTSR, ExtiLine);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
|
||||
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||
* generated on these lines. If a rising edge on a configurable interrupt
|
||||
* line occurs during a write operation in the EXTI_RTSR register, the
|
||||
* pending bit is not set.
|
||||
* Rising and falling edge triggers can be set for
|
||||
* the same interrupt line. In this case, both generate a trigger
|
||||
* condition.
|
||||
* @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
CLEAR_BIT(EXTI->RTSR, ExtiLine);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
|
||||
* @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
|
||||
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||
* generated on these lines. If a falling edge on a configurable interrupt
|
||||
* line occurs during a write operation in the EXTI_FTSR register, the
|
||||
* pending bit is not set.
|
||||
* Rising and falling edge triggers can be set for
|
||||
* the same interrupt line. In this case, both generate a trigger
|
||||
* condition.
|
||||
* @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->FTSR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
|
||||
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||
* generated on these lines. If a Falling edge on a configurable interrupt
|
||||
* line occurs during a write operation in the EXTI_FTSR register, the
|
||||
* pending bit is not set.
|
||||
* Rising and falling edge triggers can be set for the same interrupt line.
|
||||
* In this case, both generate a trigger condition.
|
||||
* @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
CLEAR_BIT(EXTI->FTSR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
|
||||
* @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Generate a software Interrupt Event for Lines in range 0 to 31
|
||||
* @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
|
||||
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
|
||||
* resulting in an interrupt request generation.
|
||||
* This bit is cleared by clearing the corresponding bit in the EXTI_PR
|
||||
* register (by writing a 1 into the bit)
|
||||
* @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->SWIER, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
|
||||
* @note This bit is set when the selected edge event arrives on the interrupt
|
||||
* line. This bit is cleared by writing a 1 to the bit.
|
||||
* @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read ExtLine Combination Flag for Lines in range 0 to 31
|
||||
* @note This bit is set when the selected edge event arrives on the interrupt
|
||||
* line. This bit is cleared by writing a 1 to the bit.
|
||||
* @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval @note This bit is set when the selected edge event arrives on the interrupt
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear ExtLine Flags for Lines in range 0 to 31
|
||||
* @note This bit is set when the selected edge event arrives on the interrupt
|
||||
* line. This bit is cleared by writing a 1 to the bit.
|
||||
* @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
WRITE_REG(EXTI->PR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
|
||||
uint32_t LL_EXTI_DeInit(void);
|
||||
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* EXTI */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_EXTI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_ll_fmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of FMC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
1000
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h
Normal file
1000
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h
Normal file
File diff suppressed because it is too large
Load diff
2207
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_i2c.h
Normal file
2207
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_i2c.h
Normal file
File diff suppressed because it is too large
Load diff
363
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_iwdg.h
Normal file
363
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_iwdg.h
Normal file
|
|
@ -0,0 +1,363 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of IWDG LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_IWDG_H
|
||||
#define __STM32F7xx_LL_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(IWDG)
|
||||
|
||||
/** @defgroup IWDG_LL IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
|
||||
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
|
||||
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
|
||||
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_IWDG_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
|
||||
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
|
||||
#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
|
||||
* @{
|
||||
*/
|
||||
#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
|
||||
#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
|
||||
#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
|
||||
#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
|
||||
#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
|
||||
#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
|
||||
#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in IWDG register
|
||||
* @param __INSTANCE__ IWDG Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in IWDG register
|
||||
* @param __INSTANCE__ IWDG Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup IWDG_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the Independent Watchdog
|
||||
* @note Except if the hardware watchdog option is selected
|
||||
* @rmtoll KR KEY LL_IWDG_Enable
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reloads IWDG counter with value defined in the reload register
|
||||
* @rmtoll KR KEY LL_IWDG_ReloadCounter
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
|
||||
* @rmtoll KR KEY LL_IWDG_EnableWriteAccess
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
|
||||
* @rmtoll KR KEY LL_IWDG_DisableWriteAccess
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the prescaler of the IWDG
|
||||
* @rmtoll PR PR LL_IWDG_SetPrescaler
|
||||
* @param IWDGx IWDG Instance
|
||||
* @param Prescaler This parameter can be one of the following values:
|
||||
* @arg @ref LL_IWDG_PRESCALER_4
|
||||
* @arg @ref LL_IWDG_PRESCALER_8
|
||||
* @arg @ref LL_IWDG_PRESCALER_16
|
||||
* @arg @ref LL_IWDG_PRESCALER_32
|
||||
* @arg @ref LL_IWDG_PRESCALER_64
|
||||
* @arg @ref LL_IWDG_PRESCALER_128
|
||||
* @arg @ref LL_IWDG_PRESCALER_256
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
|
||||
{
|
||||
WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the selected prescaler of the IWDG
|
||||
* @rmtoll PR PR LL_IWDG_GetPrescaler
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_IWDG_PRESCALER_4
|
||||
* @arg @ref LL_IWDG_PRESCALER_8
|
||||
* @arg @ref LL_IWDG_PRESCALER_16
|
||||
* @arg @ref LL_IWDG_PRESCALER_32
|
||||
* @arg @ref LL_IWDG_PRESCALER_64
|
||||
* @arg @ref LL_IWDG_PRESCALER_128
|
||||
* @arg @ref LL_IWDG_PRESCALER_256
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(IWDGx->PR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Specify the IWDG down-counter reload value
|
||||
* @rmtoll RLR RL LL_IWDG_SetReloadCounter
|
||||
* @param IWDGx IWDG Instance
|
||||
* @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
|
||||
{
|
||||
WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the specified IWDG down-counter reload value
|
||||
* @rmtoll RLR RL LL_IWDG_GetReloadCounter
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(IWDGx->RLR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Specify high limit of the window value to be compared to the down-counter.
|
||||
* @rmtoll WINR WIN LL_IWDG_SetWindow
|
||||
* @param IWDGx IWDG Instance
|
||||
* @param Window Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
|
||||
{
|
||||
WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the high limit of the window value specified.
|
||||
* @rmtoll WINR WIN LL_IWDG_GetWindow
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(IWDGx->WINR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check if flag Prescaler Value Update is set or not
|
||||
* @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if flag Reload Value Update is set or not
|
||||
* @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if flag Window Value Update is set or not
|
||||
* @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
|
||||
* @rmtoll SR PVU LL_IWDG_IsReady\n
|
||||
* SR WVU LL_IWDG_IsReady\n
|
||||
* SR RVU LL_IWDG_IsReady
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bits (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* IWDG) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_IWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
1382
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_lptim.h
Normal file
1382
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_lptim.h
Normal file
File diff suppressed because it is too large
Load diff
1036
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h
Normal file
1036
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h
Normal file
File diff suppressed because it is too large
Load diff
5170
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h
Normal file
5170
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h
Normal file
File diff suppressed because it is too large
Load diff
355
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rng.h
Normal file
355
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rng.h
Normal file
|
|
@ -0,0 +1,355 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_rng.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of RNG LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_RNG_H
|
||||
#define __STM32F7xx_LL_RNG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(RNG)
|
||||
|
||||
/** @defgroup RNG_LL RNG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_RNG_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
|
||||
#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
|
||||
#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
|
||||
#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
|
||||
#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EC_IT IT Defines
|
||||
* @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
|
||||
* @{
|
||||
*/
|
||||
#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in RNG register
|
||||
* @param __INSTANCE__ RNG Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in RNG register
|
||||
* @param __INSTANCE__ RNG Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable Random Number Generation
|
||||
* @rmtoll CR RNGEN LL_RNG_Enable
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
|
||||
{
|
||||
SET_BIT(RNGx->CR, RNG_CR_RNGEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Random Number Generation
|
||||
* @rmtoll CR RNGEN LL_RNG_Disable
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
|
||||
{
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Random Number Generator is enabled
|
||||
* @rmtoll CR RNGEN LL_RNG_IsEnabled
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Indicate if the RNG Data ready Flag is set or not
|
||||
* @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if the Clock Error Current Status Flag is set or not
|
||||
* @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if the Seed Error Current Status Flag is set or not
|
||||
* @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if the Clock Error Interrupt Status Flag is set or not
|
||||
* @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if the Seed Error Interrupt Status Flag is set or not
|
||||
* @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Clock Error interrupt Status (CEIS) Flag
|
||||
* @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Seed Error interrupt Status (SEIS) Flag
|
||||
* @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EF_IT_Management IT Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable Random Number Generator Interrupt
|
||||
* (applies for either Seed error, Clock Error or Data ready interrupts)
|
||||
* @rmtoll CR IE LL_RNG_EnableIT
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
|
||||
{
|
||||
SET_BIT(RNGx->CR, RNG_CR_IE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Random Number Generator Interrupt
|
||||
* (applies for either Seed error, Clock Error or Data ready interrupts)
|
||||
* @rmtoll CR IE LL_RNG_DisableIT
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
|
||||
{
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_IE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Random Number Generator Interrupt is enabled
|
||||
* (applies for either Seed error, Clock Error or Data ready interrupts)
|
||||
* @rmtoll CR IE LL_RNG_IsEnabledIT
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EF_Data_Management Data Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return32-bit Random Number value
|
||||
* @rmtoll DR RNDATA LL_RNG_ReadRandData32
|
||||
* @param RNGx RNG Instance
|
||||
* @retval Generated 32-bit random value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(RNGx->DR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(RNG) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_RNG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
3867
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rtc.h
Normal file
3867
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rtc.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_ll_sdmmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of SDMMC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -145,6 +145,196 @@ typedef struct
|
|||
/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
|
||||
* @{
|
||||
*/
|
||||
#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */
|
||||
#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */
|
||||
#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */
|
||||
#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */
|
||||
#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
|
||||
#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
|
||||
#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
|
||||
#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
|
||||
number of transferred bytes does not match the block length */
|
||||
#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
|
||||
#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
|
||||
#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
|
||||
#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
|
||||
command or if there was an attempt to access a locked card */
|
||||
#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
|
||||
#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
|
||||
#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
|
||||
#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */
|
||||
#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */
|
||||
#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */
|
||||
#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */
|
||||
#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
|
||||
#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
|
||||
#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
|
||||
#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
|
||||
of erase sequence command was received */
|
||||
#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
|
||||
#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
|
||||
#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
|
||||
#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */
|
||||
#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */
|
||||
#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */
|
||||
#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */
|
||||
#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
|
||||
#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
|
||||
|
||||
/**
|
||||
* @brief SDMMC Commands Index
|
||||
*/
|
||||
#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
|
||||
#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
|
||||
#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
|
||||
#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
|
||||
#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
|
||||
#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
|
||||
operating condition register (OCR) content in the response on the CMD line. */
|
||||
#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
|
||||
#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
|
||||
#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
|
||||
and asks the card whether card supports voltage. */
|
||||
#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
|
||||
#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
|
||||
#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */
|
||||
#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
|
||||
#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
|
||||
#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
|
||||
#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
|
||||
#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
|
||||
(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
|
||||
for SDHS and SDXC. */
|
||||
#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
|
||||
fixed 512 bytes in case of SDHC and SDXC. */
|
||||
#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
|
||||
STOP_TRANSMISSION command. */
|
||||
#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
|
||||
#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
|
||||
#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
|
||||
#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
|
||||
fixed 512 bytes in case of SDHC and SDXC. */
|
||||
#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
|
||||
#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
|
||||
#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
|
||||
#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
|
||||
#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
|
||||
#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
|
||||
#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
|
||||
#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
|
||||
#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
|
||||
system set by switch function command (CMD6). */
|
||||
#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
|
||||
Reserved for each command system set by switch function command (CMD6). */
|
||||
#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
|
||||
#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
|
||||
#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
|
||||
#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
|
||||
the SET_BLOCK_LEN command. */
|
||||
#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
|
||||
than a standard command. */
|
||||
#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
|
||||
for general purpose/application specific commands. */
|
||||
#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
|
||||
|
||||
/**
|
||||
* @brief Following commands are SD Card Specific commands.
|
||||
* SDMMC_APP_CMD should be sent before sending these commands.
|
||||
*/
|
||||
#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
|
||||
widths are given in SCR register. */
|
||||
#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
|
||||
#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
|
||||
32bit+CRC data block. */
|
||||
#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
|
||||
send its operating condition register (OCR) content in the response on the CMD line. */
|
||||
#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
|
||||
#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
|
||||
#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
|
||||
#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
|
||||
|
||||
/**
|
||||
* @brief Following commands are SD Card Specific security commands.
|
||||
* SDMMC_CMD_APP_CMD should be sent before sending these commands.
|
||||
*/
|
||||
#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
|
||||
#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
|
||||
#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
|
||||
#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
|
||||
#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
|
||||
#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
|
||||
#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
|
||||
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
|
||||
#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
|
||||
#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
|
||||
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
|
||||
|
||||
/**
|
||||
* @brief Masks for errors Card Status R1 (OCR Register)
|
||||
*/
|
||||
#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
|
||||
#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
|
||||
#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
|
||||
#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
|
||||
#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
|
||||
#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
|
||||
#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
|
||||
#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
|
||||
#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
|
||||
#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
|
||||
#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
|
||||
#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
|
||||
#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
|
||||
#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
|
||||
#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
|
||||
#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
|
||||
#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
|
||||
#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
|
||||
#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
|
||||
#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
|
||||
|
||||
/**
|
||||
* @brief Masks for R6 Response
|
||||
*/
|
||||
#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
|
||||
#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
|
||||
#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
|
||||
|
||||
#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
|
||||
#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
|
||||
#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
|
||||
#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
|
||||
|
||||
#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
|
||||
|
||||
#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
|
||||
|
||||
#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
|
||||
|
||||
#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
|
||||
#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
|
||||
#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
|
||||
|
||||
#define SDMMC_DATATIMEOUT ((uint32_t)0x00100000U)
|
||||
|
||||
#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
|
||||
#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
|
||||
#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
|
||||
#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
|
||||
#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
|
||||
|
||||
#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
|
||||
#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
|
||||
|
||||
/**
|
||||
* @brief Command Class supported
|
||||
*/
|
||||
#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
|
||||
|
||||
#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
|
||||
#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
|
||||
|
||||
|
||||
/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
|
||||
* @{
|
||||
|
|
@ -428,6 +618,10 @@ typedef struct
|
|||
#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
|
||||
#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
|
||||
#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
|
||||
#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
|
||||
SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
|
||||
SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
|
||||
SDMMC_FLAG_DBCKEND))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -751,7 +945,6 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
|
|||
/** @addtogroup HAL_SDMMC_LL_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Blocking mode: Polling */
|
||||
uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
|
||||
HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
|
||||
/**
|
||||
|
|
@ -772,13 +965,40 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
|
|||
uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
|
||||
|
||||
/* Data path state machine (DPSM) management functions */
|
||||
HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
|
||||
HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
|
||||
uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
|
||||
|
||||
/* SDMMC Cards mode management functions */
|
||||
HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
|
||||
|
||||
/* SDMMC Commands management functions */
|
||||
uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
|
||||
uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
|
||||
uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
|
||||
uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
|
||||
uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
|
||||
uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
|
||||
uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
|
||||
uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
|
||||
uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
|
||||
uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
|
||||
uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType);
|
||||
uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
|
||||
uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
|
||||
uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
2293
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h
Normal file
2293
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h
Normal file
File diff suppressed because it is too large
Load diff
1039
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h
Normal file
1039
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h
Normal file
File diff suppressed because it is too large
Load diff
4663
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h
Normal file
4663
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h
Normal file
File diff suppressed because it is too large
Load diff
3560
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h
Normal file
3560
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_ll_usb.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of USB Core HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -126,6 +126,8 @@ typedef struct
|
|||
|
||||
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
|
||||
|
||||
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
|
||||
|
||||
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
|
||||
|
||||
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
|
||||
|
|
@ -256,6 +258,12 @@ typedef struct
|
|||
*/
|
||||
#define USB_OTG_ULPI_PHY 1U
|
||||
#define USB_OTG_EMBEDDED_PHY 2U
|
||||
#define USB_OTG_HS_EMBEDDED_PHY 3U
|
||||
|
||||
#if !defined (USB_HS_PHYC_TUNE_VALUE)
|
||||
#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */
|
||||
#endif /* USB_HS_PHYC_TUNE_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -382,6 +390,9 @@ typedef struct
|
|||
|
||||
#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
|
||||
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
|
||||
#define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
323
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h
Normal file
323
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h
Normal file
|
|
@ -0,0 +1,323 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_utils.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of UTILS LL module.
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The LL UTILS driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) Device electronic signature
|
||||
(+) Timing functions
|
||||
(+) PLL configuration functions
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_UTILS_H
|
||||
#define __STM32F7xx_LL_UTILS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL UTILS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Max delay can be used in LL_mDelay */
|
||||
#define LL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* @brief Unique device ID register base address
|
||||
*/
|
||||
#define UID_BASE_ADDRESS UID_BASE
|
||||
|
||||
/**
|
||||
* @brief Flash size data register base address
|
||||
*/
|
||||
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
|
||||
|
||||
/**
|
||||
* @brief Package data register base address
|
||||
*/
|
||||
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief UTILS PLL structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
|
||||
uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
|
||||
This parameter must be a number between Min_Data = 50 and Max_Data = 432
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
|
||||
uint32_t PLLP; /*!< Division for the main system clock.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
} LL_UTILS_PLLInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief UTILS System, AHB and APB buses clock configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAHBPrescaler(). */
|
||||
|
||||
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB1Prescaler(). */
|
||||
|
||||
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB2Prescaler(). */
|
||||
|
||||
} LL_UTILS_ClkInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
|
||||
* @{
|
||||
*/
|
||||
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
|
||||
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
|
||||
* @{
|
||||
*/
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000100U /*!< LQFP100 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 0x00000200U /*!< LQFP144 or WLCSP143 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 0x00000300U /*!< WLCSP180, LQFP176 or UFBGA176 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 0x00000400U /*!< LQFP176, LQFP208 or TFBGA216 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_TFBGA216_LQFP176_LQFP208 0x00000500U /*!< LQFP176, LQFP208 or TFBGA216 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP176_TFBGA216_LQFP208 0x00000600U /*!< LQFP176, LQFP208 or TFBGA216 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP208_LQFP176_TFBGA216 0x00000700U /*!< LQFP176, LQFP208 or TFBGA216 package type */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[31:0]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[63:32]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[95:64]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Flash memory size
|
||||
* @note This bitfield indicates the size of the device Flash memory expressed in
|
||||
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
|
||||
* @retval FLASH_SIZE[15:0]: Flash memory size
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||
{
|
||||
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Package type
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetPackageType(void)
|
||||
{
|
||||
return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL_EF_DELAY DELAY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Cortex-M SysTick source of the time base.
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param Ticks Number of ticks
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
{
|
||||
/* Configure the SysTick to have interrupt in 1ms time base */
|
||||
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
|
||||
}
|
||||
|
||||
void LL_Init1msTick(uint32_t HCLKFrequency);
|
||||
void LL_mDelay(uint32_t Delay);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_SYSTEM SYSTEM
|
||||
* @{
|
||||
*/
|
||||
|
||||
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_UTILS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
342
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_wwdg.h
Normal file
342
lib/main/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_wwdg.h
Normal file
|
|
@ -0,0 +1,342 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief Header file of WWDG LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_WWDG_H
|
||||
#define __STM32F7xx_LL_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (WWDG)
|
||||
|
||||
/** @defgroup WWDG_LL WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup WWDG_LL_EC_IT IT Defines
|
||||
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Write a value in WWDG register
|
||||
* @param __INSTANCE__ WWDG Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in WWDG register
|
||||
* @param __INSTANCE__ WWDG Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
|
||||
* @note It is enabled by setting the WDGA bit in the WWDG_CR register,
|
||||
* then it cannot be disabled again except by a reset.
|
||||
* This bit is set by software and only cleared by hardware after a reset.
|
||||
* When WDGA = 1, the watchdog can generate a reset.
|
||||
* @rmtoll CR WDGA LL_WWDG_Enable
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if Window Watchdog is enabled
|
||||
* @rmtoll CR WDGA LL_WWDG_IsEnabled
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
|
||||
* @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
|
||||
* This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
|
||||
* A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
|
||||
* Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
|
||||
* @rmtoll CR T LL_WWDG_SetCounter
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Counter 0..0x7F (7 bit counter value)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Counter Value (7 bits counter value)
|
||||
* @rmtoll CR T LL_WWDG_GetCounter
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval 7 bit Watchdog Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the time base of the prescaler (WDGTB).
|
||||
* @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
|
||||
* is decremented every (4096 x 2expWDGTB) PCLK cycles
|
||||
* @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Prescaler This parameter can be one of the following values:
|
||||
* @arg @ref LL_WWDG_PRESCALER_1
|
||||
* @arg @ref LL_WWDG_PRESCALER_2
|
||||
* @arg @ref LL_WWDG_PRESCALER_4
|
||||
* @arg @ref LL_WWDG_PRESCALER_8
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Prescaler Value
|
||||
* @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_WWDG_PRESCALER_1
|
||||
* @arg @ref LL_WWDG_PRESCALER_2
|
||||
* @arg @ref LL_WWDG_PRESCALER_4
|
||||
* @arg @ref LL_WWDG_PRESCALER_8
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
|
||||
* @note This window value defines when write in the WWDG_CR register
|
||||
* to program Watchdog counter is allowed.
|
||||
* Watchdog counter value update must occur only when the counter value
|
||||
* is lower than the Watchdog window register value.
|
||||
* Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
|
||||
* (in the control register) is refreshed before the downcounter has reached
|
||||
* the watchdog window register value.
|
||||
* Physically is possible to set the Window lower then 0x40 but it is not recommended.
|
||||
* To generate an immediate reset, it is possible to set the Counter lower than 0x40.
|
||||
* @rmtoll CFR W LL_WWDG_SetWindow
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Window 0x00..0x7F (7 bit Window value)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Window Value (7 bits value)
|
||||
* @rmtoll CFR W LL_WWDG_GetWindow
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval 7 bit Watchdog Window value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
|
||||
* @note This bit is set by hardware when the counter has reached the value 0x40.
|
||||
* It must be cleared by software by writing 0.
|
||||
* A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
|
||||
* @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
|
||||
* @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_IT_Management IT_Management
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the Early Wakeup Interrupt.
|
||||
* @note When set, an interrupt occurs whenever the counter reaches value 0x40.
|
||||
* This interrupt is only cleared by hardware after a reset
|
||||
* @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Early Wakeup Interrupt is enabled
|
||||
* @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* WWDG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_WWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief HAL module driver.
|
||||
* This is the common part of the HAL initialization
|
||||
*
|
||||
|
|
@ -68,11 +68,11 @@
|
|||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32F7xx HAL Driver version number V1.1.2
|
||||
* @brief STM32F7xx HAL Driver version number V1.2.0
|
||||
*/
|
||||
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32F7xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
|
||||
#define __STM32F7xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|
||||
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f7xx_hal_adc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.2
|
||||
* @date 23-September-2016
|
||||
* @version V1.2.0
|
||||
* @date 30-December-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
|
|
@ -270,7 +270,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
|
|||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
|
||||
assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
|
||||
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
|
||||
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
|
||||
assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
|
||||
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
|
||||
|
|
|
|||
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