Mirror/betaflight
1
0
Fork 0
mirror of https://github.com/betaflight/betaflight.git synced 2025-07-23 00:05:33 +03:00
Code Issues Wiki Activity

Removing Custom Defaults (#12425)

Browse source
This commit is contained in:
J Blackman 2023-03-03 05:39:44 +11:00 • committed by GitHub
parent 68136910d0
commit ee77239db1
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
48 changed files with 155 additions and 552 deletions
Download patch file Download diff file Expand all files Collapse all files

13
src/link/at32_flash_f43xM.ld
View file

@ -18,21 +18,16 @@
*****************************************************************************
*/
/*
FLASH : 0x0800 0000 -- 0x083E FFFF
MEM : 0x2000 0000 -- 0x2007 FFFF
FLASH : 0x0800 0000 -- 0x083E FFFF
MEM : 0x2000 0000 -- 0x2007 FFFF
*/
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 10K
FLASH_CDEF (r) : ORIGIN = 0x08002800, LENGTH = 6K
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 16K
FLASH_CONFIG (r) : ORIGIN = 0x08004000, LENGTH = 16K
FLASH1 (rx) : ORIGIN = 0x08008000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 3984K: 4000K
FLASH_CDEF_EXT (r) : ORIGIN = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 0x083EC000 : 0x083F0000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 16K : 0K
FLASH1 (rx) : ORIGIN = 0x08008000, LENGTH = 4000K
SYSTEM_MEMORY (rx) : ORIGIN = 0x1FFF0000, LENGTH = 16K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K /* external ram */

21
src/link/at32_flash_f4_split.ld
View file

@ -73,7 +73,7 @@ SECTIONS
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH1
/*
Critical program code goes into RAM
*/
@ -81,14 +81,13 @@ SECTIONS
.tcm_code :
{
. = ALIGN(4);
tcm_code_start = .;
tcm_code_start = .;
*(.tcm_code)
*(.tcm_code*)
. = ALIGN(4);
tcm_code_end = .;
} >RAM AT >FLASH1
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
@ -130,22 +129,6 @@ SECTIONS
PROVIDE_HIDDEN (__pg_resetdata_end = .);
} >FLASH1
/* Storage for the address for the configuration section so we can grab it out of the hex file */
.custom_defaults :
{
. = ALIGN(4);
KEEP (*(.custom_defaults_start_address))
. = ALIGN(4);
KEEP (*(.custom_defaults_end_address))
. = ALIGN(4);
__custom_defaults_internal_start = .;
KEEP (*(.custom_defaults))
. = ALIGN(4);
} >FLASH_CDEF
PROVIDE_HIDDEN (__custom_defaults_start = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? ORIGIN(FLASH_CDEF_EXT) : __custom_defaults_internal_start);
PROVIDE_HIDDEN (__custom_defaults_end = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? ORIGIN(FLASH_CDEF_EXT) + LENGTH(FLASH_CDEF_EXT) : ORIGIN(FLASH_CDEF) + LENGTH(FLASH_CDEF));
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);

11
src/link/stm32_flash.ld
View file

@ -54,19 +54,18 @@ SECTIONS
} >FLASH
/* Critical program code goes into CCM RAM */
/* Copy specific fast-executing code to CCM RAM */
ccm_code = LOADADDR(.ccm_code);
/* Copy specific fast-executing code to CCM RAM */
ccm_code = LOADADDR(.ccm_code);
.ccm_code :
{
. = ALIGN(4);
ccm_code_start = .;
ccm_code_start = .;
*(.ccm_code)
*(.ccm_code*)
. = ALIGN(4);
ccm_code_end = .;
ccm_code_end = .;
} >CCM AT >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
@ -138,7 +137,7 @@ SECTIONS
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
.fastram_bss (NOLOAD) :
{
__fastram_bss_start__ = .;

6
src/link/stm32_flash_f405.ld
View file

@ -19,11 +19,9 @@
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 10K
FLASH_CUSTOM_DEFAULTS (r) : ORIGIN = 0x08002800, LENGTH = 6K
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 16K
FLASH_CONFIG (r) : ORIGIN = 0x08004000, LENGTH = 16K
FLASH1 (rx) : ORIGIN = 0x08008000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 976K : 992K
FLASH_CUSTOM_DEFAULTS_EXTENDED (r): ORIGIN = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 0x080FC000 : 0x08100000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 16K : 0K
FLASH1 (rx) : ORIGIN = 0x08008000, LENGTH = 992K
SYSTEM_MEMORY (rx): ORIGIN = 0x1FFF0000, LENGTH = 29K

6
src/link/stm32_flash_f411.ld
View file

@ -20,11 +20,9 @@
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 10K
FLASH_CUSTOM_DEFAULTS (r) : ORIGIN = 0x08002800, LENGTH = 6K
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 16K
FLASH_CONFIG (r) : ORIGIN = 0x08004000, LENGTH = 16K
FLASH1 (rx) : ORIGIN = 0x08008000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 464K : 480K
FLASH_CUSTOM_DEFAULTS_EXTENDED (r): ORIGIN = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 0x0807C000 : 0x08080000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 16K : 0K
FLASH1 (rx) : ORIGIN = 0x08008000, LENGTH = 480K
SYSTEM_MEMORY (rx): ORIGIN = 0x1FFF0000, LENGTH = 29K

16
src/link/stm32_flash_f4_split.ld
View file

@ -116,22 +116,6 @@ SECTIONS
PROVIDE_HIDDEN (__pg_resetdata_end = .);
} >FLASH1
/* Storage for the address for the configuration section so we can grab it out of the hex file */
.custom_defaults :
{
. = ALIGN(4);
KEEP (*(.custom_defaults_start_address))
. = ALIGN(4);
KEEP (*(.custom_defaults_end_address))
. = ALIGN(4);
__custom_defaults_internal_start = .;
KEEP (*(.custom_defaults))
. = ALIGN(4);
} >FLASH_CUSTOM_DEFAULTS
PROVIDE_HIDDEN (__custom_defaults_start = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? ORIGIN(FLASH_CUSTOM_DEFAULTS_EXTENDED) : __custom_defaults_internal_start);
PROVIDE_HIDDEN (__custom_defaults_end = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? ORIGIN(FLASH_CUSTOM_DEFAULTS_EXTENDED) + LENGTH(FLASH_CUSTOM_DEFAULTS_EXTENDED) : ORIGIN(FLASH_CUSTOM_DEFAULTS) + LENGTH(FLASH_CUSTOM_DEFAULTS));
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);

8
src/link/stm32_flash_f722.ld
View file

@ -26,12 +26,10 @@ MEMORY
ITCM_FLASH_CONFIG (r) : ORIGIN = 0x00204000, LENGTH = 16K
ITCM_FLASH1 (rx) : ORIGIN = 0x00208000, LENGTH = 480K
AXIM_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 10K
AXIM_FLASH_CUSTOM_DEFAULTS (r) : ORIGIN = 0x08002800, LENGTH = 6K
AXIM_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 16K
/* config occupies the entire flash sector 1 for the ease of erasure, 16K on F72x */
AXIM_FLASH_CONFIG (r) : ORIGIN = 0x08004000, LENGTH = 16K
AXIM_FLASH1 (rx) : ORIGIN = 0x08008000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 464K : 480K
AXIM_FLASH_CUSTOM_DEFAULTS_EXTENDED (r) : ORIGIN = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 0x0807C000 : 0x08080000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 16K : 0K
AXIM_FLASH1 (rx) : ORIGIN = 0x08008000, LENGTH = 480K
DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
SRAM1 (rwx) : ORIGIN = 0x20010000, LENGTH = 176K
@ -41,11 +39,9 @@ MEMORY
REGION_ALIAS("FLASH", AXIM_FLASH)
REGION_ALIAS("WRITABLE_FLASH", AXIM_FLASH)
REGION_ALIAS("FLASH_CUSTOM_DEFAULTS", AXIM_FLASH_CUSTOM_DEFAULTS)
REGION_ALIAS("FLASH_CONFIG", AXIM_FLASH_CONFIG)
REGION_ALIAS("FLASH1", AXIM_FLASH1)
REGION_ALIAS("WRITABLE_FLASH1", AXIM_FLASH1)
REGION_ALIAS("FLASH_CUSTOM_DEFAULTS_EXTENDED", AXIM_FLASH_CUSTOM_DEFAULTS_EXTENDED)
REGION_ALIAS("STACKRAM", DTCM_RAM)
REGION_ALIAS("FASTRAM", DTCM_RAM)

27
src/link/stm32_flash_f74x.ld
View file

@ -21,34 +21,29 @@
/* Specify the memory areas */
MEMORY
{
ITCM_RAM (rx) : ORIGIN = 0x00000000, LENGTH = 16K
ITCM_RAM (rx) : ORIGIN = 0x00000000, LENGTH = 16K
/* Alternate access to the same flash storage as AXIM flash, but not writable by the boot loader. */
ITCM_FLASH (rx) : ORIGIN = 0x00200000, LENGTH = 32K
ITCM_FLASH_CONFIG (r) : ORIGIN = 0x00208000, LENGTH = 32K
ITCM_FLASH1 (rx) : ORIGIN = 0x00210000, LENGTH = 960K
ITCM_FLASH (rx) : ORIGIN = 0x00200000, LENGTH = 32K
ITCM_FLASH_CONFIG (r) : ORIGIN = 0x00208000, LENGTH = 32K
ITCM_FLASH1 (rx) : ORIGIN = 0x00210000, LENGTH = 960K
AXIM_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 10K
AXIM_FLASH_CUSTOM_DEFAULTS (r) : ORIGIN = 0x08002800, LENGTH = 10K
AXIM_FLASH_UNUSED (r) : ORIGIN = 0x08005000, LENGTH = 12K
AXIM_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
/* config occupies the entire flash sector 1 for the ease of erasure, 32K on F74x */
AXIM_FLASH_CONFIG (r) : ORIGIN = 0x08008000, LENGTH = 32K
AXIM_FLASH1 (rx) : ORIGIN = 0x08010000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 928K : 960K
AXIM_FLASH_CUSTOM_DEFAULTS_EXTENDED (r) : ORIGIN = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 0x080F8000 : 0x08100000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 32K : 0K
AXIM_FLASH_CONFIG (r) : ORIGIN = 0x08008000, LENGTH = 32K
AXIM_FLASH1 (rx) : ORIGIN = 0x08010000, LENGTH = 960K
DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
SRAM1 (rwx) : ORIGIN = 0x20010000, LENGTH = 240K
SRAM2 (rwx) : ORIGIN = 0x2004C000, LENGTH = 16K
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
SRAM1 (rwx) : ORIGIN = 0x20010000, LENGTH = 240K
SRAM2 (rwx) : ORIGIN = 0x2004C000, LENGTH = 16K
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
}
REGION_ALIAS("FLASH", ITCM_FLASH)
REGION_ALIAS("WRITABLE_FLASH", AXIM_FLASH)
REGION_ALIAS("FLASH_CUSTOM_DEFAULTS", AXIM_FLASH_CUSTOM_DEFAULTS)
REGION_ALIAS("FLASH_CONFIG", AXIM_FLASH_CONFIG)
REGION_ALIAS("FLASH1", ITCM_FLASH1)
REGION_ALIAS("WRITABLE_FLASH1", AXIM_FLASH1)
REGION_ALIAS("FLASH_CUSTOM_DEFAULTS_EXTENDED", AXIM_FLASH_CUSTOM_DEFAULTS_EXTENDED)
REGION_ALIAS("STACKRAM", DTCM_RAM)
REGION_ALIAS("FASTRAM", DTCM_RAM)

4
src/link/stm32_flash_f765.ld
View file

@ -28,9 +28,7 @@ MEMORY
ITCM_FLASH_CONFIG (r) : ORIGIN = 0x00208000, LENGTH = 32K
ITCM_FLASH1 (rx) : ORIGIN = 0x00210000, LENGTH = 1984K
AXIM_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 10K
AXIM_FLASH_CUSTOM_DEFAULTS (r) : ORIGIN = 0x08002800, LENGTH = 10K
AXIM_FLASH_UNUSED (r) : ORIGIN = 0x08005000, LENGTH = 12K
AXIM_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
AXIM_FLASH_CONFIG (r) : ORIGIN = 0x08008000, LENGTH = 32K
AXIM_FLASH1 (rx) : ORIGIN = 0x08010000, LENGTH = 1984K

36
src/link/stm32_flash_f7_split.ld
View file

@ -54,24 +54,24 @@ SECTIONS
} >FLASH1 AT >WRITABLE_FLASH1
/* Critical program code goes into ITCM RAM */
/* Copy specific fast-executing code to ITCM RAM */
tcm_code = LOADADDR(.tcm_code);
/* Copy specific fast-executing code to ITCM RAM */
tcm_code = LOADADDR(.tcm_code);
.tcm_code :
{
. = ALIGN(4);
tcm_code_start = .;
tcm_code_start = .;
*(.tcm_code)
*(.tcm_code*)
. = ALIGN(4);
tcm_code_end = .;
tcm_code_end = .;
} >ITCM_RAM AT >WRITABLE_FLASH1
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >MOVABLE_FLASH
.ARM :
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*) __exidx_end = .;
@ -84,7 +84,7 @@ SECTIONS
KEEP (*(SORT(.pg_registry.*)))
PROVIDE_HIDDEN (__pg_registry_end = .);
} >MOVABLE_FLASH
.pg_resetdata :
{
PROVIDE_HIDDEN (__pg_resetdata_start = .);
@ -92,22 +92,6 @@ SECTIONS
PROVIDE_HIDDEN (__pg_resetdata_end = .);
} >WRITABLE_FLASH1
/* Storage for the address for the configuration section so we can grab it out of the hex file */
.custom_defaults :
{
. = ALIGN(4);
KEEP (*(.custom_defaults_start_address))
. = ALIGN(4);
KEEP (*(.custom_defaults_end_address))
. = ALIGN(4);
__custom_defaults_internal_start = .;
KEEP (*(.custom_defaults))
. = ALIGN(4);
} >FLASH_CUSTOM_DEFAULTS
PROVIDE_HIDDEN (__custom_defaults_start = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? ORIGIN(FLASH_CUSTOM_DEFAULTS_EXTENDED) : __custom_defaults_internal_start);
PROVIDE_HIDDEN (__custom_defaults_end = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? ORIGIN(FLASH_CUSTOM_DEFAULTS_EXTENDED) + LENGTH(FLASH_CUSTOM_DEFAULTS_EXTENDED) : ORIGIN(FLASH_CUSTOM_DEFAULTS) + LENGTH(FLASH_CUSTOM_DEFAULTS));
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);

5
src/link/stm32_flash_g474.ld
View file

@ -13,11 +13,8 @@
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 10K
FLASH_CUSTOM_DEFAULTS (r) : ORIGIN = 0x08002800, LENGTH = 6K
FLASH_CONFIG (r) : ORIGIN = 0x08004000, LENGTH = 8K
FLASH1 (rx) : ORIGIN = 0x08006000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 480K : 488K
FLASH_CUSTOM_DEFAULTS_EXTENDED (r): ORIGIN = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 0x0807E000 : 0x08080000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 8K : 0K
FLASH1 (rx) : ORIGIN = 0x08006000, LENGTH = 496K
SYSTEM_MEMORY (r) : ORIGIN = 0x1FFF0000, LENGTH = 64K
/* Below are the true lengths for normal and close coupled RAM

16
src/link/stm32_flash_g4_split.ld
View file

@ -119,22 +119,6 @@ SECTIONS
PROVIDE_HIDDEN (__pg_resetdata_end = .);
} >FLASH1
/* Storage for the address for the configuration section so we can grab it out of the hex file */
.custom_defaults :
{
. = ALIGN(4);
KEEP (*(.custom_defaults_start_address))
. = ALIGN(4);
KEEP (*(.custom_defaults_end_address))
. = ALIGN(4);
__custom_defaults_internal_start = .;
KEEP (*(.custom_defaults))
. = ALIGN(4);
} >FLASH_CUSTOM_DEFAULTS
PROVIDE_HIDDEN (__custom_defaults_start = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? ORIGIN(FLASH_CUSTOM_DEFAULTS_EXTENDED) : __custom_defaults_internal_start);
PROVIDE_HIDDEN (__custom_defaults_end = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? ORIGIN(FLASH_CUSTOM_DEFAULTS_EXTENDED) + LENGTH(FLASH_CUSTOM_DEFAULTS_EXTENDED) : ORIGIN(FLASH_CUSTOM_DEFAULTS) + LENGTH(FLASH_CUSTOM_DEFAULTS));
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);

43
src/link/stm32_flash_h723_1m.ld
View file

@ -36,13 +36,9 @@ ENTRY(Reset_Handler)
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 10K
FLASH_CUSTOM_DEFAULTS (r) : ORIGIN = 0x08002800, LENGTH = 10K
FLASH_UNUSED (r) : ORIGIN = 0x08005000, LENGTH = 108K
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
FLASH_CONFIG (r) : ORIGIN = 0x08020000, LENGTH = 128K
FLASH1 (rx) : ORIGIN = 0x08040000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 640K : 768K
FLASH_CUSTOM_DEFAULTS_EXTENDED (r): ORIGIN = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 0x081E0000 : 0x08200000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 128K : 0K
FLASH1 (rx) : ORIGIN = 0x08040000, LENGTH = 768K
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
@ -101,24 +97,24 @@ SECTIONS
} >FLASH1
/* Critical program code goes into ITCM RAM */
/* Copy specific fast-executing code to ITCM RAM */
tcm_code = LOADADDR(.tcm_code);
/* Copy specific fast-executing code to ITCM RAM */
tcm_code = LOADADDR(.tcm_code);
.tcm_code :
{
. = ALIGN(4);
tcm_code_start = .;
tcm_code_start = .;
*(.tcm_code)
*(.tcm_code*)
. = ALIGN(4);
tcm_code_end = .;
tcm_code_end = .;
} >ITCM_RAM AT >FLASH1
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >FLASH1
.ARM :
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*) __exidx_end = .;
@ -131,7 +127,7 @@ SECTIONS
KEEP (*(SORT(.pg_registry.*)))
PROVIDE_HIDDEN (__pg_registry_end = .);
} >FLASH1
.pg_resetdata :
{
PROVIDE_HIDDEN (__pg_resetdata_start = .);
@ -139,21 +135,6 @@ SECTIONS
PROVIDE_HIDDEN (__pg_resetdata_end = .);
} >FLASH1
/* Storage for the address for the configuration section so we can grab it out of the hex file */
.custom_defaults :
{
. = ALIGN(4);
KEEP (*(.custom_defaults_start_address))
. = ALIGN(4);
KEEP (*(.custom_defaults_end_address))
. = ALIGN(4);
__custom_defaults_internal_start = .;
*(.custom_defaults);
} >FLASH_CUSTOM_DEFAULTS
PROVIDE_HIDDEN (__custom_defaults_start = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? ORIGIN(FLASH_CUSTOM_DEFAULTS_EXTENDED) : __custom_defaults_internal_start);
PROVIDE_HIDDEN (__custom_defaults_end = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? ORIGIN(FLASH_CUSTOM_DEFAULTS_EXTENDED) + LENGTH(FLASH_CUSTOM_DEFAULTS_EXTENDED) : ORIGIN(FLASH_CUSTOM_DEFAULTS) + LENGTH(FLASH_CUSTOM_DEFAULTS));
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);

43
src/link/stm32_flash_h743_2m.ld
View file

@ -37,13 +37,9 @@ ENTRY(Reset_Handler)
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 10K
FLASH_CUSTOM_DEFAULTS (r) : ORIGIN = 0x08002800, LENGTH = 10K
FLASH_UNUSED (r) : ORIGIN = 0x08005000, LENGTH = 108K
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
FLASH_CONFIG (r) : ORIGIN = 0x08020000, LENGTH = 128K
FLASH1 (rx) : ORIGIN = 0x08040000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 1664K : 1792K
FLASH_CUSTOM_DEFAULTS_EXTENDED (r): ORIGIN = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 0x081E0000 : 0x08200000, LENGTH = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? 128K : 0K
FLASH1 (rx) : ORIGIN = 0x08040000, LENGTH = 1792K
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
@ -103,24 +99,24 @@ SECTIONS
} >FLASH1
/* Critical program code goes into ITCM RAM */
/* Copy specific fast-executing code to ITCM RAM */
tcm_code = LOADADDR(.tcm_code);
/* Copy specific fast-executing code to ITCM RAM */
tcm_code = LOADADDR(.tcm_code);
.tcm_code :
{
. = ALIGN(4);
tcm_code_start = .;
tcm_code_start = .;
*(.tcm_code)
*(.tcm_code*)
. = ALIGN(4);
tcm_code_end = .;
tcm_code_end = .;
} >ITCM_RAM AT >FLASH1
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >FLASH1
.ARM :
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*) __exidx_end = .;
@ -133,7 +129,7 @@ SECTIONS
KEEP (*(SORT(.pg_registry.*)))
PROVIDE_HIDDEN (__pg_registry_end = .);
} >FLASH1
.pg_resetdata :
{
PROVIDE_HIDDEN (__pg_resetdata_start = .);
@ -141,21 +137,6 @@ SECTIONS
PROVIDE_HIDDEN (__pg_resetdata_end = .);
} >FLASH1
/* Storage for the address for the configuration section so we can grab it out of the hex file */
.custom_defaults :
{
. = ALIGN(4);
KEEP (*(.custom_defaults_start_address))
. = ALIGN(4);
KEEP (*(.custom_defaults_end_address))
. = ALIGN(4);
__custom_defaults_internal_start = .;
*(.custom_defaults);
} >FLASH_CUSTOM_DEFAULTS
PROVIDE_HIDDEN (__custom_defaults_start = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? ORIGIN(FLASH_CUSTOM_DEFAULTS_EXTENDED) : __custom_defaults_internal_start);
PROVIDE_HIDDEN (__custom_defaults_end = DEFINED(USE_CUSTOM_DEFAULTS_EXTENDED) ? ORIGIN(FLASH_CUSTOM_DEFAULTS_EXTENDED) + LENGTH(FLASH_CUSTOM_DEFAULTS_EXTENDED) : ORIGIN(FLASH_CUSTOM_DEFAULTS) + LENGTH(FLASH_CUSTOM_DEFAULTS));
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);

2
src/link/stm32_flash_h750_128k.ld
View file

@ -43,7 +43,7 @@ MEMORY
D2_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 256K /* SRAM1 + SRAM2 */
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
QUADSPI (rx) : ORIGIN = 0x90000000, LENGTH = 0K
QUADSPI (rx) : ORIGIN = 0x90000000, LENGTH = 0K
}
REGION_ALIAS("STACKRAM", DTCM_RAM)

2
src/link/stm32_flash_h750_1m.ld
View file

@ -43,7 +43,7 @@ MEMORY
D2_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 256K /* SRAM1 + SRAM2 */
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
QUADSPI (rx) : ORIGIN = 0x90000000, LENGTH = 0K
QUADSPI (rx) : ORIGIN = 0x90000000, LENGTH = 0K
}
REGION_ALIAS("STACKRAM", DTCM_RAM)

30
src/link/stm32_h723_common.ld
View file

@ -36,7 +36,7 @@ SECTIONS
. = ALIGN(512); /* Vector table offset must be multiple of 0x200 */
PROVIDE (ram_isr_vector_table_base = .);
. += (isr_vector_table_end - isr_vector_table_base);
. = ALIGN(4);
. = ALIGN(4);
PROVIDE (ram_isr_vector_table_end = .);
} >DTCM_RAM
@ -60,24 +60,24 @@ SECTIONS
} >MAIN
/* Critical program code goes into ITCM RAM */
/* Copy specific fast-executing code to ITCM RAM */
tcm_code = LOADADDR(.tcm_code);
/* Copy specific fast-executing code to ITCM RAM */
tcm_code = LOADADDR(.tcm_code);
.tcm_code :
{
. = ALIGN(4);
tcm_code_start = .;
tcm_code_start = .;
*(.tcm_code)
*(.tcm_code*)
. = ALIGN(4);
tcm_code_end = .;
tcm_code_end = .;
} >ITCM_RAM AT >MAIN
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >MAIN
.ARM :
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*) __exidx_end = .;
@ -90,7 +90,7 @@ SECTIONS
KEEP (*(SORT(.pg_registry.*)))
PROVIDE_HIDDEN (__pg_registry_end = .);
} >MAIN
.pg_resetdata :
{
PROVIDE_HIDDEN (__pg_resetdata_start = .);
@ -114,16 +114,16 @@ SECTIONS
} >DTCM_RAM AT >MAIN
/* Non-critical program code goes into RAM */
/* Copy specific slow-executing code to RAM */
ram_code = LOADADDR(.ram_code);
/* Copy specific slow-executing code to RAM */
ram_code = LOADADDR(.ram_code);
.ram_code :
{
. = ALIGN(4);
ram_code_start = .;
ram_code_start = .;
*(.ram_code)
*(.ram_code*)
. = ALIGN(4);
ram_code_end = .;
ram_code_end = .;
} >RAM AT >MAIN
/* Uninitialized data section */

2
src/link/stm32_h723_common_post.ld
View file

@ -31,7 +31,7 @@ SECTIONS
*(.mb1rodata) /* read-only data (constants) */
*(.mb1rodata*)
} >MEMORY_B1
/* Remove information from the standard libraries */
/DISCARD/ :
{

16
src/link/stm32_h730_common.ld
View file

@ -36,7 +36,7 @@ SECTIONS
. = ALIGN(512); /* Vector table offset must be multiple of 0x200 */
PROVIDE (ram_isr_vector_table_base = .);
. += (isr_vector_table_end - isr_vector_table_base);
. = ALIGN(4);
. = ALIGN(4);
PROVIDE (ram_isr_vector_table_end = .);
} >DTCM_RAM
@ -76,8 +76,8 @@ SECTIONS
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >MAIN
.ARM :
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*) __exidx_end = .;
@ -90,7 +90,7 @@ SECTIONS
KEEP (*(SORT(.pg_registry.*)))
PROVIDE_HIDDEN (__pg_registry_end = .);
} >MAIN
.pg_resetdata :
{
PROVIDE_HIDDEN (__pg_resetdata_start = .);
@ -114,16 +114,16 @@ SECTIONS
} >DTCM_RAM AT >MAIN
/* Non-critical program code goes into RAM */
/* Copy specific slow-executing code to RAM */
ram_code = LOADADDR(.ram_code);
/* Copy specific slow-executing code to RAM */
ram_code = LOADADDR(.ram_code);
.ram_code :
{
. = ALIGN(4);
ram_code_start = .;
ram_code_start = .;
*(.ram_code)
*(.ram_code*)
. = ALIGN(4);
ram_code_end = .;
ram_code_end = .;
} >RAM AT >MAIN
/* Uninitialized data section */

2
src/link/stm32_h730_common_post.ld
View file

@ -31,7 +31,7 @@ SECTIONS
*(.mb1rodata) /* read-only data (constants) */
*(.mb1rodata*)
} >MEMORY_B1
/* Remove information from the standard libraries */
/DISCARD/ :
{

20
src/link/stm32_h750_common.ld
View file

@ -44,24 +44,24 @@ SECTIONS
} >MAIN
/* Critical program code goes into ITCM RAM */
/* Copy specific fast-executing code to ITCM RAM */
tcm_code = LOADADDR(.tcm_code);
/* Copy specific fast-executing code to ITCM RAM */
tcm_code = LOADADDR(.tcm_code);
.tcm_code :
{
. = ALIGN(4);
tcm_code_start = .;
tcm_code_start = .;
*(.tcm_code)
*(.tcm_code*)
. = ALIGN(4);
tcm_code_end = .;
tcm_code_end = .;
} >ITCM_RAM AT >MAIN
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >MAIN
.ARM :
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*) __exidx_end = .;
@ -74,7 +74,7 @@ SECTIONS
KEEP (*(SORT(.pg_registry.*)))
PROVIDE_HIDDEN (__pg_registry_end = .);
} >MAIN
.pg_resetdata :
{
PROVIDE_HIDDEN (__pg_resetdata_start = .);

2
src/link/stm32_h750_common_post.ld
View file

@ -31,7 +31,7 @@ SECTIONS
*(.mb1rodata) /* read-only data (constants) */
*(.mb1rodata*)
} >MEMORY_B1
/* Remove information from the standard libraries */
/DISCARD/ :
{

7
src/link/stm32_ram_h723_exst.ld
View file

@ -30,7 +30,7 @@ ENTRY(Reset_Handler)
0x08000000 to 0x0801FFFF 128K isr vector, startup code, firmware, no config! // FLASH_Sector_0
*/
/*
/*
For H7 EXFL (External Flash) targets a binary is built that is placed on an external device.
The bootloader will enable the memory mapped mode on the CPU which allows code to run directly from
@ -61,7 +61,7 @@ MEMORY
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
OCTOSPI2 (rx) : ORIGIN = 0x70000000, LENGTH = 256M
OCTOSPI1 (rx) : ORIGIN = 0x90000000, LENGTH = 256M
OCTOSPI1 (rx) : ORIGIN = 0x90000000, LENGTH = 256M
OCTOSPI1_CODE (rx): ORIGIN = ORIGIN(OCTOSPI1) + 1M, LENGTH = 1M - _exst_hash_size /* hard coded start address, as required by SPRACINGH7 boot loader, don't change! */
EXST_HASH (rx) : ORIGIN = ORIGIN(OCTOSPI1_CODE) + LENGTH(OCTOSPI1_CODE), LENGTH = _exst_hash_size
}
@ -112,7 +112,7 @@ SECTIONS
_edmaram = .;
_dmaram_end__ = _edmaram;
} >RAM
.DMA_RW_D2 (NOLOAD) :
{
. = ALIGN(32);
@ -140,4 +140,3 @@ SECTIONS
INCLUDE "stm32_h723_common_post.ld"
INCLUDE "stm32_ram_h723_exst_post.ld"

6
src/link/stm32_ram_h723_exst_post.ld
View file

@ -11,12 +11,12 @@ SECTIONS
BYTE(0x00); /* Checksum method, 0x00 = MD5 hash */
BYTE(0x00); /* Reserved */
BYTE(0x00); /* Reserved */
/* Fill the last 60 bytes with data, including an empty hash aligned */
/* to the last 16 bytes. */
FILL(0x00000000); /* Reserved */
. = ORIGIN(EXST_HASH) + LENGTH(EXST_HASH) - 16;
__md5_hash_address__ = .;
LONG(0x00000000);

7
src/link/stm32_ram_h730_exst.ld
View file

@ -30,7 +30,7 @@ ENTRY(Reset_Handler)
0x08000000 to 0x0801FFFF 128K isr vector, startup code, firmware, no config! // FLASH_Sector_0
*/
/*
/*
For H7 EXFL (External Flash) targets a binary is built that is placed on an external device.
The bootloader will enable the memory mapped mode on the CPU which allows code to run directly from
@ -61,7 +61,7 @@ MEMORY
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
OCTOSPI2 (rx) : ORIGIN = 0x70000000, LENGTH = 256M
OCTOSPI1 (rx) : ORIGIN = 0x90000000, LENGTH = 256M
OCTOSPI1 (rx) : ORIGIN = 0x90000000, LENGTH = 256M
OCTOSPI1_CODE (rx): ORIGIN = ORIGIN(OCTOSPI1) + 1M, LENGTH = 1M - _exst_hash_size /* hard coded start address, as required by SPRACINGH7 boot loader, don't change! */
EXST_HASH (rx) : ORIGIN = ORIGIN(OCTOSPI1_CODE) + LENGTH(OCTOSPI1_CODE), LENGTH = _exst_hash_size
}
@ -112,7 +112,7 @@ SECTIONS
_edmaram = .;
_dmaram_end__ = _edmaram;
} >RAM
.DMA_RW_D2 (NOLOAD) :
{
. = ALIGN(32);
@ -140,4 +140,3 @@ SECTIONS
INCLUDE "stm32_h730_common_post.ld"
INCLUDE "stm32_ram_h730_exst_post.ld"

6
src/link/stm32_ram_h730_exst_post.ld
View file

@ -11,12 +11,12 @@ SECTIONS
BYTE(0x00); /* Checksum method, 0x00 = MD5 hash */
BYTE(0x00); /* Reserved */
BYTE(0x00); /* Reserved */
/* Fill the last 60 bytes with data, including an empty hash aligned */
/* to the last 16 bytes. */
FILL(0x00000000); /* Reserved */
. = ORIGIN(EXST_HASH) + LENGTH(EXST_HASH) - 16;
__md5_hash_address__ = .;
LONG(0x00000000);

20
src/link/stm32_ram_h743.ld
View file

@ -102,24 +102,24 @@ SECTIONS
} >RAM
/* Critical program code goes into ITCM RAM */
/* Copy specific fast-executing code to ITCM RAM */
tcm_code = LOADADDR(.tcm_code);
/* Copy specific fast-executing code to ITCM RAM */
tcm_code = LOADADDR(.tcm_code);
.tcm_code :
{
. = ALIGN(4);
tcm_code_start = .;
tcm_code_start = .;
*(.tcm_code)
*(.tcm_code*)
. = ALIGN(4);
tcm_code_end = .;
tcm_code_end = .;
} >ITCM_RAM
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >RAM
.ARM :
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*) __exidx_end = .;
@ -132,7 +132,7 @@ SECTIONS
KEEP (*(SORT(.pg_registry.*)))
PROVIDE_HIDDEN (__pg_registry_end = .);
} >RAM
.pg_resetdata :
{
PROVIDE_HIDDEN (__pg_resetdata_start = .);

9
src/link/stm32_ram_h750_exst.ld
View file

@ -31,7 +31,7 @@ ENTRY(Reset_Handler)
0x08000000 to 0x0801FFFF 128K isr vector, startup code, firmware, no config! // FLASH_Sector_0
*/
/*
/*
For H7 EXST (External Storage) targets a binary is built that is placed on an external device.
The bootloader will then copy this entire binary to RAM, at the CODE_RAM address. The bootloader
@ -46,7 +46,7 @@ to ram and one section for the main code. e.g. one file for .tcm_code, one file
one for the main code/data, then load each to the appropriate address and adjust the usual startup
code which will no-longer need to duplicate code/data sections from RAM to ITCM/DTCM RAM.
The initial CODE_RAM is sized at 448K to enable all firmware features and to as much RAM free as
The initial CODE_RAM is sized at 448K to enable all firmware features and to as much RAM free as
possible.
*/
@ -66,7 +66,7 @@ MEMORY
D2_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 256K /* SRAM1 + SRAM2 */
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
QUADSPI (rx) : ORIGIN = 0x90000000, LENGTH = 0K
QUADSPI (rx) : ORIGIN = 0x90000000, LENGTH = 0K
}
REGION_ALIAS("STACKRAM", DTCM_RAM)
@ -113,7 +113,7 @@ SECTIONS
_edmaram = .;
_dmaram_end__ = _edmaram;
} >RAM
.DMA_RW_D2 (NOLOAD) :
{
. = ALIGN(32);
@ -141,4 +141,3 @@ SECTIONS
INCLUDE "stm32_h750_common_post.ld"
INCLUDE "stm32_ram_h750_exst_post.ld"

6
src/link/stm32_ram_h750_exst_post.ld
View file

@ -11,12 +11,12 @@ SECTIONS
BYTE(0x00); /* Checksum method, 0x00 = MD5 hash */
BYTE(0x00); /* Reserved */
BYTE(0x00); /* Reserved */
/* Fill the last 60 bytes with data, including an empty hash aligned */
/* to the last 16 bytes. */
FILL(0x00000000); /* Reserved */
. = ORIGIN(EXST_HASH) + LENGTH(EXST_HASH) - 16;
__md5_hash_address__ = .;
LONG(0x00000000);