diff --git a/Makefile b/Makefile
index 7957806296..506e4db4d9 100644
--- a/Makefile
+++ b/Makefile
@@ -183,7 +183,7 @@ STM32F3DISCOVERY_SRC	 = startup_stm32f30x_md_gcc.S \
 		   drivers/adc_common.c \
 		   drivers/bus_i2c_stm32f30x.c \
 		   drivers/bus_spi.c \
-		   drivers/gpio_stm32f10x.c \
+		   drivers/gpio_stm32f30x.c \
 		   drivers/pwm_common.c \
 		   drivers/serial_uart_stm32f30x.c \
 		   drivers/serial_softserial.c \
diff --git a/src/drivers/gpio_stm32f10x.c b/src/drivers/gpio_stm32f10x.c
index b6a1e6338b..01e8890449 100644
--- a/src/drivers/gpio_stm32f10x.c
+++ b/src/drivers/gpio_stm32f10x.c
@@ -8,10 +8,41 @@
 
 void gpioInit(GPIO_TypeDef *gpio, gpio_config_t *config)
 {
-    // FIXME implement
+    uint32_t pinpos;
+    for (pinpos = 0; pinpos < 16; pinpos++) {
+        // are we doing this pin?
+        if (config->pin & (0x1 << pinpos)) {
+            // reference CRL or CRH, depending whether pin number is 0..7 or 8..15
+            __IO uint32_t *cr = &gpio->CRL + (pinpos / 8);
+            // mask out extra bits from pinmode, leaving just CNF+MODE
+            uint32_t currentmode = config->mode & 0x0F;
+            // offset to CNF and MODE portions of CRx register
+            uint32_t shift = (pinpos % 8) * 4;
+            // Read out current CRx value
+            uint32_t tmp = *cr;
+            // if we're in output mode, add speed too.
+            if (config->mode & 0x10)
+                currentmode |= config->speed;
+            // Mask out 4 bits
+            tmp &= ~(0xF << shift);
+            // apply current pinmode
+            tmp |= currentmode << shift;
+            *cr = tmp;
+            // Special handling for IPD/IPU
+            if (config->mode == Mode_IPD) {
+                gpio->ODR &= ~(1U << pinpos);
+            } else if (config->mode == Mode_IPU) {
+                gpio->ODR |= (1U << pinpos);
+            }
+        }
+    }
 }
 
 void gpioExtiLineConfig(uint8_t portsrc, uint8_t pinsrc)
 {
-    // FIXME needed? implement?
+    uint32_t tmp = 0x00;
+
+    tmp = ((uint32_t)0x0F) << (0x04 * (pinsrc & (uint8_t)0x03));
+    AFIO->EXTICR[pinsrc >> 0x02] &= ~tmp;
+    AFIO->EXTICR[pinsrc >> 0x02] |= (((uint32_t)portsrc) << (0x04 * (pinsrc & (uint8_t)0x03)));
 }
diff --git a/src/drivers/gpio_stm32f30x.c b/src/drivers/gpio_stm32f30x.c
index 01e8890449..b6a1e6338b 100644
--- a/src/drivers/gpio_stm32f30x.c
+++ b/src/drivers/gpio_stm32f30x.c
@@ -8,41 +8,10 @@
 
 void gpioInit(GPIO_TypeDef *gpio, gpio_config_t *config)
 {
-    uint32_t pinpos;
-    for (pinpos = 0; pinpos < 16; pinpos++) {
-        // are we doing this pin?
-        if (config->pin & (0x1 << pinpos)) {
-            // reference CRL or CRH, depending whether pin number is 0..7 or 8..15
-            __IO uint32_t *cr = &gpio->CRL + (pinpos / 8);
-            // mask out extra bits from pinmode, leaving just CNF+MODE
-            uint32_t currentmode = config->mode & 0x0F;
-            // offset to CNF and MODE portions of CRx register
-            uint32_t shift = (pinpos % 8) * 4;
-            // Read out current CRx value
-            uint32_t tmp = *cr;
-            // if we're in output mode, add speed too.
-            if (config->mode & 0x10)
-                currentmode |= config->speed;
-            // Mask out 4 bits
-            tmp &= ~(0xF << shift);
-            // apply current pinmode
-            tmp |= currentmode << shift;
-            *cr = tmp;
-            // Special handling for IPD/IPU
-            if (config->mode == Mode_IPD) {
-                gpio->ODR &= ~(1U << pinpos);
-            } else if (config->mode == Mode_IPU) {
-                gpio->ODR |= (1U << pinpos);
-            }
-        }
-    }
+    // FIXME implement
 }
 
 void gpioExtiLineConfig(uint8_t portsrc, uint8_t pinsrc)
 {
-    uint32_t tmp = 0x00;
-
-    tmp = ((uint32_t)0x0F) << (0x04 * (pinsrc & (uint8_t)0x03));
-    AFIO->EXTICR[pinsrc >> 0x02] &= ~tmp;
-    AFIO->EXTICR[pinsrc >> 0x02] |= (((uint32_t)portsrc) << (0x04 * (pinsrc & (uint8_t)0x03)));
+    // FIXME needed? implement?
 }