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[G4] timer support
This commit is contained in:
jflyper
parent
30bf9e809f
commit
fb1be68a8a
4 changed files with 540 additions and 27 deletions
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@ -37,22 +37,7 @@
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typedef uint16_t captureCompare_t; // 16 bit on both 103 and 303, just register access must be 32bit sometimes (use timCCR_t)
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#if defined(STM32F4)
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typedef uint32_t timCCR_t;
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typedef uint32_t timCCER_t;
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typedef uint32_t timSR_t;
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typedef uint32_t timCNT_t;
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#elif defined(STM32F7)
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typedef uint32_t timCCR_t;
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typedef uint32_t timCCER_t;
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typedef uint32_t timSR_t;
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typedef uint32_t timCNT_t;
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#elif defined(STM32F3)
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typedef uint32_t timCCR_t;
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typedef uint32_t timCCER_t;
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typedef uint32_t timSR_t;
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typedef uint32_t timCNT_t;
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#elif defined(STM32H7)
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#if defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) || defined(UNIT_TEST) || defined(SIMULATOR_BUILD)
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typedef uint32_t timCCR_t;
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typedef uint32_t timCCER_t;
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typedef uint32_t timSR_t;
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@ -62,11 +47,6 @@ typedef uint16_t timCCR_t;
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typedef uint16_t timCCER_t;
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typedef uint16_t timSR_t;
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typedef uint16_t timCNT_t;
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#elif defined(UNIT_TEST) || defined(SIMULATOR_BUILD)
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typedef uint32_t timCCR_t;
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typedef uint32_t timCCER_t;
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typedef uint32_t timSR_t;
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typedef uint32_t timCNT_t;
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#else
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#error "Unknown CPU defined"
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#endif
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@ -111,25 +91,25 @@ typedef struct timerHardware_s {
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uint8_t channel;
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timerUsageFlag_e usageFlags;
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uint8_t output;
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#if defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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#if defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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uint8_t alternateFunction;
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#endif
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#if defined(USE_TIMER_DMA)
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#if defined(USE_DMA_SPEC)
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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dmaResource_t *dmaRefConfigured;
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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uint32_t dmaChannelConfigured;
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#endif
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#else // USE_DMA_SPEC
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dmaResource_t *dmaRef;
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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uint32_t dmaChannel; // XXX Can be much smaller (e.g. uint8_t)
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#endif
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#endif // USE_DMA_SPEC
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dmaResource_t *dmaTimUPRef;
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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uint32_t dmaTimUPChannel;
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#endif
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uint8_t dmaTimUPIrqHandler;
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@ -161,6 +141,9 @@ typedef enum {
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#elif defined(STM32H7)
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#define HARDWARE_TIMER_DEFINITION_COUNT 17
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#define TIMUP_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(15) | BIT(16) | BIT(17) )
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#elif defined(STM32G4)
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#define HARDWARE_TIMER_DEFINITION_COUNT 12
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#define TIMUP_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(15) | BIT(16) | BIT(17) )
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#endif
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#define MHZ_TO_HZ(x) ((x) * 1000000)
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@ -191,6 +174,10 @@ extern const timerHardware_t timerHardware[];
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#define FULL_TIMER_CHANNEL_COUNT 87
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#elif defined(STM32G4)
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#define FULL_TIMER_CHANNEL_COUNT 91 // XXX Need review
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#endif
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extern const timerHardware_t fullTimerHardware[];
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@ -218,6 +205,10 @@ extern const timerHardware_t fullTimerHardware[];
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#define USED_TIMERS ( TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(5) | TIM_N(6) | TIM_N(7) | TIM_N(8) | TIM_N(12) | TIM_N(13) | TIM_N(14) | TIM_N(15) | TIM_N(16) | TIM_N(17) )
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#elif defined(STM32G4)
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#define USED_TIMERS ( TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(5) | TIM_N(6) | TIM_N(7) | TIM_N(8) | TIM_N(15) | TIM_N(16) | TIM_N(17) | TIM_N(20) )
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#else
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#error "No timer / channel tag definition found for CPU"
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#endif
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@ -41,10 +41,16 @@
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#define BTCH_TIM1_CH1N BTCH_TIM1_CH1
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#define BTCH_TIM1_CH2N BTCH_TIM1_CH2
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#define BTCH_TIM1_CH3N BTCH_TIM1_CH3
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#ifdef STM32G4
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#define BTCH_TIM1_CH4N BTCH_TIM1_CH4
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#endif
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#define BTCH_TIM8_CH1N BTCH_TIM8_CH1
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#define BTCH_TIM8_CH2N BTCH_TIM8_CH2
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#define BTCH_TIM8_CH3N BTCH_TIM8_CH3
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#ifdef STM32G4
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#define BTCH_TIM8_CH4N BTCH_TIM8_CH4
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#endif
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#define BTCH_TIM20_CH1N BTCH_TIM20_CH1
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#define BTCH_TIM20_CH2N BTCH_TIM20_CH2
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@ -65,6 +71,9 @@
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#define DEF_TIM_CH__CH_CH1N D(1, 1)
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#define DEF_TIM_CH__CH_CH2N D(2, 1)
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#define DEF_TIM_CH__CH_CH3N D(3, 1)
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#ifdef STM32G4
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#define DEF_TIM_CH__CH_CH4N D(4, 1)
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#endif
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// timer table D(tim_n)
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#define DEF_TIM_TIM_GET(tim) CONCAT2(DEF_TIM_TIM__, tim)
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@ -1014,6 +1023,289 @@
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#define DEF_TIM_AF__PI6__TCH_TIM8_CH2 D(3, 8)
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#define DEF_TIM_AF__PI7__TCH_TIM8_CH3 D(3, 8)
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#elif defined(STM32G4)
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// Missing from FW1.0.0 library?
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#define GPIO_AF12_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
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#define DEF_TIM(tim, chan, pin, flags, out, dmaopt, upopt) { \
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tim, \
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TIMER_GET_IO_TAG(pin), \
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DEF_TIM_CHANNEL(CH_ ## chan), \
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flags, \
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(DEF_TIM_OUTPUT(CH_ ## chan) | out), \
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DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
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DEF_TIM_DMA_COND(/* add comma */ , \
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DEF_TIM_DMA_CHANNEL(dmaopt, TCH_## tim ## _ ## chan), \
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DEF_TIM_DMA_REQUEST(TCH_## tim ## _ ## chan) \
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) \
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DEF_TIM_DMA_COND(/* add comma */ , \
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DEF_TIM_DMA_CHANNEL(upopt, TCH_## tim ## _UP), \
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DEF_TIM_DMA_REQUEST(TCH_## tim ## _UP), \
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DEF_TIM_DMA_HANDLER(upopt, TCH_## tim ## _UP) \
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) \
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} \
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/**/
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#define DEF_TIM_CHANNEL(ch) CONCAT(DEF_TIM_CHANNEL__, DEF_TIM_CH_GET(ch))
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#define DEF_TIM_CHANNEL__D(chan_n, n_channel) TIM_CHANNEL_ ## chan_n
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#define DEF_TIM_AF(timch, pin) CONCAT(DEF_TIM_AF__, DEF_TIM_AF_GET(timch, pin))
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#define DEF_TIM_AF__D(af_n, tim_n) GPIO_AF ## af_n ## _TIM ## tim_n
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#define DEF_TIM_DMA_CHANNEL(variant, timch) \
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CONCAT(DEF_TIM_DMA_CHANNEL__, DEF_TIM_DMA_GET(variant, timch))
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#define DEF_TIM_DMA_CHANNEL__D(dma_n, channel_n) (dmaResource_t *)DMA ## dma_n ## _Channel ## channel_n
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#define DEF_TIM_DMA_CHANNEL__NONE NULL
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// XXX This is awful. There must be some smart way of doing this ...
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#define DEF_TIM_DMA_REQUEST(timch) \
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CONCAT(DEF_TIM_DMA_REQ__, DEF_TIM_TCH2BTCH(timch))
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#define DEF_TIM_DMA_HANDLER(variant, timch) \
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CONCAT(DEF_TIM_DMA_HANDLER__, DEF_TIM_DMA_GET(variant, timch))
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#define DEF_TIM_DMA_HANDLER__D(dma_n, channel_n) DMA ## dma_n ## _CH ## channel_n ## _HANDLER
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#define DEF_TIM_DMA_HANDLER__NONE 0
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/* G4 Channel Mappings */
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// D(DMAx, Stream)
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// G4 has DMAMUX that allow arbitrary assignment of peripherals to streams.
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#define DEF_TIM_DMA_FULL \
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D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), D(1, 8), \
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D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(2, 8)
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#define DEF_TIM_DMA__BTCH_TIM1_CH1 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM1_CH2 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM1_CH3 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM1_CH4 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM2_CH1 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM2_CH2 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM2_CH3 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM2_CH4 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM3_CH1 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM3_CH2 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM3_CH3 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM3_CH4 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM4_CH1 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM4_CH2 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM4_CH3 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM4_CH4 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM5_CH1 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM5_CH2 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM5_CH3 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM5_CH4 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM8_CH1 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM8_CH2 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM8_CH3 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM8_CH4 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM15_CH1 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM15_CH2 NONE
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#define DEF_TIM_DMA__BTCH_TIM16_CH1 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM17_CH1 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM20_CH1 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM20_CH2 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM20_CH3 DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM20_CH4 DEF_TIM_DMA_FULL
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// TIM_UP table
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#define DEF_TIM_DMA__BTCH_TIM1_UP DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM2_UP DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM3_UP DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM4_UP DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM5_UP DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM6_UP DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM7_UP DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM8_UP DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM15_UP DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM16_UP DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM17_UP DEF_TIM_DMA_FULL
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#define DEF_TIM_DMA__BTCH_TIM20_UP DEF_TIM_DMA_FULL
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// TIMx_CHy request table
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// This is not defined in stm32g7xx_hal_timer.h
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#define DMA_REQUEST_NONE 255
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#define DEF_TIM_DMA_REQ__BTCH_TIM1_CH1 DMA_REQUEST_TIM1_CH1
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#define DEF_TIM_DMA_REQ__BTCH_TIM1_CH2 DMA_REQUEST_TIM1_CH2
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#define DEF_TIM_DMA_REQ__BTCH_TIM1_CH3 DMA_REQUEST_TIM1_CH3
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#define DEF_TIM_DMA_REQ__BTCH_TIM1_CH4 DMA_REQUEST_TIM1_CH4
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#define DEF_TIM_DMA_REQ__BTCH_TIM2_CH1 DMA_REQUEST_TIM2_CH1
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#define DEF_TIM_DMA_REQ__BTCH_TIM2_CH2 DMA_REQUEST_TIM2_CH2
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#define DEF_TIM_DMA_REQ__BTCH_TIM2_CH3 DMA_REQUEST_TIM2_CH3
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#define DEF_TIM_DMA_REQ__BTCH_TIM2_CH4 DMA_REQUEST_TIM2_CH4
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#define DEF_TIM_DMA_REQ__BTCH_TIM3_CH1 DMA_REQUEST_TIM3_CH1
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#define DEF_TIM_DMA_REQ__BTCH_TIM3_CH2 DMA_REQUEST_TIM3_CH2
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#define DEF_TIM_DMA_REQ__BTCH_TIM3_CH3 DMA_REQUEST_TIM3_CH3
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#define DEF_TIM_DMA_REQ__BTCH_TIM3_CH4 DMA_REQUEST_TIM3_CH4
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#define DEF_TIM_DMA_REQ__BTCH_TIM4_CH1 DMA_REQUEST_TIM4_CH1
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#define DEF_TIM_DMA_REQ__BTCH_TIM4_CH2 DMA_REQUEST_TIM4_CH2
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#define DEF_TIM_DMA_REQ__BTCH_TIM4_CH3 DMA_REQUEST_TIM4_CH3
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#define DEF_TIM_DMA_REQ__BTCH_TIM4_CH4 DMA_REQUEST_TIM4_CH4
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#define DEF_TIM_DMA_REQ__BTCH_TIM5_CH1 DMA_REQUEST_TIM5_CH1
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#define DEF_TIM_DMA_REQ__BTCH_TIM5_CH2 DMA_REQUEST_TIM5_CH2
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#define DEF_TIM_DMA_REQ__BTCH_TIM5_CH3 DMA_REQUEST_TIM5_CH3
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#define DEF_TIM_DMA_REQ__BTCH_TIM5_CH4 DMA_REQUEST_TIM5_CH4
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#define DEF_TIM_DMA_REQ__BTCH_TIM8_CH1 DMA_REQUEST_TIM8_CH1
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#define DEF_TIM_DMA_REQ__BTCH_TIM8_CH2 DMA_REQUEST_TIM8_CH2
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#define DEF_TIM_DMA_REQ__BTCH_TIM8_CH3 DMA_REQUEST_TIM8_CH3
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#define DEF_TIM_DMA_REQ__BTCH_TIM8_CH4 DMA_REQUEST_TIM8_CH4
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#define DEF_TIM_DMA_REQ__BTCH_TIM15_CH1 DMA_REQUEST_TIM15_CH1
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#define DEF_TIM_DMA_REQ__BTCH_TIM15_CH2 DMA_REQUEST_NONE
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#define DEF_TIM_DMA_REQ__BTCH_TIM16_CH1 DMA_REQUEST_TIM16_CH1
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#define DEF_TIM_DMA_REQ__BTCH_TIM17_CH1 DMA_REQUEST_TIM17_CH1
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#define DEF_TIM_DMA_REQ__BTCH_TIM20_CH1 DMA_REQUEST_TIM20_CH1
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#define DEF_TIM_DMA_REQ__BTCH_TIM20_CH2 DMA_REQUEST_TIM20_CH2
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#define DEF_TIM_DMA_REQ__BTCH_TIM20_CH3 DMA_REQUEST_TIM20_CH3
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#define DEF_TIM_DMA_REQ__BTCH_TIM20_CH4 DMA_REQUEST_TIM20_CH4
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// TIM_UP request table
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#define DEF_TIM_DMA_REQ__BTCH_TIM1_UP DMA_REQUEST_TIM1_UP
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#define DEF_TIM_DMA_REQ__BTCH_TIM2_UP DMA_REQUEST_TIM2_UP
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#define DEF_TIM_DMA_REQ__BTCH_TIM3_UP DMA_REQUEST_TIM3_UP
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#define DEF_TIM_DMA_REQ__BTCH_TIM4_UP DMA_REQUEST_TIM4_UP
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#define DEF_TIM_DMA_REQ__BTCH_TIM5_UP DMA_REQUEST_TIM5_UP
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#define DEF_TIM_DMA_REQ__BTCH_TIM6_UP DMA_REQUEST_TIM6_UP
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#define DEF_TIM_DMA_REQ__BTCH_TIM7_UP DMA_REQUEST_TIM7_UP
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#define DEF_TIM_DMA_REQ__BTCH_TIM8_UP DMA_REQUEST_TIM8_UP
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#define DEF_TIM_DMA_REQ__BTCH_TIM15_UP DMA_REQUEST_TIM15_UP
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#define DEF_TIM_DMA_REQ__BTCH_TIM16_UP DMA_REQUEST_TIM16_UP
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#define DEF_TIM_DMA_REQ__BTCH_TIM17_UP DMA_REQUEST_TIM17_UP
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#define DEF_TIM_DMA_REQ__BTCH_TIM20_UP DMA_REQUEST_TIM20_UP
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// AF table
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//PORTA
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#define DEF_TIM_AF__PA0__TCH_TIM2_CH1 D(1, 2)
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#define DEF_TIM_AF__PA1__TCH_TIM2_CH2 D(1, 2)
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#define DEF_TIM_AF__PA2__TCH_TIM2_CH3 D(1, 2)
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#define DEF_TIM_AF__PA3__TCH_TIM2_CH4 D(1, 2)
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#define DEF_TIM_AF__PA5__TCH_TIM2_CH1 D(1, 2)
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#define DEF_TIM_AF__PA6__TCH_TIM16_CH1 D(1, 16)
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#define DEF_TIM_AF__PA7__TCH_TIM17_CH1 D(1, 17)
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#define DEF_TIM_AF__PA12__TCH_TIM16_CH1 D(1, 16)
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#define DEF_TIM_AF__PA13__TCH_TIM16_CH1N D(1, 16)
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#define DEF_TIM_AF__PA15__TCH_TIM2_CH1 D(1, 2)
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#define DEF_TIM_AF__PA0__TCH_TIM5_CH1 D(2, 5)
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#define DEF_TIM_AF__PA1__TCH_TIM5_CH2 D(2, 5)
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#define DEF_TIM_AF__PA2__TCH_TIM5_CH3 D(2, 5)
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#define DEF_TIM_AF__PA3__TCH_TIM5_CH4 D(2, 5)
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#define DEF_TIM_AF__PA4__TCH_TIM3_CH2 D(2, 3)
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#define DEF_TIM_AF__PA6__TCH_TIM3_CH1 D(2, 3)
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#define DEF_TIM_AF__PA7__TCH_TIM3_CH2 D(2, 3)
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#define DEF_TIM_AF__PA15__TCH_TIM8_CH1 D(2, 8)
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#define DEF_TIM_AF__PA7__TCH_TIM8_CH1N D(4, 8)
|
||||
|
||||
#define DEF_TIM_AF__PA7__TCH_TIM1_CH1N D(6, 1)
|
||||
#define DEF_TIM_AF__PA8__TCH_TIM1_CH1 D(6, 1)
|
||||
#define DEF_TIM_AF__PA9__TCH_TIM1_CH2 D(6, 1)
|
||||
#define DEF_TIM_AF__PA10__TCH_TIM1_CH3 D(6, 1)
|
||||
#define DEF_TIM_AF__PA11__TCH_TIM1_CH1N D(6, 1)
|
||||
#define DEF_TIM_AF__PA12__TCH_TIM1_CH2N D(6, 1)
|
||||
|
||||
#define DEF_TIM_AF__PA1__TCH_TIM15_CH1N D(9, 15)
|
||||
#define DEF_TIM_AF__PA2__TCH_TIM15_CH1 D(9, 15)
|
||||
#define DEF_TIM_AF__PA3__TCH_TIM15_CH2 D(9, 15)
|
||||
|
||||
#define DEF_TIM_AF__PA9__TCH_TIM2_CH3 D(10, 2)
|
||||
#define DEF_TIM_AF__PA10__TCH_TIM2_CH4 D(10, 2)
|
||||
#define DEF_TIM_AF__PA11__TCH_TIM4_CH1 D(10, 4)
|
||||
#define DEF_TIM_AF__PA12__TCH_TIM4_CH2 D(10, 4)
|
||||
#define DEF_TIM_AF__PA13__TCH_TIM4_CH3 D(10, 4)
|
||||
|
||||
#define DEF_TIM_AF__PA11__TCH_TIM1_CH4 D(11, 1)
|
||||
|
||||
//PORTB
|
||||
#define DEF_TIM_AF__PB3__TCH_TIM2_CH2 D(1, 2)
|
||||
#define DEF_TIM_AF__PB4__TCH_TIM16_CH1 D(1, 16)
|
||||
#define DEF_TIM_AF__PB6__TCH_TIM16_CH1N D(1, 16)
|
||||
#define DEF_TIM_AF__PB7__TCH_TIM17_CH1N D(1, 17)
|
||||
#define DEF_TIM_AF__PB8__TCH_TIM16_CH1 D(1, 16)
|
||||
#define DEF_TIM_AF__PB9__TCH_TIM17_CH1 D(1, 17)
|
||||
#define DEF_TIM_AF__PB10__TCH_TIM2_CH3 D(1, 2)
|
||||
#define DEF_TIM_AF__PB11__TCH_TIM2_CH4 D(1, 2)
|
||||
#define DEF_TIM_AF__PB14__TCH_TIM15_CH1 D(1, 15)
|
||||
#define DEF_TIM_AF__PB15__TCH_TIM15_CH2 D(1, 15)
|
||||
|
||||
#define DEF_TIM_AF__PB0__TCH_TIM3_CH3 D(2, 3)
|
||||
#define DEF_TIM_AF__PB1__TCH_TIM3_CH4 D(2, 3)
|
||||
#define DEF_TIM_AF__PB2__TCH_TIM5_CH1 D(2, 5)
|
||||
#define DEF_TIM_AF__PB4__TCH_TIM3_CH1 D(2, 3)
|
||||
#define DEF_TIM_AF__PB5__TCH_TIM3_CH2 D(2, 3)
|
||||
#define DEF_TIM_AF__PB6__TCH_TIM4_CH1 D(2, 4)
|
||||
#define DEF_TIM_AF__PB7__TCH_TIM4_CH2 D(2, 4)
|
||||
#define DEF_TIM_AF__PB8__TCH_TIM4_CH3 D(2, 4)
|
||||
#define DEF_TIM_AF__PB9__TCH_TIM4_CH4 D(2, 4)
|
||||
#define DEF_TIM_AF__PB15__TCH_TIM15_CH1N D(2, 15)
|
||||
|
||||
#define DEF_TIM_AF__PB2__TCH_TIM20_CH1 D(3, 20)
|
||||
#define DEF_TIM_AF__PB5__TCH_TIM8_CH3N D(3, 8)
|
||||
|
||||
#define DEF_TIM_AF__PB0__TCH_TIM8_CH2N D(4, 8)
|
||||
#define DEF_TIM_AF__PB1__TCH_TIM8_CH3N D(4, 8)
|
||||
#define DEF_TIM_AF__PB3__TCH_TIM8_CH1N D(4, 8)
|
||||
#define DEF_TIM_AF__PB4__TCH_TIM8_CH2N D(4, 8)
|
||||
#define DEF_TIM_AF__PB15__TCH_TIM1_CH3N D(4, 1)
|
||||
|
||||
#define DEF_TIM_AF__PB0__TCH_TIM1_CH2N D(6, 1)
|
||||
#define DEF_TIM_AF__PB0__TCH_TIM1_CH3N D(6, 1)
|
||||
#define DEF_TIM_AF__PB13__TCH_TIM1_CH1N D(6, 1)
|
||||
#define DEF_TIM_AF__PB14__TCH_TIM1_CH2N D(6, 1)
|
||||
|
||||
#define DEF_TIM_AF__PB5__TCH_TIM17_CH1 D(10, 17)
|
||||
#define DEF_TIM_AF__PB7__TCH_TIM3_CH4 D(10, 3)
|
||||
#define DEF_TIM_AF__PB8__TCH_TIM8_CH2 D(10, 8)
|
||||
#define DEF_TIM_AF__PB9__TCH_TIM8_CH3 D(10, 8)
|
||||
|
||||
#define DEF_TIM_AF__PB9__TCH_TIM1_CH3N D(12, 1)
|
||||
|
||||
//PORTC
|
||||
#define DEF_TIM_AF__PC12__TCH_TIM5_CH2 D(1, 5)
|
||||
|
||||
#define DEF_TIM_AF__PC0__TCH_TIM1_CH1 D(2, 1)
|
||||
#define DEF_TIM_AF__PC1__TCH_TIM1_CH2 D(2, 1)
|
||||
#define DEF_TIM_AF__PC2__TCH_TIM1_CH3 D(2, 1)
|
||||
#define DEF_TIM_AF__PC3__TCH_TIM1_CH4 D(2, 1)
|
||||
#define DEF_TIM_AF__PC6__TCH_TIM3_CH1 D(2, 3)
|
||||
#define DEF_TIM_AF__PC7__TCH_TIM3_CH2 D(2, 3)
|
||||
#define DEF_TIM_AF__PC8__TCH_TIM3_CH3 D(2, 3)
|
||||
#define DEF_TIM_AF__PC9__TCH_TIM3_CH4 D(2, 3)
|
||||
|
||||
#define DEF_TIM_AF__PC6__TCH_TIM8_CH1 D(4, 8)
|
||||
#define DEF_TIM_AF__PC7__TCH_TIM8_CH2 D(4, 8)
|
||||
#define DEF_TIM_AF__PC8__TCH_TIM8_CH3 D(4, 8)
|
||||
#define DEF_TIM_AF__PC9__TCH_TIM8_CH4 D(4, 8)
|
||||
#define DEF_TIM_AF__PC10__TCH_TIM8_CH1N D(4, 8)
|
||||
#define DEF_TIM_AF__PC11__TCH_TIM8_CH2N D(4, 8)
|
||||
#define DEF_TIM_AF__PC12__TCH_TIM8_CH3N D(4, 8)
|
||||
#define DEF_TIM_AF__PC13__TCH_TIM1_CH1N D(4, 1)
|
||||
|
||||
#define DEF_TIM_AF__PC2__TCH_TIM20_CH2 D(6, 20)
|
||||
#define DEF_TIM_AF__PC5__TCH_TIM1_CH4N D(6, 1)
|
||||
#define DEF_TIM_AF__PC8__TCH_TIM20_CH3 D(6, 20)
|
||||
#define DEF_TIM_AF__PC13__TCH_TIM8_CH4N D(6, 8)
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -140,6 +140,9 @@ static uint8_t lookupTimerIndex(const TIM_TypeDef *tim)
|
|||
#endif
|
||||
#if USED_TIMERS & TIM_N(17)
|
||||
_CASE(17);
|
||||
#endif
|
||||
#if USED_TIMERS & TIM_N(20)
|
||||
_CASE(20);
|
||||
#endif
|
||||
default: return ~1; // make sure final index is out of range
|
||||
}
|
||||
|
|
@ -174,7 +177,7 @@ TIM_TypeDef * const usedTimers[USED_TIMER_COUNT] = {
|
|||
#if USED_TIMERS & TIM_N(8)
|
||||
_DEF(8),
|
||||
#endif
|
||||
#if !defined(STM32H7)
|
||||
#if !(defined(STM32H7) || defined(STM32G4))
|
||||
#if USED_TIMERS & TIM_N(9)
|
||||
_DEF(9),
|
||||
#endif
|
||||
|
|
@ -185,6 +188,7 @@ TIM_TypeDef * const usedTimers[USED_TIMER_COUNT] = {
|
|||
_DEF(11),
|
||||
#endif
|
||||
#endif
|
||||
#if !defined(STM32G4)
|
||||
#if USED_TIMERS & TIM_N(12)
|
||||
_DEF(12),
|
||||
#endif
|
||||
|
|
@ -194,6 +198,7 @@ TIM_TypeDef * const usedTimers[USED_TIMER_COUNT] = {
|
|||
#if USED_TIMERS & TIM_N(14)
|
||||
_DEF(14),
|
||||
#endif
|
||||
#endif
|
||||
#if USED_TIMERS & TIM_N(15)
|
||||
_DEF(15),
|
||||
#endif
|
||||
|
|
@ -203,6 +208,11 @@ TIM_TypeDef * const usedTimers[USED_TIMER_COUNT] = {
|
|||
#if USED_TIMERS & TIM_N(17)
|
||||
_DEF(17),
|
||||
#endif
|
||||
#if defined(STM32G4)
|
||||
#if USED_TIMERS & TIM_N(20)
|
||||
_DEF(20),
|
||||
#endif
|
||||
#endif
|
||||
#undef _DEF
|
||||
};
|
||||
|
||||
|
|
@ -261,6 +271,9 @@ const int8_t timerNumbers[USED_TIMER_COUNT] = {
|
|||
#if USED_TIMERS & TIM_N(17)
|
||||
_DEF(17),
|
||||
#endif
|
||||
#if USED_TIMERS & TIM_N(20)
|
||||
_DEF(20),
|
||||
#endif
|
||||
#undef _DEF
|
||||
};
|
||||
|
||||
|
|
@ -347,7 +360,7 @@ void configTimeBase(TIM_TypeDef *tim, uint16_t period, uint32_t hz)
|
|||
|
||||
HAL_TIM_Base_Init(&timerHandle[timerIndex].Handle);
|
||||
if (tim == TIM1 || tim == TIM2 || tim == TIM3 || tim == TIM4 || tim == TIM5 || tim == TIM8
|
||||
#if !defined(STM32H7)
|
||||
#if !(defined(STM32H7) || defined(STM32G4))
|
||||
|| tim == TIM9
|
||||
#endif
|
||||
) {
|
||||
|
|
@ -390,12 +403,18 @@ void timerConfigure(const timerHardware_t *timerHardwarePtr, uint16_t period, ui
|
|||
timerNVICConfigure(TIM1_UP_TIM10_IRQn);
|
||||
#elif defined(STM32H7)
|
||||
timerNVICConfigure(TIM1_UP_IRQn);
|
||||
#elif defined(STM32G4)
|
||||
timerNVICConfigure(TIM1_UP_TIM16_IRQn);
|
||||
#else
|
||||
// Empty
|
||||
#endif
|
||||
break;
|
||||
case TIM8_CC_IRQn:
|
||||
#if defined(STM32G4)
|
||||
timerNVICConfigure(TIM8_UP_IRQn);
|
||||
#else
|
||||
timerNVICConfigure(TIM8_UP_TIM13_IRQn);
|
||||
#endif
|
||||
break;
|
||||
|
||||
}
|
||||
|
|
@ -783,6 +802,12 @@ static void timCCxHandler(TIM_TypeDef *tim, timerConfig_t *timerConfig)
|
|||
_TIM_IRQ_HANDLER(TIM1_CC_IRQHandler, 1);
|
||||
# if defined(STM32H7)
|
||||
_TIM_IRQ_HANDLER(TIM1_UP_IRQHandler, 1);
|
||||
# elif defined(STM32G4)
|
||||
# if USED_TIMERS & TIM_N(16)
|
||||
_TIM_IRQ_HANDLER2(TIM1_UP_TIM16_IRQHandler, 1, 16); // both timers are in use
|
||||
# else
|
||||
_TIM_IRQ_HANDLER(TIM1_UP_TIM16_IRQHandler, 1); // timer16 is not used timers are in use
|
||||
# endif
|
||||
# else
|
||||
# if USED_TIMERS & TIM_N(10)
|
||||
_TIM_IRQ_HANDLER2(TIM1_UP_TIM10_IRQHandler, 1, 10); // both timers are in use
|
||||
|
|
@ -807,6 +832,9 @@ _TIM_IRQ_HANDLER(TIM5_IRQHandler, 5);
|
|||
|
||||
#if USED_TIMERS & TIM_N(8)
|
||||
_TIM_IRQ_HANDLER(TIM8_CC_IRQHandler, 8);
|
||||
# if defined(STM32G4)
|
||||
_TIM_IRQ_HANDLER(TIM8_UP_IRQHandler, 8);
|
||||
# endif
|
||||
|
||||
# if USED_TIMERS & TIM_N(13)
|
||||
_TIM_IRQ_HANDLER2(TIM8_UP_TIM13_IRQHandler, 8, 13); // both timers are in use
|
||||
|
|
@ -833,6 +861,9 @@ _TIM_IRQ_HANDLER(TIM1_UP_TIM16_IRQHandler, 16); // only timer16 is used, not
|
|||
#if USED_TIMERS & TIM_N(17)
|
||||
_TIM_IRQ_HANDLER(TIM1_TRG_COM_TIM17_IRQHandler, 17);
|
||||
#endif
|
||||
#if USED_TIMERS & TIM_N(20)
|
||||
_TIM_IRQ_HANDLER(TIM20_CC_IRQHandler, 20);
|
||||
#endif
|
||||
|
||||
void timerInit(void)
|
||||
{
|
||||
|
|
@ -891,6 +922,9 @@ void timerInit(void)
|
|||
#if USED_TIMERS & TIM_N(17)
|
||||
__HAL_RCC_TIM17_CLK_ENABLE();
|
||||
#endif
|
||||
#if USED_TIMERS & TIM_N(20)
|
||||
__HAL_RCC_TIM20_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
/* enable the timer peripherals */
|
||||
for (int i = 0; i < TIMER_CHANNEL_COUNT; i++) {
|
||||
|
|
|
|||
196
src/main/drivers/timer_stm32g4xx.c
Normal file
196
src/main/drivers/timer_stm32g4xx.c
Normal file
|
|
@ -0,0 +1,196 @@
|
|||
/*
|
||||
* This file is part of Cleanflight and Betaflight.
|
||||
*
|
||||
* Cleanflight and Betaflight are free software. You can redistribute
|
||||
* this software and/or modify this software under the terms of the
|
||||
* GNU General Public License as published by the Free Software
|
||||
* Foundation, either version 3 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* Cleanflight and Betaflight are distributed in the hope that they
|
||||
* will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
* See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this software.
|
||||
*
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "platform.h"
|
||||
|
||||
#ifdef USE_TIMER
|
||||
|
||||
#include "common/utils.h"
|
||||
|
||||
#include "drivers/dma.h"
|
||||
#include "drivers/io.h"
|
||||
#include "drivers/timer_def.h"
|
||||
|
||||
#include "stm32g4xx.h"
|
||||
#include "rcc.h"
|
||||
#include "timer.h"
|
||||
|
||||
|
||||
const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
|
||||
{ .TIMx = TIM1, .rcc = RCC_APB2(TIM1), .inputIrq = TIM1_CC_IRQn},
|
||||
{ .TIMx = TIM2, .rcc = RCC_APB11(TIM2), .inputIrq = TIM2_IRQn},
|
||||
{ .TIMx = TIM3, .rcc = RCC_APB11(TIM3), .inputIrq = TIM3_IRQn},
|
||||
{ .TIMx = TIM4, .rcc = RCC_APB11(TIM4), .inputIrq = TIM4_IRQn},
|
||||
{ .TIMx = TIM5, .rcc = RCC_APB11(TIM5), .inputIrq = TIM5_IRQn},
|
||||
{ .TIMx = TIM6, .rcc = RCC_APB11(TIM6), .inputIrq = 0},
|
||||
{ .TIMx = TIM7, .rcc = RCC_APB11(TIM7), .inputIrq = 0},
|
||||
{ .TIMx = TIM8, .rcc = RCC_APB2(TIM8), .inputIrq = TIM8_CC_IRQn},
|
||||
{ .TIMx = TIM15, .rcc = RCC_APB2(TIM15), .inputIrq = TIM1_BRK_TIM15_IRQn},
|
||||
{ .TIMx = TIM16, .rcc = RCC_APB2(TIM16), .inputIrq = TIM1_UP_TIM16_IRQn},
|
||||
{ .TIMx = TIM17, .rcc = RCC_APB2(TIM17), .inputIrq = TIM1_TRG_COM_TIM17_IRQn},
|
||||
{ .TIMx = TIM20, .rcc = RCC_APB2(TIM20), .inputIrq = TIM20_CC_IRQn},
|
||||
};
|
||||
|
||||
#if defined(USE_TIMER_MGMT)
|
||||
const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
|
||||
// Auto-generated from 'timer_def.h'
|
||||
// Port A
|
||||
DEF_TIM(TIM2, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM2, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM2, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM2, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM2, CH1, PA5, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM16, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM17, CH1, PA7, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM16, CH1, PA12, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM16, CH1N, PA13, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM2, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM5, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM5, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM5, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM5, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM3, CH2, PA4, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM3, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM3, CH2, PA7, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM8, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM1, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH1, PA8, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH2, PA9, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH3, PA10, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH1N, PA11, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH2N, PA12, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM15, CH1N, PA1, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM15, CH1, PA2, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM15, CH2, PA3, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM2, CH3, PA9, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM2, CH4, PA10, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM4, CH1, PA11, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM4, CH2, PA12, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM4, CH3, PA13, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM1, CH4, PA11, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
// Port B
|
||||
DEF_TIM(TIM2, CH2, PB3, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM16, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM16, CH1N, PB6, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM17, CH1N, PB7, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM16, CH1, PB8, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM17, CH1, PB9, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM2, CH3, PB10, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM2, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM15, CH1, PB14, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM15, CH2, PB15, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM3, CH3, PB0, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM3, CH4, PB1, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM5, CH1, PB2, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM3, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM3, CH2, PB5, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM4, CH1, PB6, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM4, CH2, PB7, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM4, CH3, PB8, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM4, CH4, PB9, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM15, CH1N, PB15, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM20, CH1, PB2, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH3N, PB5, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM8, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH1N, PB3, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH2N, PB4, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM1, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH3N, PB0, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH1N, PB13, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM17, CH1, PB5, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM3, CH4, PB7, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH2, PB8, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH3, PB9, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM1, CH3N, PB9, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
// Port C
|
||||
DEF_TIM(TIM5, CH2, PC12, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM1, CH1, PC0, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH2, PC1, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH3, PC2, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH4, PC3, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM3, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM3, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM3, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM3, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM8, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH1N, PC10, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH2N, PC11, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH3N, PC12, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH1N, PC13, TIM_USE_ANY, 0, 0, 0),
|
||||
|
||||
DEF_TIM(TIM20, CH2, PC2, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM1, CH4N, PC5, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM20, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
|
||||
DEF_TIM(TIM8, CH4N, PC13, TIM_USE_ANY, 0, 0, 0),
|
||||
};
|
||||
#endif
|
||||
|
||||
uint32_t timerClock(TIM_TypeDef *tim)
|
||||
{
|
||||
/*
|
||||
* RM0440 Rev.1
|
||||
* 6.2.13 Timer clock
|
||||
* The timer clock frequencies are automatically defined by hardware. There are two cases:
|
||||
* 1. If the APB prescaler equals 1, the timer clock frequencies are set to the same frequency as that of the APB domain.
|
||||
* 2. Otherwise, they are set to twice (×2) the frequency of the APB domain.
|
||||
*/
|
||||
|
||||
uint32_t pclk;
|
||||
|
||||
if (tim == TIM1 || tim == TIM8 || tim == TIM15 || tim == TIM16 || tim == TIM17 || tim == TIM20) {
|
||||
// Timers on APB2; PCLK2
|
||||
pclk = HAL_RCC_GetPCLK2Freq();
|
||||
if (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)) {
|
||||
pclk *= 2;
|
||||
}
|
||||
} else {
|
||||
// Timers on APB1; PCLK1
|
||||
pclk = HAL_RCC_GetPCLK1Freq();
|
||||
if (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)) {
|
||||
pclk *= 2;
|
||||
}
|
||||
}
|
||||
|
||||
return pclk;
|
||||
}
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue