mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-21 15:25:36 +03:00
Configurable UART
This commit is contained in:
jflyper
parent
4ee7a330d6
commit
fdfe9e8af3
15 changed files with 1617 additions and 1604 deletions
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@ -15,6 +15,10 @@
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* jflyper - Refactoring, cleanup and made pin-configurable
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*/
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#include <stdbool.h>
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#include <stdint.h>
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@ -22,219 +26,155 @@
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#include "drivers/system.h"
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#include "drivers/io.h"
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#include "rcc.h"
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#include "drivers/dma.h"
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#include "drivers/nvic.h"
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#include "dma.h"
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#include "drivers/rcc.h"
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#include "serial.h"
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#include "serial_uart.h"
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#include "serial_uart_impl.h"
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#include "drivers/serial.h"
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#include "drivers/serial_uart.h"
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#include "drivers/serial_uart_impl.h"
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#define UART_RX_BUFFER_SIZE 512
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#define UART_TX_BUFFER_SIZE 512
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#ifdef USE_UART
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typedef struct uartDevice_s {
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USART_TypeDef* dev;
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uartPort_t port;
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uint32_t DMAChannel;
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DMA_Stream_TypeDef *txDMAStream;
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DMA_Stream_TypeDef *rxDMAStream;
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ioTag_t rx;
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ioTag_t tx;
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volatile uint8_t rxBuffer[UART_RX_BUFFER_SIZE];
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volatile uint8_t txBuffer[UART_TX_BUFFER_SIZE];
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rccPeriphTag_t rcc_uart;
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uint8_t af;
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uint8_t rxIrq;
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uint32_t txPriority;
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uint32_t rxPriority;
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} uartDevice_t;
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//static uartPort_t uartPort[MAX_UARTS];
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const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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#ifdef USE_UART1
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static uartDevice_t uart1 =
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{
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.DMAChannel = DMA_Channel_4,
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{
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.device = UARTDEV_1,
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.reg = USART1,
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_UART1_RX_DMA
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.rxDMAStream = DMA2_Stream5,
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.rxDMAStream = DMA2_Stream5,
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#endif
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#ifdef USE_UART1_TX_DMA
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.txDMAStream = DMA2_Stream7,
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.txDMAStream = DMA2_Stream7,
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#endif
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.dev = USART1,
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.rx = IO_TAG(UART1_RX_PIN),
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.tx = IO_TAG(UART1_TX_PIN),
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.af = GPIO_AF_USART1,
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.rcc_uart = RCC_APB2(USART1),
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.rxIrq = USART1_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART1_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART1
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};
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.pinPair = {
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{ DEFIO_TAG_E(PA10), DEFIO_TAG_E(PA9) },
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{ DEFIO_TAG_E(PB7), DEFIO_TAG_E(PB6) },
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},
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.af = GPIO_AF_USART1,
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.rcc = RCC_APB2(USART1),
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.irqn = USART1_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART1_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART1
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},
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#endif
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#ifdef USE_UART2
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static uartDevice_t uart2 =
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{
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.DMAChannel = DMA_Channel_4,
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{
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.device = UARTDEV_2,
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.reg = USART2,
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_UART2_RX_DMA
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.rxDMAStream = DMA1_Stream5,
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.rxDMAStream = DMA1_Stream5,
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#endif
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#ifdef USE_UART2_TX_DMA
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.txDMAStream = DMA1_Stream6,
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.txDMAStream = DMA1_Stream6,
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#endif
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.dev = USART2,
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.rx = IO_TAG(UART2_RX_PIN),
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.tx = IO_TAG(UART2_TX_PIN),
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.af = GPIO_AF_USART2,
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.rcc_uart = RCC_APB1(USART2),
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.rxIrq = USART2_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART2_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART2
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};
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.pinPair = {
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{ DEFIO_TAG_E(PA3), DEFIO_TAG_E(PA2) },
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{ DEFIO_TAG_E(PD6), DEFIO_TAG_E(PD5) },
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},
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.af = GPIO_AF_USART2,
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.rcc = RCC_APB1(USART2),
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.irqn = USART2_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART2_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART2
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},
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#endif
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#ifdef USE_UART3
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static uartDevice_t uart3 =
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{
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.DMAChannel = DMA_Channel_4,
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{
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.device = UARTDEV_3,
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.reg = USART3,
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_UART3_RX_DMA
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.rxDMAStream = DMA1_Stream1,
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.rxDMAStream = DMA1_Stream1,
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#endif
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#ifdef USE_UART3_TX_DMA
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.txDMAStream = DMA1_Stream3,
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.txDMAStream = DMA1_Stream3,
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#endif
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.dev = USART3,
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.rx = IO_TAG(UART3_RX_PIN),
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.tx = IO_TAG(UART3_TX_PIN),
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.af = GPIO_AF_USART3,
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.rcc_uart = RCC_APB1(USART3),
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.rxIrq = USART3_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART3_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART3
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};
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.pinPair = {
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{ DEFIO_TAG_E(PB11), DEFIO_TAG_E(PB10) },
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{ DEFIO_TAG_E(PC11), DEFIO_TAG_E(PC10) },
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{ DEFIO_TAG_E(PD9), DEFIO_TAG_E(PD8) }
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},
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.af = GPIO_AF_USART3,
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.rcc = RCC_APB1(USART3),
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.irqn = USART3_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART3_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART3
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},
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#endif
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#ifdef USE_UART4
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static uartDevice_t uart4 =
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{
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.DMAChannel = DMA_Channel_4,
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{
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.device = UARTDEV_4,
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.reg = UART4,
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_UART4_RX_DMA
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.rxDMAStream = DMA1_Stream2,
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.rxDMAStream = DMA1_Stream2,
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#endif
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#ifdef USE_UART4_TX_DMA
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.txDMAStream = DMA1_Stream4,
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.txDMAStream = DMA1_Stream4,
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#endif
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.dev = UART4,
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.rx = IO_TAG(UART4_RX_PIN),
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.tx = IO_TAG(UART4_TX_PIN),
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.af = GPIO_AF_UART4,
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.rcc_uart = RCC_APB1(UART4),
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.rxIrq = UART4_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART4_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART4
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};
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.pinPair = {
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{ DEFIO_TAG_E(PA1), DEFIO_TAG_E(PA0) },
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{ DEFIO_TAG_E(PC11), DEFIO_TAG_E(PC10) },
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},
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.af = GPIO_AF_UART4,
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.rcc = RCC_APB1(UART4),
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.irqn = UART4_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART4_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART4
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},
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#endif
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#ifdef USE_UART5
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static uartDevice_t uart5 =
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{
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.DMAChannel = DMA_Channel_4,
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{
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.device = UARTDEV_5,
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.reg = UART5,
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_UART5_RX_DMA
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.rxDMAStream = DMA1_Stream0,
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.rxDMAStream = DMA1_Stream0,
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#endif
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#ifdef USE_UART5_TX_DMA
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.txDMAStream = DMA1_Stream7,
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.txDMAStream = DMA1_Stream7,
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#endif
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.dev = UART5,
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.rx = IO_TAG(UART5_RX_PIN),
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.tx = IO_TAG(UART5_TX_PIN),
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.af = GPIO_AF_UART5,
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.rcc_uart = RCC_APB1(UART5),
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.rxIrq = UART5_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART5_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART5
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};
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.pinPair = {
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{ DEFIO_TAG_E(PD2), DEFIO_TAG_E(PC12) },
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},
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.af = GPIO_AF_UART5,
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.rcc = RCC_APB1(UART5),
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.irqn = UART5_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART5_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART5
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},
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#endif
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#ifdef USE_UART6
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static uartDevice_t uart6 =
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{
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.DMAChannel = DMA_Channel_5,
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{
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.device = UARTDEV_6,
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.reg = USART6,
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.DMAChannel = DMA_Channel_5,
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#ifdef USE_UART6_RX_DMA
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.rxDMAStream = DMA2_Stream1,
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.rxDMAStream = DMA2_Stream1,
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#endif
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#ifdef USE_UART6_TX_DMA
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.txDMAStream = DMA2_Stream6,
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.txDMAStream = DMA2_Stream6,
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#endif
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.pinPair = {
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{ DEFIO_TAG_E(PC7), DEFIO_TAG_E(PC6) },
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{ DEFIO_TAG_E(PG9), DEFIO_TAG_E(PG14) },
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},
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.af = GPIO_AF_USART6,
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.rcc = RCC_APB2(USART6),
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.irqn = USART6_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART6_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART6
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},
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#endif
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.dev = USART6,
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.rx = IO_TAG(UART6_RX_PIN),
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.tx = IO_TAG(UART6_TX_PIN),
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.af = GPIO_AF_USART6,
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.rcc_uart = RCC_APB2(USART6),
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.rxIrq = USART6_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART6_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART6
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};
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#endif
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static uartDevice_t* uartHardwareMap[] = {
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#ifdef USE_UART1
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&uart1,
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#else
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NULL,
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#endif
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#ifdef USE_UART2
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&uart2,
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#else
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NULL,
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#endif
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#ifdef USE_UART3
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&uart3,
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#else
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NULL,
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#endif
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#ifdef USE_UART4
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&uart4,
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#else
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NULL,
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#endif
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#ifdef USE_UART5
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&uart5,
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#else
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NULL,
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#endif
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#ifdef USE_UART6
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&uart6,
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#else
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NULL,
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#endif
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};
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void uartIrqHandler(uartPort_t *s)
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{
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if (!s->rxDMAStream && (USART_GetITStatus(s->USARTx, USART_IT_RXNE) == SET)) {
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if (s->port.rxCallback) {
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s->port.rxCallback(s->USARTx->DR);
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} else {
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s->port.rxBuffer[s->port.rxBufferHead] = s->USARTx->DR;
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s->port.rxBufferHead = (s->port.rxBufferHead + 1) % s->port.rxBufferSize;
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}
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}
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if (!s->txDMAStream && (USART_GetITStatus(s->USARTx, USART_IT_TXE) == SET)) {
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if (s->port.txBufferTail != s->port.txBufferHead) {
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USART_SendData(s->USARTx, s->port.txBuffer[s->port.txBufferTail]);
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s->port.txBufferTail = (s->port.txBufferTail + 1) % s->port.txBufferSize;
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} else {
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USART_ITConfig(s->USARTx, USART_IT_TXE, DISABLE);
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}
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}
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if (USART_GetITStatus(s->USARTx, USART_FLAG_ORE) == SET)
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{
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USART_ClearITPendingBit (s->USARTx, USART_IT_ORE);
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}
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}
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static void handleUsartTxDma(uartPort_t *s)
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{
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@ -269,14 +209,19 @@ void dmaIRQHandler(dmaChannelDescriptor_t* descriptor)
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}
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}
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// XXX Should serialUART be consolidated?
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uartPort_t *serialUART(UARTDevice device, uint32_t baudRate, portMode_t mode, portOptions_t options)
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{
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uartPort_t *s;
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NVIC_InitTypeDef NVIC_InitStructure;
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uartDevice_t *uart = uartHardwareMap[device];
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uartDevice_t *uart = uartDevmap[device];
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if (!uart) return NULL;
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const uartHardware_t *hardware = uart->hardware;
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if (!hardware) return NULL; // XXX Can't happen !?
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s = &(uart->port);
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s->port.vTable = uartVTable;
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@ -287,54 +232,52 @@ uartPort_t *serialUART(UARTDevice device, uint32_t baudRate, portMode_t mode, po
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s->port.rxBufferSize = sizeof(uart->rxBuffer);
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s->port.txBufferSize = sizeof(uart->txBuffer);
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s->USARTx = uart->dev;
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if (uart->rxDMAStream) {
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s->rxDMAChannel = uart->DMAChannel;
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s->rxDMAStream = uart->rxDMAStream;
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dmaInit(dmaGetIdentifier(uart->rxDMAStream), OWNER_SERIAL_RX, RESOURCE_INDEX(device));
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s->USARTx = hardware->reg;
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if (hardware->rxDMAStream) {
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dmaInit(dmaGetIdentifier(hardware->rxDMAStream), OWNER_SERIAL_RX, RESOURCE_INDEX(device));
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s->rxDMAChannel = hardware->DMAChannel;
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s->rxDMAStream = hardware->rxDMAStream;
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s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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}
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if (uart->txDMAStream) {
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s->txDMAChannel = uart->DMAChannel;
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s->txDMAStream = uart->txDMAStream;
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const dmaIdentifier_e identifier = dmaGetIdentifier(uart->txDMAStream);
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if (hardware->txDMAStream) {
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const dmaIdentifier_e identifier = dmaGetIdentifier(hardware->txDMAStream);
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dmaInit(identifier, OWNER_SERIAL_TX, RESOURCE_INDEX(device));
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// DMA TX Interrupt
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dmaSetHandler(identifier, dmaIRQHandler, uart->txPriority, (uint32_t)uart);
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dmaSetHandler(identifier, dmaIRQHandler, hardware->txPriority, (uint32_t)uart);
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s->txDMAChannel = hardware->DMAChannel;
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s->txDMAStream = hardware->txDMAStream;
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s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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}
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s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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IO_t txIO = IOGetByTag(uart->tx);
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IO_t rxIO = IOGetByTag(uart->rx);
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IO_t tx = IOGetByTag(uart->tx);
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IO_t rx = IOGetByTag(uart->rx);
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if (uart->rcc_uart) {
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RCC_ClockCmd(uart->rcc_uart, ENABLE);
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if (hardware->rcc) {
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RCC_ClockCmd(hardware->rcc, ENABLE);
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}
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if (options & SERIAL_BIDIR) {
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IOInit(tx, OWNER_SERIAL_TX, RESOURCE_INDEX(device));
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if (options & SERIAL_BIDIR_PP)
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IOConfigGPIOAF(tx, IOCFG_AF_PP, uart->af);
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else
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IOConfigGPIOAF(tx, IOCFG_AF_OD, uart->af);
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}
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else {
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if ((mode & MODE_TX) && tx) {
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IOInit(tx, OWNER_SERIAL_TX, RESOURCE_INDEX(device));
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IOConfigGPIOAF(tx, IOCFG_AF_PP_UP, uart->af);
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IOInit(txIO, OWNER_SERIAL_TX, RESOURCE_INDEX(device));
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IOConfigGPIOAF(txIO, (options & SERIAL_BIDIR_PP) ? IOCFG_AF_PP : IOCFG_AF_OD, hardware->af);
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} else {
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if ((mode & MODE_TX) && txIO) {
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IOInit(txIO, OWNER_SERIAL_TX, RESOURCE_INDEX(device));
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IOConfigGPIOAF(txIO, IOCFG_AF_PP_UP, hardware->af);
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}
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if ((mode & MODE_RX) && rx) {
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IOInit(rx, OWNER_SERIAL_RX, RESOURCE_INDEX(device));
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IOConfigGPIOAF(rx, IOCFG_AF_PP_UP, uart->af);
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if ((mode & MODE_RX) && rxIO) {
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IOInit(rxIO, OWNER_SERIAL_RX, RESOURCE_INDEX(device));
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IOConfigGPIOAF(rxIO, IOCFG_AF_PP_UP, hardware->af);
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}
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}
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if (!(s->rxDMAChannel)) {
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NVIC_InitStructure.NVIC_IRQChannel = uart->rxIrq;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(uart->rxPriority);
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(uart->rxPriority);
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NVIC_InitTypeDef NVIC_InitStructure;
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NVIC_InitStructure.NVIC_IRQChannel = hardware->irqn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(hardware->rxPriority);
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(hardware->rxPriority);
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
|
|
@ -342,56 +285,29 @@ uartPort_t *serialUART(UARTDevice device, uint32_t baudRate, portMode_t mode, po
|
|||
return s;
|
||||
}
|
||||
|
||||
#ifdef USE_UART1
|
||||
// USART1 Rx/Tx IRQ Handler
|
||||
void USART1_IRQHandler(void)
|
||||
void uartIrqHandler(uartPort_t *s)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_1]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
if (!s->rxDMAStream && (USART_GetITStatus(s->USARTx, USART_IT_RXNE) == SET)) {
|
||||
if (s->port.rxCallback) {
|
||||
s->port.rxCallback(s->USARTx->DR);
|
||||
} else {
|
||||
s->port.rxBuffer[s->port.rxBufferHead] = s->USARTx->DR;
|
||||
s->port.rxBufferHead = (s->port.rxBufferHead + 1) % s->port.rxBufferSize;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
if (!s->txDMAStream && (USART_GetITStatus(s->USARTx, USART_IT_TXE) == SET)) {
|
||||
if (s->port.txBufferTail != s->port.txBufferHead) {
|
||||
USART_SendData(s->USARTx, s->port.txBuffer[s->port.txBufferTail]);
|
||||
s->port.txBufferTail = (s->port.txBufferTail + 1) % s->port.txBufferSize;
|
||||
} else {
|
||||
USART_ITConfig(s->USARTx, USART_IT_TXE, DISABLE);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef USE_UART2
|
||||
void USART2_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_2]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_UART3
|
||||
// USART3
|
||||
void USART3_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_3]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_UART4
|
||||
// UART4
|
||||
void UART4_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_4]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_UART5
|
||||
// UART5
|
||||
void UART5_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_5]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_UART6
|
||||
// USART6
|
||||
void USART6_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_6]->port);
|
||||
uartIrqHandler(s);
|
||||
if (USART_GetITStatus(s->USARTx, USART_FLAG_ORE) == SET)
|
||||
{
|
||||
USART_ClearITPendingBit (s->USARTx, USART_IT_ORE);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue