mirror of
https://github.com/betaflight/betaflight.git
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Configurable UART
This commit is contained in:
jflyper
parent
4ee7a330d6
commit
fdfe9e8af3
15 changed files with 1617 additions and 1604 deletions
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@ -15,272 +15,227 @@
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* jflyper - Refactoring, cleanup and made pin-configurable
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include "platform.h"
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#include "drivers/system.h"
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#include "drivers/dma.h"
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#include "drivers/io.h"
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#include "rcc.h"
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#include "drivers/nvic.h"
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#include "dma.h"
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#include "drivers/rcc.h"
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#include "serial.h"
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#include "serial_uart.h"
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#include "serial_uart_impl.h"
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#include "drivers/serial.h"
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#include "drivers/serial_uart.h"
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#include "drivers/serial_uart_impl.h"
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#ifdef USE_UART
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static void handleUsartTxDma(uartPort_t *s);
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#define UART_RX_BUFFER_SIZE UART1_RX_BUFFER_SIZE
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#define UART_TX_BUFFER_SIZE UART1_TX_BUFFER_SIZE
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typedef struct uartDevice_s {
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USART_TypeDef* dev;
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uartPort_t port;
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uint32_t DMAChannel;
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DMA_Stream_TypeDef *txDMAStream;
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DMA_Stream_TypeDef *rxDMAStream;
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ioTag_t rx;
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ioTag_t tx;
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volatile uint8_t rxBuffer[UART_RX_BUFFER_SIZE];
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volatile uint8_t txBuffer[UART_TX_BUFFER_SIZE];
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uint32_t rcc_ahb1;
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rccPeriphTag_t rcc_apb2;
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rccPeriphTag_t rcc_apb1;
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uint8_t af;
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uint8_t txIrq;
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uint8_t rxIrq;
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uint32_t txPriority;
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uint32_t rxPriority;
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} uartDevice_t;
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//static uartPort_t uartPort[MAX_UARTS];
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const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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#ifdef USE_UART1
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static uartDevice_t uart1 =
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{
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.DMAChannel = DMA_CHANNEL_4,
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{
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.device = UARTDEV_1,
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.reg = USART1,
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.DMAChannel = DMA_CHANNEL_4,
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#ifdef USE_UART1_RX_DMA
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.rxDMAStream = DMA2_Stream5,
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.rxDMAStream = DMA2_Stream5,
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#endif
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.txDMAStream = DMA2_Stream7,
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.dev = USART1,
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.rx = IO_TAG(UART1_RX_PIN),
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.tx = IO_TAG(UART1_TX_PIN),
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.af = GPIO_AF7_USART1,
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.txDMAStream = DMA2_Stream7,
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.pinPair = {
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{ DEFIO_TAG_E(PA10), DEFIO_TAG_E(PA9) },
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{ DEFIO_TAG_E(PB7), DEFIO_TAG_E(PB6) },
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},
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.af = GPIO_AF7_USART1,
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#ifdef UART1_AHB1_PERIPHERALS
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.rcc_ahb1 = UART1_AHB1_PERIPHERALS,
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.rcc_ahb1 = UART1_AHB1_PERIPHERALS,
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#endif
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.rcc_apb2 = RCC_APB2(USART1),
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.txIrq = DMA2_ST7_HANDLER,
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.rxIrq = USART1_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART1_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART1
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};
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.rcc_apb2 = RCC_APB2(USART1),
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.txIrq = DMA2_ST7_HANDLER,
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.rxIrq = USART1_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART1_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART1
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},
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#endif
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#ifdef USE_UART2
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static uartDevice_t uart2 =
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{
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.DMAChannel = DMA_CHANNEL_4,
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{
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.device = UARTDEV_2,
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.reg = USART2,
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.DMAChannel = DMA_CHANNEL_4,
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#ifdef USE_UART2_RX_DMA
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.rxDMAStream = DMA1_Stream5,
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.rxDMAStream = DMA1_Stream5,
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#endif
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.txDMAStream = DMA1_Stream6,
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.dev = USART2,
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.rx = IO_TAG(UART2_RX_PIN),
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.tx = IO_TAG(UART2_TX_PIN),
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.af = GPIO_AF7_USART2,
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.txDMAStream = DMA1_Stream6,
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.pinPair = {
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{ DEFIO_TAG_E(PA3), DEFIO_TAG_E(PA2) },
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{ DEFIO_TAG_E(PD6), DEFIO_TAG_E(PD5) },
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},
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.af = GPIO_AF7_USART2,
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#ifdef UART2_AHB1_PERIPHERALS
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.rcc_ahb1 = UART2_AHB1_PERIPHERALS,
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.rcc_ahb1 = UART2_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(USART2),
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.txIrq = DMA1_ST6_HANDLER,
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.rxIrq = USART2_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART2_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART2
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};
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.rcc_apb1 = RCC_APB1(USART2),
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.txIrq = DMA1_ST6_HANDLER,
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.rxIrq = USART2_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART2_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART2
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},
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#endif
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#ifdef USE_UART3
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static uartDevice_t uart3 =
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{
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.DMAChannel = DMA_CHANNEL_4,
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{
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.device = UARTDEV_3,
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.reg = USART3,
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.DMAChannel = DMA_CHANNEL_4,
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#ifdef USE_UART3_RX_DMA
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.rxDMAStream = DMA1_Stream1,
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.rxDMAStream = DMA1_Stream1,
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#endif
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.txDMAStream = DMA1_Stream3,
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.dev = USART3,
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.rx = IO_TAG(UART3_RX_PIN),
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.tx = IO_TAG(UART3_TX_PIN),
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.af = GPIO_AF7_USART3,
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.txDMAStream = DMA1_Stream3,
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.pinPair = {
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{ DEFIO_TAG_E(PB11), DEFIO_TAG_E(PB10) },
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{ DEFIO_TAG_E(PC11), DEFIO_TAG_E(PC10) },
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{ DEFIO_TAG_E(PD9), DEFIO_TAG_E(PD8) },
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},
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.af = GPIO_AF7_USART3,
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#ifdef UART3_AHB1_PERIPHERALS
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.rcc_ahb1 = UART3_AHB1_PERIPHERALS,
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.rcc_ahb1 = UART3_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(USART3),
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.txIrq = DMA1_ST3_HANDLER,
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.rxIrq = USART3_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART3_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART3
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};
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.rcc_apb1 = RCC_APB1(USART3),
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.txIrq = DMA1_ST3_HANDLER,
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.rxIrq = USART3_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART3_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART3
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},
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#endif
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#ifdef USE_UART4
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static uartDevice_t uart4 =
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{
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.DMAChannel = DMA_CHANNEL_4,
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{
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.device = UARTDEV_4,
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.reg = UART4,
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.DMAChannel = DMA_CHANNEL_4,
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#ifdef USE_UART4_RX_DMA
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.rxDMAStream = DMA1_Stream2,
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.rxDMAStream = DMA1_Stream2,
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#endif
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.txDMAStream = DMA1_Stream4,
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.dev = UART4,
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.rx = IO_TAG(UART4_RX_PIN),
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.tx = IO_TAG(UART4_TX_PIN),
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.af = GPIO_AF8_UART4,
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.txDMAStream = DMA1_Stream4,
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.pinPair = {
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{ DEFIO_TAG_E(PA1), DEFIO_TAG_E(PA0) },
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{ DEFIO_TAG_E(PC11), DEFIO_TAG_E(PC10) },
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},
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.af = GPIO_AF8_UART4,
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#ifdef UART4_AHB1_PERIPHERALS
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.rcc_ahb1 = UART4_AHB1_PERIPHERALS,
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.rcc_ahb1 = UART4_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(UART4),
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.txIrq = DMA1_ST4_HANDLER,
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.rxIrq = UART4_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART4_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART4
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};
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.rcc_apb1 = RCC_APB1(UART4),
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.txIrq = DMA1_ST4_HANDLER,
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.rxIrq = UART4_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART4_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART4
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},
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#endif
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#ifdef USE_UART5
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static uartDevice_t uart5 =
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{
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.DMAChannel = DMA_CHANNEL_4,
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{
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.device = UARTDEV_5,
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.reg = UART5,
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.DMAChannel = DMA_CHANNEL_4,
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#ifdef USE_UART5_RX_DMA
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.rxDMAStream = DMA1_Stream0,
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.rxDMAStream = DMA1_Stream0,
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#endif
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.txDMAStream = DMA1_Stream7,
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.dev = UART5,
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.rx = IO_TAG(UART5_RX_PIN),
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.tx = IO_TAG(UART5_TX_PIN),
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.af = GPIO_AF8_UART5,
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.txDMAStream = DMA1_Stream7,
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.pinPair = {
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{ DEFIO_TAG_E(PD2), DEFIO_TAG_E(PC12) },
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},
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.af = GPIO_AF8_UART5,
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#ifdef UART5_AHB1_PERIPHERALS
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.rcc_ahb1 = UART5_AHB1_PERIPHERALS,
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.rcc_ahb1 = UART5_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(UART5),
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.txIrq = DMA1_ST7_HANDLER,
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.rxIrq = UART5_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART5_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART5
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};
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.rcc_apb1 = RCC_APB1(UART5),
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.txIrq = DMA1_ST7_HANDLER,
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.rxIrq = UART5_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART5_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART5
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},
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#endif
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#ifdef USE_UART6
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static uartDevice_t uart6 =
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{
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.DMAChannel = DMA_CHANNEL_5,
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{
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.device = UARTDEV_6,
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.reg = USART6,
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.DMAChannel = DMA_CHANNEL_5,
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#ifdef USE_UART6_RX_DMA
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.rxDMAStream = DMA2_Stream1,
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.rxDMAStream = DMA2_Stream1,
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#endif
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.txDMAStream = DMA2_Stream6,
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.dev = USART6,
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.rx = IO_TAG(UART6_RX_PIN),
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.tx = IO_TAG(UART6_TX_PIN),
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.af = GPIO_AF8_USART6,
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.txDMAStream = DMA2_Stream6,
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.pinPair = {
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{ DEFIO_TAG_E(PC7), DEFIO_TAG_E(PC6) },
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{ DEFIO_TAG_E(PG9), DEFIO_TAG_E(PG14) },
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},
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.af = GPIO_AF8_USART6,
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#ifdef UART6_AHB1_PERIPHERALS
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.rcc_ahb1 = UART6_AHB1_PERIPHERALS,
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.rcc_ahb1 = UART6_AHB1_PERIPHERALS,
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#endif
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.rcc_apb2 = RCC_APB2(USART6),
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.txIrq = DMA2_ST6_HANDLER,
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.rxIrq = USART6_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART6_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART6
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};
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.rcc_apb2 = RCC_APB2(USART6),
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.txIrq = DMA2_ST6_HANDLER,
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.rxIrq = USART6_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART6_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART6
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},
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#endif
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#ifdef USE_UART7
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static uartDevice_t uart7 =
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{
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.DMAChannel = DMA_CHANNEL_5,
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{
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.device = UARTDEV_7,
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.reg = UART7,
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.DMAChannel = DMA_CHANNEL_5,
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#ifdef USE_UART7_RX_DMA
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.rxDMAStream = DMA1_Stream3,
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.rxDMAStream = DMA1_Stream3,
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#endif
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.txDMAStream = DMA1_Stream1,
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.dev = UART7,
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.rx = IO_TAG(UART7_RX_PIN),
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.tx = IO_TAG(UART7_TX_PIN),
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.af = GPIO_AF8_UART7,
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.txDMAStream = DMA1_Stream1,
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.pinPair = {
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{ DEFIO_TAG_E(PE7), DEFIO_TAG_E(PE8) },
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{ DEFIO_TAG_E(PF6), DEFIO_TAG_E(PF7) },
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},
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.af = GPIO_AF8_UART7,
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#ifdef UART7_AHB1_PERIPHERALS
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.rcc_ahb1 = UART7_AHB1_PERIPHERALS,
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.rcc_ahb1 = UART7_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(UART7),
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.txIrq = DMA1_ST1_HANDLER,
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.rxIrq = UART7_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART7_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART7
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};
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.rcc_apb1 = RCC_APB1(UART7),
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.txIrq = DMA1_ST1_HANDLER,
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.rxIrq = UART7_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART7_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART7
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},
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#endif
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#ifdef USE_UART8
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static uartDevice_t uart8 =
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{
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.DMAChannel = DMA_CHANNEL_5,
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{
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.device = UARTDEV_8,
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.reg = UART8,
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.DMAChannel = DMA_CHANNEL_5,
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#ifdef USE_UART8_RX_DMA
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.rxDMAStream = DMA1_Stream6,
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.rxDMAStream = DMA1_Stream6,
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#endif
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.txDMAStream = DMA1_Stream0,
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.dev = UART8,
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.rx = IO_TAG(UART8_RX_PIN),
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.tx = IO_TAG(UART8_TX_PIN),
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.af = GPIO_AF8_UART8,
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.txDMAStream = DMA1_Stream0,
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.pinPair = {
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{ DEFIO_TAG_E(PE0), DEFIO_TAG_E(PE1) },
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},
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.af = GPIO_AF8_UART8,
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#ifdef UART8_AHB1_PERIPHERALS
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.rcc_ahb1 = UART8_AHB1_PERIPHERALS,
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.rcc_ahb1 = UART8_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(UART8),
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.txIrq = DMA1_ST0_HANDLER,
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.rxIrq = UART8_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART8_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART8
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};
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#endif
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static uartDevice_t* uartHardwareMap[] = {
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#ifdef USE_UART1
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&uart1,
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#else
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NULL,
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#endif
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#ifdef USE_UART2
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&uart2,
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#else
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NULL,
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#endif
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#ifdef USE_UART3
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&uart3,
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#else
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NULL,
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#endif
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#ifdef USE_UART4
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&uart4,
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#else
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NULL,
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#endif
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#ifdef USE_UART5
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&uart5,
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#else
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NULL,
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#endif
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#ifdef USE_UART6
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&uart6,
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#else
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NULL,
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#endif
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#ifdef USE_UART7
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&uart7,
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#else
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NULL,
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#endif
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#ifdef USE_UART8
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&uart8,
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#else
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NULL,
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.rcc_apb1 = RCC_APB1(UART8),
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.txIrq = DMA1_ST0_HANDLER,
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.rxIrq = UART8_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART8_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART8
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},
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#endif
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};
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@ -361,140 +316,76 @@ void dmaIRQHandler(dmaChannelDescriptor_t* descriptor)
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HAL_DMA_IRQHandler(&s->txDMAHandle);
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}
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// XXX Should serialUART be consolidated?
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uartPort_t *serialUART(UARTDevice device, uint32_t baudRate, portMode_t mode, portOptions_t options)
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{
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uartPort_t *s;
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uartDevice_t *uartdev = uartDevmap[device];
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if (!uartdev) {
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||||
return NULL;
|
||||
}
|
||||
|
||||
uartDevice_t *uart = uartHardwareMap[device];
|
||||
if (!uart) return NULL;
|
||||
uartPort_t *s = &(uartdev->port);
|
||||
|
||||
s = &(uart->port);
|
||||
s->port.vTable = uartVTable;
|
||||
|
||||
s->port.baudRate = baudRate;
|
||||
|
||||
s->port.rxBuffer = uart->rxBuffer;
|
||||
s->port.txBuffer = uart->txBuffer;
|
||||
s->port.rxBufferSize = sizeof(uart->rxBuffer);
|
||||
s->port.txBufferSize = sizeof(uart->txBuffer);
|
||||
s->port.rxBuffer = uartdev->rxBuffer;
|
||||
s->port.txBuffer = uartdev->txBuffer;
|
||||
s->port.rxBufferSize = ARRAYLEN(uartdev->rxBuffer);
|
||||
s->port.txBufferSize = ARRAYLEN(uartdev->txBuffer);
|
||||
|
||||
s->USARTx = uart->dev;
|
||||
if (uart->rxDMAStream) {
|
||||
s->rxDMAChannel = uart->DMAChannel;
|
||||
s->rxDMAStream = uart->rxDMAStream;
|
||||
const uartHardware_t *hardware = uartdev->hardware;
|
||||
|
||||
s->USARTx = hardware->reg;
|
||||
|
||||
if (hardware->rxDMAStream) {
|
||||
s->rxDMAChannel = hardware->DMAChannel;
|
||||
s->rxDMAStream = hardware->rxDMAStream;
|
||||
}
|
||||
s->txDMAChannel = uart->DMAChannel;
|
||||
s->txDMAStream = uart->txDMAStream;
|
||||
s->txDMAChannel = hardware->DMAChannel;
|
||||
s->txDMAStream = hardware->txDMAStream;
|
||||
|
||||
s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->TDR;
|
||||
s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->RDR;
|
||||
|
||||
s->Handle.Instance = uart->dev;
|
||||
s->Handle.Instance = hardware->reg;
|
||||
|
||||
IO_t tx = IOGetByTag(uart->tx);
|
||||
IO_t rx = IOGetByTag(uart->rx);
|
||||
IO_t txIO = IOGetByTag(uartdev->tx);
|
||||
IO_t rxIO = IOGetByTag(uartdev->rx);
|
||||
|
||||
if ((options & SERIAL_BIDIR) && tx) {
|
||||
IOInit(tx, OWNER_SERIAL_TX, RESOURCE_INDEX(device));
|
||||
IOConfigGPIOAF(tx, IOCFG_AF_PP, uart->af);
|
||||
if ((options & SERIAL_BIDIR) && txIO) {
|
||||
// XXX BIDIR_PP handling is missing
|
||||
IOInit(txIO, OWNER_SERIAL_TX, RESOURCE_INDEX(device));
|
||||
IOConfigGPIOAF(txIO, IOCFG_AF_PP, hardware->af);
|
||||
}
|
||||
else {
|
||||
if ((mode & MODE_TX) && tx) {
|
||||
IOInit(tx, OWNER_SERIAL_TX, RESOURCE_INDEX(device));
|
||||
IOConfigGPIOAF(tx, IOCFG_AF_PP, uart->af);
|
||||
if ((mode & MODE_TX) && txIO) {
|
||||
IOInit(txIO, OWNER_SERIAL_TX, RESOURCE_INDEX(device));
|
||||
IOConfigGPIOAF(txIO, IOCFG_AF_PP, hardware->af);
|
||||
}
|
||||
|
||||
if ((mode & MODE_RX) && rx) {
|
||||
IOInit(rx, OWNER_SERIAL_RX, RESOURCE_INDEX(device));
|
||||
IOConfigGPIOAF(rx, IOCFG_AF_PP, uart->af);
|
||||
if ((mode & MODE_RX) && rxIO) {
|
||||
IOInit(rxIO, OWNER_SERIAL_RX, RESOURCE_INDEX(device));
|
||||
IOConfigGPIOAF(rxIO, IOCFG_AF_PP, hardware->af);
|
||||
}
|
||||
}
|
||||
|
||||
// DMA TX Interrupt
|
||||
dmaInit(uart->txIrq, OWNER_SERIAL_TX, RESOURCE_INDEX(device));
|
||||
dmaSetHandler(uart->txIrq, dmaIRQHandler, uart->txPriority, (uint32_t)uart);
|
||||
dmaInit(hardware->txIrq, OWNER_SERIAL_TX, RESOURCE_INDEX(device));
|
||||
dmaSetHandler(hardware->txIrq, dmaIRQHandler, hardware->txPriority, (uint32_t)uartdev);
|
||||
|
||||
|
||||
//HAL_NVIC_SetPriority(uart->txIrq, NVIC_PRIORITY_BASE(uart->txPriority), NVIC_PRIORITY_SUB(uart->txPriority));
|
||||
//HAL_NVIC_EnableIRQ(uart->txIrq);
|
||||
//HAL_NVIC_SetPriority(hardware->txIrq, NVIC_PRIORITY_BASE(hardware->txPriority), NVIC_PRIORITY_SUB(hardware->txPriority));
|
||||
//HAL_NVIC_EnableIRQ(hardware->txIrq);
|
||||
|
||||
if(!s->rxDMAChannel)
|
||||
{
|
||||
HAL_NVIC_SetPriority(uart->rxIrq, NVIC_PRIORITY_BASE(uart->rxPriority), NVIC_PRIORITY_SUB(uart->rxPriority));
|
||||
HAL_NVIC_EnableIRQ(uart->rxIrq);
|
||||
HAL_NVIC_SetPriority(hardware->rxIrq, NVIC_PRIORITY_BASE(hardware->rxPriority), NVIC_PRIORITY_SUB(hardware->rxPriority));
|
||||
HAL_NVIC_EnableIRQ(hardware->rxIrq);
|
||||
}
|
||||
|
||||
return s;
|
||||
}
|
||||
|
||||
#ifdef USE_UART1
|
||||
// USART1 Rx/Tx IRQ Handler
|
||||
void USART1_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_1]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_UART2
|
||||
// USART2 Rx/Tx IRQ Handler
|
||||
void USART2_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_2]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_UART3
|
||||
// USART3 Rx/Tx IRQ Handler
|
||||
void USART3_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_3]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_UART4
|
||||
// UART4 Rx/Tx IRQ Handler
|
||||
void UART4_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_4]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_UART5
|
||||
// UART5 Rx/Tx IRQ Handler
|
||||
void UART5_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_5]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_UART6
|
||||
// USART6 Rx/Tx IRQ Handler
|
||||
void USART6_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_6]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_UART7
|
||||
// UART7 Rx/Tx IRQ Handler
|
||||
void UART7_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_7]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_UART8
|
||||
// UART8 Rx/Tx IRQ Handler
|
||||
void UART8_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_8]->port);
|
||||
uartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
#endif // USE_UART
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue