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[H7] BB-Dshot support (TIM1/TIM8 limited version)

This commit is contained in:
jflyper 2019-09-01 02:01:29 +09:00
parent 575460ac52
commit fe1a05fa2a
7 changed files with 30 additions and 9 deletions

View file

@ -239,6 +239,9 @@ MCU_COMMON_SRC = \
drivers/bus_quadspi_hal.c \ drivers/bus_quadspi_hal.c \
drivers/bus_spi_hal.c \ drivers/bus_spi_hal.c \
drivers/dma_stm32h7xx.c \ drivers/dma_stm32h7xx.c \
drivers/dshot_bitbang.c \
drivers/dshot_bitbang_decode.c \
drivers/dshot_bitbang_ll.c \
drivers/light_ws2811strip_hal.c \ drivers/light_ws2811strip_hal.c \
drivers/adc_stm32h7xx.c \ drivers/adc_stm32h7xx.c \
drivers/bus_i2c_hal.c \ drivers/bus_i2c_hal.c \

View file

@ -34,7 +34,8 @@ typedef struct dmaResource_s dmaResource_t;
#if defined(STM32F4) || defined(STM32F7) #if defined(STM32F4) || defined(STM32F7)
#define DMA_ARCH_TYPE DMA_Stream_TypeDef #define DMA_ARCH_TYPE DMA_Stream_TypeDef
#elif defined(STM32H7) #elif defined(STM32H7)
#define DMA_ARCH_TYPE void // H7 has stream based DMA and channel based BDMA, but we ignore BDMA (for now).
#define DMA_ARCH_TYPE DMA_Stream_TypeDef
#else #else
#define DMA_ARCH_TYPE DMA_Channel_TypeDef #define DMA_ARCH_TYPE DMA_Channel_TypeDef
#endif #endif

View file

@ -104,8 +104,9 @@ const timerHardware_t bbTimerHardware[] = {
DEF_TIM(TIM1, CH2, NONE, TIM_USE_NONE, 0, 1), DEF_TIM(TIM1, CH2, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM1, CH3, NONE, TIM_USE_NONE, 0, 1), DEF_TIM(TIM1, CH3, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM1, CH4, NONE, TIM_USE_NONE, 0, 0), DEF_TIM(TIM1, CH4, NONE, TIM_USE_NONE, 0, 0),
#elif defined(STM32G4)
// XXX TODO: STM32G4 can use any timer for pacing #elif defined(STM32G4) || defined(STM32H7)
// XXX TODO: STM32G4 and STM32H7 can use any timer for pacing
// DMA request numbers are duplicated for TIM1 and TIM8: // DMA request numbers are duplicated for TIM1 and TIM8:
// - Any pacer can serve a GPIO port. // - Any pacer can serve a GPIO port.
@ -121,6 +122,7 @@ const timerHardware_t bbTimerHardware[] = {
DEF_TIM(TIM1, CH2, NONE, TIM_USE_NONE, 0, 1, 0), DEF_TIM(TIM1, CH2, NONE, TIM_USE_NONE, 0, 1, 0),
DEF_TIM(TIM1, CH3, NONE, TIM_USE_NONE, 0, 2, 0), DEF_TIM(TIM1, CH3, NONE, TIM_USE_NONE, 0, 2, 0),
DEF_TIM(TIM1, CH4, NONE, TIM_USE_NONE, 0, 3, 0), DEF_TIM(TIM1, CH4, NONE, TIM_USE_NONE, 0, 3, 0),
#else #else
#error MCU dependent code required #error MCU dependent code required
#endif #endif
@ -703,7 +705,7 @@ motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t
bbMotors[motorIndex].output = output; bbMotors[motorIndex].output = output;
#if defined(STM32F4) || defined(STM32F3) #if defined(STM32F4) || defined(STM32F3)
bbMotors[motorIndex].iocfg = IO_CONFIG(GPIO_Mode_OUT, GPIO_Speed_50MHz, GPIO_OType_PP, bbPuPdMode); bbMotors[motorIndex].iocfg = IO_CONFIG(GPIO_Mode_OUT, GPIO_Speed_50MHz, GPIO_OType_PP, bbPuPdMode);
#elif defined(STM32F7) || defined(STM32G4) #elif defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
bbMotors[motorIndex].iocfg = IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_VERY_HIGH, bbPuPdMode); bbMotors[motorIndex].iocfg = IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_VERY_HIGH, bbPuPdMode);
#endif #endif

View file

@ -74,7 +74,7 @@
#ifdef USE_DMA_REGISTER_CACHE #ifdef USE_DMA_REGISTER_CACHE
typedef struct dmaRegCache_s { typedef struct dmaRegCache_s {
#if defined(STM32F4) || defined(STM32F7) #if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
uint32_t CR; uint32_t CR;
uint32_t FCR; uint32_t FCR;
uint32_t NDTR; uint32_t NDTR;

View file

@ -51,7 +51,11 @@ void bbGpioSetup(bbMotor_t *bbMotor)
bbPort_t *bbPort = bbMotor->bbPort; bbPort_t *bbPort = bbMotor->bbPort;
int pinIndex = bbMotor->pinIndex; int pinIndex = bbMotor->pinIndex;
#ifdef STM32H7
bbPort->gpioModeMask |= (GPIO_MODER_MODE0 << (pinIndex * 2)); // A minor name change in H7 CMSIS
#else
bbPort->gpioModeMask |= (GPIO_MODER_MODER0 << (pinIndex * 2)); bbPort->gpioModeMask |= (GPIO_MODER_MODER0 << (pinIndex * 2));
#endif
bbPort->gpioModeInput |= (LL_GPIO_MODE_INPUT << (pinIndex * 2)); bbPort->gpioModeInput |= (LL_GPIO_MODE_INPUT << (pinIndex * 2));
bbPort->gpioModeOutput |= (LL_GPIO_MODE_OUTPUT << (pinIndex * 2)); bbPort->gpioModeOutput |= (LL_GPIO_MODE_OUTPUT << (pinIndex * 2));
@ -73,7 +77,7 @@ void bbGpioSetup(bbMotor_t *bbMotor)
IOWrite(bbMotor->io, 0); IOWrite(bbMotor->io, 0);
} }
#if defined(STM32F7) || defined(STM32G4) #if defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
IOConfigGPIO(bbMotor->io, IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_HIGH, bbPuPdMode)); IOConfigGPIO(bbMotor->io, IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_HIGH, bbPuPdMode));
#else #else
#error MCU dependent code required #error MCU dependent code required
@ -127,7 +131,7 @@ void bbTimerChannelInit(bbPort_t *bbPort)
#ifdef USE_DMA_REGISTER_CACHE #ifdef USE_DMA_REGISTER_CACHE
void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache) void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache)
{ {
#if defined(STM32F7) #if defined(STM32F7) || defined(STM32H7)
((DMA_ARCH_TYPE *)dmaResource)->CR = dmaRegCache->CR; ((DMA_ARCH_TYPE *)dmaResource)->CR = dmaRegCache->CR;
((DMA_ARCH_TYPE *)dmaResource)->FCR = dmaRegCache->FCR; ((DMA_ARCH_TYPE *)dmaResource)->FCR = dmaRegCache->FCR;
((DMA_ARCH_TYPE *)dmaResource)->NDTR = dmaRegCache->NDTR; ((DMA_ARCH_TYPE *)dmaResource)->NDTR = dmaRegCache->NDTR;
@ -145,7 +149,7 @@ void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache)
static void bbSaveDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache) static void bbSaveDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache)
{ {
#if defined(STM32F7) #if defined(STM32F7) || defined(STM32H7)
dmaRegCache->CR = ((DMA_ARCH_TYPE *)dmaResource)->CR; dmaRegCache->CR = ((DMA_ARCH_TYPE *)dmaResource)->CR;
dmaRegCache->FCR = ((DMA_ARCH_TYPE *)dmaResource)->FCR; dmaRegCache->FCR = ((DMA_ARCH_TYPE *)dmaResource)->FCR;
dmaRegCache->NDTR = ((DMA_ARCH_TYPE *)dmaResource)->NDTR; dmaRegCache->NDTR = ((DMA_ARCH_TYPE *)dmaResource)->NDTR;
@ -242,7 +246,7 @@ void bbDMAPreconfigure(bbPort_t *bbPort, uint8_t direction)
LL_DMA_StructInit(dmainit); LL_DMA_StructInit(dmainit);
dmainit->Mode = LL_DMA_MODE_NORMAL; dmainit->Mode = LL_DMA_MODE_NORMAL;
#if defined(STM32G4) #if defined(STM32G4) || defined(STM32H7)
dmainit->PeriphRequest = bbPort->dmaChannel; dmainit->PeriphRequest = bbPort->dmaChannel;
#else #else
dmainit->Channel = bbPort->dmaChannel; dmainit->Channel = bbPort->dmaChannel;

View file

@ -910,6 +910,16 @@
// AF table // AF table
// NONE
#define DEF_TIM_AF__NONE__TCH_TIM1_CH1 D(1, 1)
#define DEF_TIM_AF__NONE__TCH_TIM1_CH2 D(1, 1)
#define DEF_TIM_AF__NONE__TCH_TIM1_CH3 D(1, 1)
#define DEF_TIM_AF__NONE__TCH_TIM1_CH4 D(1, 1)
#define DEF_TIM_AF__NONE__TCH_TIM8_CH1 D(3, 8)
#define DEF_TIM_AF__NONE__TCH_TIM8_CH2 D(3, 8)
#define DEF_TIM_AF__NONE__TCH_TIM8_CH3 D(3, 8)
#define DEF_TIM_AF__NONE__TCH_TIM8_CH4 D(3, 8)
//PORTA //PORTA
#define DEF_TIM_AF__PA0__TCH_TIM2_CH1 D(1, 2) #define DEF_TIM_AF__PA0__TCH_TIM2_CH1 D(1, 2)
#define DEF_TIM_AF__PA1__TCH_TIM2_CH2 D(1, 2) #define DEF_TIM_AF__PA1__TCH_TIM2_CH2 D(1, 2)

View file

@ -110,6 +110,7 @@
#define USE_ITCM_RAM #define USE_ITCM_RAM
#define USE_FAST_DATA #define USE_FAST_DATA
#define USE_DSHOT #define USE_DSHOT
#define USE_DSHOT_BITBANG
#define USE_DSHOT_TELEMETRY #define USE_DSHOT_TELEMETRY
#define USE_DSHOT_TELEMETRY_STATS #define USE_DSHOT_TELEMETRY_STATS
#define USE_RPM_FILTER #define USE_RPM_FILTER