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[H7] BB-Dshot support (TIM1/TIM8 limited version)
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parent
575460ac52
commit
fe1a05fa2a
7 changed files with 30 additions and 9 deletions
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@ -239,6 +239,9 @@ MCU_COMMON_SRC = \
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drivers/bus_quadspi_hal.c \
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drivers/bus_spi_hal.c \
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drivers/dma_stm32h7xx.c \
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drivers/dshot_bitbang.c \
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drivers/dshot_bitbang_decode.c \
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drivers/dshot_bitbang_ll.c \
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drivers/light_ws2811strip_hal.c \
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drivers/adc_stm32h7xx.c \
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drivers/bus_i2c_hal.c \
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@ -34,7 +34,8 @@ typedef struct dmaResource_s dmaResource_t;
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#if defined(STM32F4) || defined(STM32F7)
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#define DMA_ARCH_TYPE DMA_Stream_TypeDef
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#elif defined(STM32H7)
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#define DMA_ARCH_TYPE void
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// H7 has stream based DMA and channel based BDMA, but we ignore BDMA (for now).
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#define DMA_ARCH_TYPE DMA_Stream_TypeDef
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#else
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#define DMA_ARCH_TYPE DMA_Channel_TypeDef
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#endif
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@ -104,8 +104,9 @@ const timerHardware_t bbTimerHardware[] = {
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DEF_TIM(TIM1, CH2, NONE, TIM_USE_NONE, 0, 1),
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DEF_TIM(TIM1, CH3, NONE, TIM_USE_NONE, 0, 1),
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DEF_TIM(TIM1, CH4, NONE, TIM_USE_NONE, 0, 0),
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#elif defined(STM32G4)
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// XXX TODO: STM32G4 can use any timer for pacing
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#elif defined(STM32G4) || defined(STM32H7)
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// XXX TODO: STM32G4 and STM32H7 can use any timer for pacing
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// DMA request numbers are duplicated for TIM1 and TIM8:
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// - Any pacer can serve a GPIO port.
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@ -121,6 +122,7 @@ const timerHardware_t bbTimerHardware[] = {
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DEF_TIM(TIM1, CH2, NONE, TIM_USE_NONE, 0, 1, 0),
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DEF_TIM(TIM1, CH3, NONE, TIM_USE_NONE, 0, 2, 0),
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DEF_TIM(TIM1, CH4, NONE, TIM_USE_NONE, 0, 3, 0),
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#else
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#error MCU dependent code required
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#endif
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@ -703,7 +705,7 @@ motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t
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bbMotors[motorIndex].output = output;
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#if defined(STM32F4) || defined(STM32F3)
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bbMotors[motorIndex].iocfg = IO_CONFIG(GPIO_Mode_OUT, GPIO_Speed_50MHz, GPIO_OType_PP, bbPuPdMode);
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#elif defined(STM32F7) || defined(STM32G4)
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#elif defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
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bbMotors[motorIndex].iocfg = IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_VERY_HIGH, bbPuPdMode);
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#endif
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@ -74,7 +74,7 @@
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#ifdef USE_DMA_REGISTER_CACHE
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typedef struct dmaRegCache_s {
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#if defined(STM32F4) || defined(STM32F7)
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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uint32_t CR;
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uint32_t FCR;
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uint32_t NDTR;
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@ -51,7 +51,11 @@ void bbGpioSetup(bbMotor_t *bbMotor)
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bbPort_t *bbPort = bbMotor->bbPort;
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int pinIndex = bbMotor->pinIndex;
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#ifdef STM32H7
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bbPort->gpioModeMask |= (GPIO_MODER_MODE0 << (pinIndex * 2)); // A minor name change in H7 CMSIS
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#else
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bbPort->gpioModeMask |= (GPIO_MODER_MODER0 << (pinIndex * 2));
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#endif
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bbPort->gpioModeInput |= (LL_GPIO_MODE_INPUT << (pinIndex * 2));
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bbPort->gpioModeOutput |= (LL_GPIO_MODE_OUTPUT << (pinIndex * 2));
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@ -73,7 +77,7 @@ void bbGpioSetup(bbMotor_t *bbMotor)
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IOWrite(bbMotor->io, 0);
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}
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#if defined(STM32F7) || defined(STM32G4)
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#if defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
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IOConfigGPIO(bbMotor->io, IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_HIGH, bbPuPdMode));
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#else
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#error MCU dependent code required
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@ -127,7 +131,7 @@ void bbTimerChannelInit(bbPort_t *bbPort)
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#ifdef USE_DMA_REGISTER_CACHE
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void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache)
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{
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#if defined(STM32F7)
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#if defined(STM32F7) || defined(STM32H7)
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((DMA_ARCH_TYPE *)dmaResource)->CR = dmaRegCache->CR;
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((DMA_ARCH_TYPE *)dmaResource)->FCR = dmaRegCache->FCR;
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((DMA_ARCH_TYPE *)dmaResource)->NDTR = dmaRegCache->NDTR;
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@ -145,7 +149,7 @@ void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache)
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static void bbSaveDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache)
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{
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#if defined(STM32F7)
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#if defined(STM32F7) || defined(STM32H7)
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dmaRegCache->CR = ((DMA_ARCH_TYPE *)dmaResource)->CR;
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dmaRegCache->FCR = ((DMA_ARCH_TYPE *)dmaResource)->FCR;
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dmaRegCache->NDTR = ((DMA_ARCH_TYPE *)dmaResource)->NDTR;
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@ -242,7 +246,7 @@ void bbDMAPreconfigure(bbPort_t *bbPort, uint8_t direction)
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LL_DMA_StructInit(dmainit);
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dmainit->Mode = LL_DMA_MODE_NORMAL;
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#if defined(STM32G4)
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#if defined(STM32G4) || defined(STM32H7)
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dmainit->PeriphRequest = bbPort->dmaChannel;
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#else
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dmainit->Channel = bbPort->dmaChannel;
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@ -910,6 +910,16 @@
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// AF table
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// NONE
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#define DEF_TIM_AF__NONE__TCH_TIM1_CH1 D(1, 1)
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#define DEF_TIM_AF__NONE__TCH_TIM1_CH2 D(1, 1)
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#define DEF_TIM_AF__NONE__TCH_TIM1_CH3 D(1, 1)
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#define DEF_TIM_AF__NONE__TCH_TIM1_CH4 D(1, 1)
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#define DEF_TIM_AF__NONE__TCH_TIM8_CH1 D(3, 8)
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#define DEF_TIM_AF__NONE__TCH_TIM8_CH2 D(3, 8)
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#define DEF_TIM_AF__NONE__TCH_TIM8_CH3 D(3, 8)
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#define DEF_TIM_AF__NONE__TCH_TIM8_CH4 D(3, 8)
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//PORTA
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#define DEF_TIM_AF__PA0__TCH_TIM2_CH1 D(1, 2)
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#define DEF_TIM_AF__PA1__TCH_TIM2_CH2 D(1, 2)
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@ -110,6 +110,7 @@
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#define USE_ITCM_RAM
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#define USE_FAST_DATA
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#define USE_DSHOT
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#define USE_DSHOT_BITBANG
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#define USE_DSHOT_TELEMETRY
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#define USE_DSHOT_TELEMETRY_STATS
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#define USE_RPM_FILTER
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