The primary reason is to support the D4R-II with it's much faster PWM
frequency. The PWM RSSI code could not keep up, and since there are no
timers free for using capture compare of PWM signals in hardware one
solution is to use the ADC at a slow sample rate.
RC2 is used as before and it expects a signal between 0 and 3.3v. An
inline smoothing capacitor may help.
This commit also removes the cli command adc_power_channel since the
reading was never actually exposed anywhere.
implementing the STM32F303 ADC code. Now this is inline with the
STM32F303 initialisation.
This also deletes some redundant code due to better initialisation
sequence.
