mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-15 12:25:20 +03:00
053a28dc62
tested. PPM and motor outputs conflict since they use the same timers so this just avoids conflicts.
476 lines
19 KiB
C
476 lines
19 KiB
C
/*
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* This file is part of Cleanflight.
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*
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* Cleanflight is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Cleanflight is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include "platform.h"
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#include "gpio.h"
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#include "system.h"
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#include "timer.h"
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/* FreeFlight/Naze32 timer layout
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TIM2_CH1 RC1 PWM1
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TIM2_CH2 RC2 PWM2
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TIM2_CH3 RC3/UA2_TX PWM3
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TIM2_CH4 RC4/UA2_RX PWM4
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TIM3_CH1 RC5 PWM5
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TIM3_CH2 RC6 PWM6
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TIM3_CH3 RC7 PWM7
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TIM3_CH4 RC8 PWM8
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TIM1_CH1 PWM1 PWM9
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TIM1_CH4 PWM2 PWM10
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TIM4_CH1 PWM3 PWM11
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TIM4_CH2 PWM4 PWM12
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TIM4_CH3 PWM5 PWM13
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TIM4_CH4 PWM6 PWM14
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RX1 TIM2_CH1 PA0 [also PPM] [also used for throttle calibration]
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RX2 TIM2_CH2 PA1
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RX3 TIM2_CH3 PA2 [also UART2_TX]
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RX4 TIM2_CH4 PA3 [also UART2_RX]
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RX5 TIM3_CH1 PA6 [also ADC_IN6]
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RX6 TIM3_CH2 PA7 [also ADC_IN7]
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RX7 TIM3_CH3 PB0 [also ADC_IN8]
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RX8 TIM3_CH4 PB1 [also ADC_IN9]
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Outputs
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PWM1 TIM1_CH1 PA8
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PWM2 TIM1_CH4 PA11
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PWM3 TIM4_CH1 PB6 [also I2C1_SCL]
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PWM4 TIM4_CH2 PB7 [also I2C1_SDA]
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PWM5 TIM4_CH3 PB8
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PWM6 TIM4_CH4 PB9
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Groups that allow running different period (ex 50Hz servos + 400Hz throttle + etc):
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TIM2 4 channels
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TIM3 4 channels
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TIM1 2 channels
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TIM4 4 channels
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*/
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#if (defined(STM32F10X_MD) || defined(NAZE)) && !defined(CC3D)
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const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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{ TIM2, GPIOA, Pin_0, TIM_Channel_1, TIM2_IRQn, 0, Mode_IPD}, // PWM1
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{ TIM2, GPIOA, Pin_1, TIM_Channel_2, TIM2_IRQn, 0, Mode_IPD}, // PWM2
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{ TIM2, GPIOA, Pin_2, TIM_Channel_3, TIM2_IRQn, 0, Mode_IPD}, // PWM3
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{ TIM2, GPIOA, Pin_3, TIM_Channel_4, TIM2_IRQn, 0, Mode_IPD}, // PWM4
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{ TIM3, GPIOA, Pin_6, TIM_Channel_1, TIM3_IRQn, 0, Mode_IPD}, // PWM5
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{ TIM3, GPIOA, Pin_7, TIM_Channel_2, TIM3_IRQn, 0, Mode_IPD}, // PWM6
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{ TIM3, GPIOB, Pin_0, TIM_Channel_3, TIM3_IRQn, 0, Mode_IPD}, // PWM7
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{ TIM3, GPIOB, Pin_1, TIM_Channel_4, TIM3_IRQn, 0, Mode_IPD}, // PWM8
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{ TIM1, GPIOA, Pin_8, TIM_Channel_1, TIM1_CC_IRQn, 1, Mode_IPD}, // PWM9
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{ TIM1, GPIOA, Pin_11, TIM_Channel_4, TIM1_CC_IRQn, 1, Mode_IPD}, // PWM10
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{ TIM4, GPIOB, Pin_6, TIM_Channel_1, TIM4_IRQn, 0, Mode_IPD}, // PWM11
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{ TIM4, GPIOB, Pin_7, TIM_Channel_2, TIM4_IRQn, 0, Mode_IPD}, // PWM12
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{ TIM4, GPIOB, Pin_8, TIM_Channel_3, TIM4_IRQn, 0, Mode_IPD}, // PWM13
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{ TIM4, GPIOB, Pin_9, TIM_Channel_4, TIM4_IRQn, 0, Mode_IPD} // PWM14
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};
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#define MAX_TIMERS 4 // TIM1..TIM4
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static const TIM_TypeDef *timers[MAX_TIMERS] = {
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TIM1, TIM2, TIM3, TIM4
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};
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#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4)
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#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB)
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#endif
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#if defined(CC3D)
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const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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{ TIM4, GPIOB, Pin_6, TIM_Channel_1, TIM4_IRQn, 0, Mode_IPD}, // S1_IN
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{ TIM3, GPIOB, Pin_5, TIM_Channel_2, TIM3_IRQn, 0, Mode_IPD}, // S2_IN - GPIO_PartialRemap_TIM3
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{ TIM3, GPIOB, Pin_0, TIM_Channel_3, TIM3_IRQn, 0, Mode_IPD}, // S3_IN
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{ TIM3, GPIOB, Pin_1, TIM_Channel_4, TIM3_IRQn, 0, Mode_IPD}, // S4_IN
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{ TIM2, GPIOA, Pin_0, TIM_Channel_1, TIM2_IRQn, 0, Mode_IPD}, // S5_IN
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{ TIM2, GPIOA, Pin_1, TIM_Channel_2, TIM2_IRQn, 0, Mode_IPD}, // S6_IN
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{ TIM4, GPIOB, Pin_9, TIM_Channel_4, TIM4_IRQn, 1, GPIO_Mode_AF_PP}, // S1_OUT
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{ TIM4, GPIOB, Pin_8, TIM_Channel_3, TIM4_IRQn, 1, GPIO_Mode_AF_PP}, // S2_OUT
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{ TIM4, GPIOB, Pin_7, TIM_Channel_2, TIM4_IRQn, 1, GPIO_Mode_AF_PP}, // S3_OUT
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{ TIM1, GPIOA, Pin_8, TIM_Channel_1, TIM1_CC_IRQn, 1, GPIO_Mode_AF_PP}, // S4_OUT
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{ TIM3, GPIOB, Pin_4, TIM_Channel_1, TIM3_IRQn, 1, GPIO_Mode_AF_PP}, // S5_OUT - GPIO_PartialRemap_TIM3
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{ TIM2, GPIOA, Pin_2, TIM_Channel_3, TIM2_IRQn, 1, GPIO_Mode_AF_PP}, // S6_OUT
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};
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#define MAX_TIMERS 4 // TIM1..TIM4
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static const TIM_TypeDef *timers[MAX_TIMERS] = {
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TIM1, TIM2, TIM3, TIM4
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};
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#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4)
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#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB)
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#endif
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#if (defined(STM32F303xC) || defined(STM32F3DISCOVERY)) && !(defined(CHEBUZZF3) || defined(NAZE32PRO))
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const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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{ TIM1, GPIOA, Pin_8, TIM_Channel_1, TIM1_CC_IRQn, 1, Mode_AF_PP_PD}, // PWM1 - PA8
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{ TIM16, GPIOB, Pin_8, TIM_Channel_1, TIM1_UP_TIM16_IRQn, 0, Mode_AF_PP_PD}, // PWM2 - PB8
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{ TIM17, GPIOB, Pin_9, TIM_Channel_1, TIM1_TRG_COM_TIM17_IRQn, 0, Mode_AF_PP_PD}, // PWM3 - PB9
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{ TIM8, GPIOC, Pin_6, TIM_Channel_1, TIM8_CC_IRQn, 1, Mode_AF_PP_PD}, // PWM4 - PC6
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{ TIM8, GPIOC, Pin_7, TIM_Channel_2, TIM8_CC_IRQn, 1, Mode_AF_PP_PD}, // PWM5 - PC7
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{ TIM8, GPIOC, Pin_8, TIM_Channel_3, TIM8_CC_IRQn, 1, Mode_AF_PP_PD}, // PWM6 - PC8
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{ TIM3, GPIOB, Pin_1, TIM_Channel_4, TIM3_IRQn, 0, Mode_AF_PP_PD}, // PWM7 - PB1
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{ TIM3, GPIOA, Pin_4, TIM_Channel_2, TIM3_IRQn, 0, Mode_AF_PP_PD}, // PWM8 - PA2
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{ TIM4, GPIOD, Pin_12, TIM_Channel_1, TIM4_IRQn, 0, Mode_AF_PP}, // PWM9 - PD12
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{ TIM4, GPIOD, Pin_13, TIM_Channel_2, TIM4_IRQn, 0, Mode_AF_PP}, // PWM10 - PD13
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{ TIM4, GPIOD, Pin_14, TIM_Channel_3, TIM4_IRQn, 0, Mode_AF_PP}, // PWM11 - PD14
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{ TIM4, GPIOD, Pin_15, TIM_Channel_4, TIM4_IRQn, 0, Mode_AF_PP}, // PWM12 - PD15
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{ TIM2, GPIOA, Pin_1, TIM_Channel_2, TIM2_IRQn, 0, Mode_AF_PP}, // PWM13 - PA1
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{ TIM2, GPIOA, Pin_2, TIM_Channel_3, TIM2_IRQn, 0, Mode_AF_PP} // PWM14 - PA2
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};
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#define MAX_TIMERS 7
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static const TIM_TypeDef *timers[MAX_TIMERS] = {
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TIM1, TIM2, TIM3, TIM4, TIM8, TIM16, TIM17
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};
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#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4)
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#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM8 | RCC_APB2Periph_TIM16 | RCC_APB2Periph_TIM17)
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#define TIMER_AHB_PERIPHERALS (RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC | RCC_AHBPeriph_GPIOD)
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#endif
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#if defined(CHEBUZZF3)
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const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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// INPUTS CH1-8
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{ TIM1, GPIOA, Pin_8, TIM_Channel_1, TIM1_CC_IRQn, 1, Mode_AF_PP_PD}, // PWM1 - PA8
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{ TIM16, GPIOB, Pin_8, TIM_Channel_1, TIM1_UP_TIM16_IRQn, 0, Mode_AF_PP_PD}, // PWM2 - PB8
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{ TIM17, GPIOB, Pin_9, TIM_Channel_1, TIM1_TRG_COM_TIM17_IRQn, 0, Mode_AF_PP_PD}, // PWM3 - PB9
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{ TIM8, GPIOC, Pin_6, TIM_Channel_1, TIM8_CC_IRQn, 1, Mode_AF_PP_PD}, // PWM4 - PC6
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{ TIM8, GPIOC, Pin_7, TIM_Channel_2, TIM8_CC_IRQn, 1, Mode_AF_PP_PD}, // PWM5 - PC7
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{ TIM8, GPIOC, Pin_8, TIM_Channel_3, TIM8_CC_IRQn, 1, Mode_AF_PP_PD}, // PWM6 - PC8
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{ TIM15, GPIOF, Pin_9, TIM_Channel_1, TIM1_BRK_TIM15_IRQn, 0, Mode_AF_PP_PD}, // PWM7 - PF9
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{ TIM15, GPIOF, Pin_10, TIM_Channel_2, TIM1_BRK_TIM15_IRQn, 0, Mode_AF_PP_PD}, // PWM8 - PF10
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// OUTPUTS CH1-10
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{ TIM4, GPIOD, Pin_12, TIM_Channel_1, TIM4_IRQn, 0, Mode_AF_PP}, // PWM9 - PD12
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{ TIM4, GPIOD, Pin_13, TIM_Channel_2, TIM4_IRQn, 0, Mode_AF_PP}, // PWM10 - PD13
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{ TIM4, GPIOD, Pin_14, TIM_Channel_3, TIM4_IRQn, 0, Mode_AF_PP}, // PWM11 - PD14
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{ TIM4, GPIOD, Pin_15, TIM_Channel_4, TIM4_IRQn, 0, Mode_AF_PP}, // PWM12 - PD15
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{ TIM2, GPIOA, Pin_1, TIM_Channel_2, TIM2_IRQn, 0, Mode_AF_PP}, // PWM13 - PA1
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{ TIM2, GPIOA, Pin_2, TIM_Channel_3, TIM2_IRQn, 0, Mode_AF_PP}, // PWM14 - PA2
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{ TIM2, GPIOA, Pin_3, TIM_Channel_4, TIM2_IRQn, 0, Mode_AF_PP}, // PWM15 - PA3
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{ TIM3, GPIOB, Pin_0, TIM_Channel_3, TIM3_IRQn, 0, Mode_AF_PP}, // PWM16 - PB0
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{ TIM3, GPIOB, Pin_1, TIM_Channel_4, TIM3_IRQn, 0, Mode_AF_PP}, // PWM17 - PB1
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{ TIM3, GPIOA, Pin_4, TIM_Channel_2, TIM3_IRQn, 0, Mode_AF_PP} // PWM18 - PA4
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};
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#define MAX_TIMERS 8
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static const TIM_TypeDef *timers[MAX_TIMERS] = {
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TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16, TIM17
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};
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#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4)
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#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM8 | RCC_APB2Periph_TIM15 | RCC_APB2Periph_TIM16 | RCC_APB2Periph_TIM17)
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#define TIMER_AHB_PERIPHERALS (RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC | RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOF)
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#endif
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#ifdef NAZE32PRO
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const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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{ TIM1, GPIOA, Pin_8, TIM_Channel_1, TIM1_CC_IRQn, 0, Mode_AF_PP_PD}, // PA8 - AF6
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{ TIM1, GPIOA, Pin_9, TIM_Channel_2, TIM1_CC_IRQn, 0, Mode_AF_PP_PD}, // PA9 - AF6
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{ TIM1, GPIOA, Pin_10, TIM_Channel_3, TIM1_CC_IRQn, 0, Mode_AF_PP_PD}, // PA10 - AF6
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{ TIM3, GPIOB, Pin_4, TIM_Channel_1, TIM3_IRQn, 0, Mode_AF_PP_PD}, // PB3 - AF2
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{ TIM4, GPIOB, Pin_6, TIM_Channel_1, TIM4_IRQn, 0, Mode_AF_PP_PD}, // PB6 - AF2 - not working yet
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{ TIM4, GPIOB, Pin_7, TIM_Channel_2, TIM4_IRQn, 0, Mode_AF_PP_PD}, // PB7 - AF2 - not working yet
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{ TIM4, GPIOB, Pin_8, TIM_Channel_3, TIM4_IRQn, 0, Mode_AF_PP_PD}, // PB8 - AF2
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{ TIM4, GPIOB, Pin_9, TIM_Channel_4, TIM4_IRQn, 0, Mode_AF_PP_PD}, // PB9 - AF2
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{ TIM2, GPIOA, Pin_0, TIM_Channel_1, TIM2_IRQn, 1, Mode_AF_PP}, // PA0 - untested
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{ TIM2, GPIOA, Pin_1, TIM_Channel_2, TIM2_IRQn, 1, Mode_AF_PP}, // PA1 - untested
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{ TIM15, GPIOA, Pin_2, TIM_Channel_1, TIM1_BRK_TIM15_IRQn, 1, Mode_AF_PP}, // PA2 - untested
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{ TIM15, GPIOA, Pin_3, TIM_Channel_2, TIM1_BRK_TIM15_IRQn, 1, Mode_AF_PP}, // PA3 - untested
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{ TIM16, GPIOA, Pin_6, TIM_Channel_1, TIM1_UP_TIM16_IRQn, 1, Mode_AF_PP}, // PA6 - untested
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{ TIM17, GPIOA, Pin_7, TIM_Channel_1, TIM1_TRG_COM_TIM17_IRQn, 1, Mode_AF_PP}, // PA7 - untested
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};
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#define MAX_TIMERS 7
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static const TIM_TypeDef *timers[MAX_TIMERS] = {
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TIM1, TIM2, TIM3, TIM4, TIM15, TIM16, TIM17
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};
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#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4)
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#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM15 | RCC_APB2Periph_TIM16 | RCC_APB2Periph_TIM17)
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#define TIMER_AHB_PERIPHERALS (RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB)
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#endif
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#define CC_CHANNELS_PER_TIMER 4 // TIM_Channel_1..4
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static const uint16_t channels[CC_CHANNELS_PER_TIMER] = {
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TIM_Channel_1, TIM_Channel_2, TIM_Channel_3, TIM_Channel_4
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};
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typedef struct timerConfig_s {
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TIM_TypeDef *tim;
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uint8_t channel;
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timerCCCallbackPtr *callback;
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uint8_t reference;
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} timerConfig_t;
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static timerConfig_t timerConfig[MAX_TIMERS * CC_CHANNELS_PER_TIMER];
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static uint8_t lookupTimerIndex(const TIM_TypeDef *tim)
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{
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uint8_t timerIndex = 0;
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while (timers[timerIndex] != tim) {
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timerIndex++;
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}
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return timerIndex;
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}
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static uint8_t lookupChannelIndex(const uint16_t channel)
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{
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uint8_t channelIndex = 0;
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while (channels[channelIndex] != channel) {
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channelIndex++;
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}
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return channelIndex;
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}
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static uint8_t lookupTimerConfigIndex(TIM_TypeDef *tim, const uint16_t channel)
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{
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return lookupTimerIndex(tim) + (MAX_TIMERS * lookupChannelIndex(channel));
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}
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void configureTimerChannelCallback(TIM_TypeDef *tim, uint8_t channel, uint8_t reference, timerCCCallbackPtr *callback)
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{
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assert_param(IS_TIM_CHANNEL(channel));
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uint8_t timerConfigIndex = lookupTimerConfigIndex(tim, channel);
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if (timerConfigIndex >= MAX_TIMERS * CC_CHANNELS_PER_TIMER) {
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return;
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}
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timerConfig[timerConfigIndex].callback = callback;
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timerConfig[timerConfigIndex].channel = channel;
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timerConfig[timerConfigIndex].reference = reference;
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}
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void configureTimerInputCaptureCompareChannel(TIM_TypeDef *tim, const uint8_t channel)
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{
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switch (channel) {
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case TIM_Channel_1:
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TIM_ITConfig(tim, TIM_IT_CC1, ENABLE);
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break;
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case TIM_Channel_2:
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TIM_ITConfig(tim, TIM_IT_CC2, ENABLE);
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break;
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case TIM_Channel_3:
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TIM_ITConfig(tim, TIM_IT_CC3, ENABLE);
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break;
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case TIM_Channel_4:
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TIM_ITConfig(tim, TIM_IT_CC4, ENABLE);
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break;
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}
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}
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void configureTimerCaptureCompareInterrupt(const timerHardware_t *timerHardwarePtr, uint8_t reference, timerCCCallbackPtr *callback)
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{
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configureTimerChannelCallback(timerHardwarePtr->tim, timerHardwarePtr->channel, reference, callback);
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configureTimerInputCaptureCompareChannel(timerHardwarePtr->tim, timerHardwarePtr->channel);
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}
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void timerNVICConfigure(uint8_t irq)
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{
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NVIC_InitTypeDef NVIC_InitStructure;
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NVIC_InitStructure.NVIC_IRQChannel = irq;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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}
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void configTimeBase(TIM_TypeDef *tim, uint16_t period, uint8_t mhz)
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{
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TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
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TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
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TIM_TimeBaseStructure.TIM_Period = period - 1; // AKA TIMx_ARR
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// "The counter clock frequency (CK_CNT) is equal to f CK_PSC / (PSC[15:0] + 1)." - STM32F10x Reference Manual 14.4.11
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// Thus for 1Mhz: 72000000 / 1000000 = 72, 72 - 1 = 71 = TIM_Prescaler
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TIM_TimeBaseStructure.TIM_Prescaler = (SystemCoreClock / ((uint32_t)mhz * 1000000)) - 1;
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TIM_TimeBaseStructure.TIM_ClockDivision = 0;
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TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
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TIM_TimeBaseInit(tim, &TIM_TimeBaseStructure);
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}
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void timerConfigure(const timerHardware_t *timerHardwarePtr, uint16_t period, uint8_t mhz)
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{
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configTimeBase(timerHardwarePtr->tim, period, mhz);
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TIM_Cmd(timerHardwarePtr->tim, ENABLE);
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timerNVICConfigure(timerHardwarePtr->irq);
|
|
}
|
|
|
|
timerConfig_t *findTimerConfig(TIM_TypeDef *tim, uint16_t channel)
|
|
{
|
|
uint8_t timerConfigIndex = lookupTimerConfigIndex(tim, channel);
|
|
return &(timerConfig[timerConfigIndex]);
|
|
}
|
|
|
|
static void timCCxHandler(TIM_TypeDef *tim)
|
|
{
|
|
captureCompare_t capture;
|
|
timerConfig_t *timerConfig;
|
|
|
|
uint8_t channelIndex = 0;
|
|
for (channelIndex = 0; channelIndex < CC_CHANNELS_PER_TIMER; channelIndex++) {
|
|
uint8_t channel = channels[channelIndex];
|
|
|
|
if (channel == TIM_Channel_1 && TIM_GetITStatus(tim, TIM_IT_CC1) == SET) {
|
|
TIM_ClearITPendingBit(tim, TIM_IT_CC1);
|
|
|
|
timerConfig = findTimerConfig(tim, TIM_Channel_1);
|
|
capture = TIM_GetCapture1(tim);
|
|
} else if (channel == TIM_Channel_2 && TIM_GetITStatus(tim, TIM_IT_CC2) == SET) {
|
|
TIM_ClearITPendingBit(tim, TIM_IT_CC2);
|
|
|
|
timerConfig = findTimerConfig(tim, TIM_Channel_2);
|
|
capture = TIM_GetCapture2(tim);
|
|
} else if (channel == TIM_Channel_3 && TIM_GetITStatus(tim, TIM_IT_CC3) == SET) {
|
|
TIM_ClearITPendingBit(tim, TIM_IT_CC3);
|
|
|
|
timerConfig = findTimerConfig(tim, TIM_Channel_3);
|
|
capture = TIM_GetCapture3(tim);
|
|
} else if (channel == TIM_Channel_4 && TIM_GetITStatus(tim, TIM_IT_CC4) == SET) {
|
|
TIM_ClearITPendingBit(tim, TIM_IT_CC4);
|
|
|
|
timerConfig = findTimerConfig(tim, TIM_Channel_4);
|
|
capture = TIM_GetCapture4(tim);
|
|
} else {
|
|
continue; // avoid uninitialised variable dereference
|
|
}
|
|
|
|
if (!timerConfig->callback) {
|
|
continue;
|
|
}
|
|
timerConfig->callback(timerConfig->reference, capture);
|
|
}
|
|
}
|
|
|
|
void TIM1_CC_IRQHandler(void)
|
|
{
|
|
timCCxHandler(TIM1);
|
|
}
|
|
|
|
void TIM2_IRQHandler(void)
|
|
{
|
|
timCCxHandler(TIM2);
|
|
}
|
|
|
|
void TIM3_IRQHandler(void)
|
|
{
|
|
timCCxHandler(TIM3);
|
|
}
|
|
|
|
void TIM4_IRQHandler(void)
|
|
{
|
|
timCCxHandler(TIM4);
|
|
}
|
|
|
|
#if defined(STM32F303xC) || defined(STM32F3DISCOVERY)
|
|
void TIM8_CC_IRQHandler(void)
|
|
{
|
|
timCCxHandler(TIM8);
|
|
}
|
|
|
|
void TIM1_BRK_TIM15_IRQHandler(void)
|
|
{
|
|
timCCxHandler(TIM15);
|
|
}
|
|
|
|
void TIM1_UP_TIM16_IRQHandler(void)
|
|
{
|
|
timCCxHandler(TIM16);
|
|
}
|
|
|
|
void TIM1_TRG_COM_TIM17_IRQHandler(void)
|
|
{
|
|
timCCxHandler(TIM17);
|
|
}
|
|
#endif
|
|
|
|
void timerInit(void)
|
|
{
|
|
memset(timerConfig, 0, sizeof (timerConfig));
|
|
|
|
#ifdef CC3D
|
|
GPIO_PinRemapConfig(GPIO_PartialRemap_TIM3, ENABLE);
|
|
#endif
|
|
|
|
#ifdef TIMER_APB1_PERIPHERALS
|
|
RCC_APB1PeriphClockCmd(TIMER_APB1_PERIPHERALS, ENABLE);
|
|
#endif
|
|
|
|
#ifdef TIMER_APB2_PERIPHERALS
|
|
RCC_APB2PeriphClockCmd(TIMER_APB2_PERIPHERALS, ENABLE);
|
|
#endif
|
|
|
|
#ifdef TIMER_AHB_PERIPHERALS
|
|
RCC_AHBPeriphClockCmd(TIMER_AHB_PERIPHERALS, ENABLE);
|
|
#endif
|
|
|
|
|
|
#ifdef STM32F303xC
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_6);
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_1);
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_1);
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource6, GPIO_AF_4);
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource7, GPIO_AF_4);
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_4);
|
|
#ifdef CHEBUZZF3
|
|
GPIO_PinAFConfig(GPIOF, GPIO_PinSource9, GPIO_AF_3);
|
|
GPIO_PinAFConfig(GPIOF, GPIO_PinSource10, GPIO_AF_3);
|
|
#endif
|
|
GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_2);
|
|
GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_2);
|
|
GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_2);
|
|
GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_2);
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_1);
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_1);
|
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource0, GPIO_AF_2);
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource1, GPIO_AF_2);
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource4, GPIO_AF_2);
|
|
#endif
|
|
|
|
#ifdef NAZE32PRO
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_6);
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_6);
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource4, GPIO_AF_2);
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_2);
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_2);
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_2);
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_2);
|
|
#endif
|
|
}
|