mirror of
https://github.com/betaflight/betaflight.git
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97 lines
3.8 KiB
C
97 lines
3.8 KiB
C
/*
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* This file is part of Cleanflight.
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*
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* Cleanflight is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Cleanflight is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include <platform.h>
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#include "drivers/nvic.h"
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#include "drivers/dma.h"
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/*
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* DMA descriptors.
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*/
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static dmaChannelDescriptor_t dmaDescriptors[] = {
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DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream0, 0, DMA1_Stream0_IRQn, RCC_AHB1ENR_DMA1EN),
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DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream1, 6, DMA1_Stream1_IRQn, RCC_AHB1ENR_DMA1EN),
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DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream2, 16, DMA1_Stream2_IRQn, RCC_AHB1ENR_DMA1EN),
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DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream3, 22, DMA1_Stream3_IRQn, RCC_AHB1ENR_DMA1EN),
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DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream4, 32, DMA1_Stream4_IRQn, RCC_AHB1ENR_DMA1EN),
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DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream5, 38, DMA1_Stream5_IRQn, RCC_AHB1ENR_DMA1EN),
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DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream6, 48, DMA1_Stream6_IRQn, RCC_AHB1ENR_DMA1EN),
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DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream7, 54, DMA1_Stream7_IRQn, RCC_AHB1ENR_DMA1EN),
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DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream0, 0, DMA2_Stream0_IRQn, RCC_AHB1ENR_DMA2EN),
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DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream1, 6, DMA2_Stream1_IRQn, RCC_AHB1ENR_DMA2EN),
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DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream2, 16, DMA2_Stream2_IRQn, RCC_AHB1ENR_DMA2EN),
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DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream3, 22, DMA2_Stream3_IRQn, RCC_AHB1ENR_DMA2EN),
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DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream4, 32, DMA2_Stream4_IRQn, RCC_AHB1ENR_DMA2EN),
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DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream5, 38, DMA2_Stream5_IRQn, RCC_AHB1ENR_DMA2EN),
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DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream6, 48, DMA2_Stream6_IRQn, RCC_AHB1ENR_DMA2EN),
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DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream7, 54, DMA2_Stream7_IRQn, RCC_AHB1ENR_DMA2EN),
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};
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/*
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* DMA IRQ Handlers
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*/
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DEFINE_DMA_IRQ_HANDLER(1, 0, DMA1_ST0_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(1, 1, DMA1_ST1_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(1, 2, DMA1_ST2_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(1, 3, DMA1_ST3_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(1, 4, DMA1_ST4_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(1, 5, DMA1_ST5_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(1, 6, DMA1_ST6_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(1, 7, DMA1_ST7_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(2, 0, DMA2_ST0_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(2, 1, DMA2_ST1_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(2, 2, DMA2_ST2_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(2, 3, DMA2_ST3_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(2, 4, DMA2_ST4_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(2, 5, DMA2_ST5_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(2, 6, DMA2_ST6_HANDLER)
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DEFINE_DMA_IRQ_HANDLER(2, 7, DMA2_ST7_HANDLER)
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void dmaInit(void)
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{
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// TODO: Do we need this?
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}
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void dmaSetHandler(dmaHandlerIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam)
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{
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//clock
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//RCC_AHB1PeriphClockCmd(dmaDescriptors[identifier].rcc, ENABLE);
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do {
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__IO uint32_t tmpreg;
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SET_BIT(RCC->AHB1ENR, dmaDescriptors[identifier].rcc);
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->AHB1ENR, dmaDescriptors[identifier].rcc);
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UNUSED(tmpreg);
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} while(0);
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dmaDescriptors[identifier].irqHandlerCallback = callback;
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dmaDescriptors[identifier].userParam = userParam;
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HAL_NVIC_SetPriority(dmaDescriptors[identifier].irqN, NVIC_PRIORITY_BASE(priority), NVIC_PRIORITY_SUB(priority));
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HAL_NVIC_EnableIRQ(dmaDescriptors[identifier].irqN);
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}
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