mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-25 01:05:27 +03:00
770 lines
21 KiB
C
770 lines
21 KiB
C
/*
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* This file is part of Cleanflight and Betaflight.
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*
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* Cleanflight and Betaflight are free software. You can redistribute
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* this software and/or modify this software under the terms of the
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* GNU General Public License as published by the Free Software
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* Foundation, either version 3 of the License, or (at your option)
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* any later version.
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*
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* Cleanflight and Betaflight are distributed in the hope that they
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* will be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software.
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*
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include "platform.h"
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#include "build/atomic.h"
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#ifdef USE_SPI
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#include "drivers/bus.h"
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#include "drivers/bus_spi.h"
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#include "drivers/bus_spi_impl.h"
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#include "drivers/dma_reqmap.h"
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#include "drivers/exti.h"
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#include "drivers/io.h"
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#include "drivers/motor.h"
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#include "drivers/rcc.h"
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#include "nvic.h"
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#include "pg/bus_spi.h"
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static uint8_t spiRegisteredDeviceCount = 0;
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spiDevice_t spiDevice[SPIDEV_COUNT];
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busDevice_t spiBusDevice[SPIDEV_COUNT];
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SPIDevice spiDeviceByInstance(SPI_TypeDef *instance)
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{
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#ifdef USE_SPI_DEVICE_1
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if (instance == SPI1) {
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return SPIDEV_1;
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}
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#endif
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#ifdef USE_SPI_DEVICE_2
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if (instance == SPI2) {
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return SPIDEV_2;
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}
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#endif
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#ifdef USE_SPI_DEVICE_3
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if (instance == SPI3) {
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return SPIDEV_3;
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}
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#endif
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#ifdef USE_SPI_DEVICE_4
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if (instance == SPI4) {
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return SPIDEV_4;
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}
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#endif
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#ifdef USE_SPI_DEVICE_5
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if (instance == SPI5) {
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return SPIDEV_5;
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}
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#endif
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#ifdef USE_SPI_DEVICE_6
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if (instance == SPI6) {
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return SPIDEV_6;
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}
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#endif
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return SPIINVALID;
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}
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SPI_TypeDef *spiInstanceByDevice(SPIDevice device)
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{
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if (device == SPIINVALID || device >= SPIDEV_COUNT) {
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return NULL;
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}
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return spiDevice[device].dev;
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}
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bool spiInit(SPIDevice device)
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{
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switch (device) {
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case SPIINVALID:
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return false;
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case SPIDEV_1:
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#ifdef USE_SPI_DEVICE_1
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spiInitDevice(device);
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return true;
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#else
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break;
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#endif
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case SPIDEV_2:
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#ifdef USE_SPI_DEVICE_2
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spiInitDevice(device);
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return true;
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#else
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break;
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#endif
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case SPIDEV_3:
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#if defined(USE_SPI_DEVICE_3) && !defined(STM32F1)
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spiInitDevice(device);
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return true;
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#else
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break;
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#endif
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case SPIDEV_4:
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#if defined(USE_SPI_DEVICE_4)
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spiInitDevice(device);
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return true;
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#else
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break;
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#endif
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case SPIDEV_5:
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#if defined(USE_SPI_DEVICE_5)
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spiInitDevice(device);
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return true;
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#else
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break;
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#endif
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case SPIDEV_6:
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#if defined(USE_SPI_DEVICE_6)
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spiInitDevice(device);
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return true;
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#else
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break;
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#endif
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}
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return false;
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}
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// Return true if DMA engine is busy
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bool spiIsBusy(const extDevice_t *dev)
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{
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return (dev->bus->curSegment != (busSegment_t *)BUS_SPI_FREE);
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}
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// Indicate that the bus on which this device resides may initiate DMA transfers from interrupt context
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void spiSetAtomicWait(const extDevice_t *dev)
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{
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dev->bus->useAtomicWait = true;
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}
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// Wait for DMA completion and claim the bus driver
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void spiWaitClaim(const extDevice_t *dev)
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{
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// If there is a device on the bus whose driver might call spiSequence from an ISR then an
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// atomic access is required to claim the bus, however if not, then interrupts need not be
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// disabled as this can result in edge triggered interrupts being missed
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if (dev->bus->useAtomicWait) {
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// Prevent race condition where the bus appears free, but a gyro interrupt starts a transfer
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do {
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ATOMIC_BLOCK(NVIC_PRIO_MAX) {
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if (dev->bus->curSegment == (busSegment_t *)BUS_SPI_FREE) {
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dev->bus->curSegment = (busSegment_t *)BUS_SPI_LOCKED;
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}
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}
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} while (dev->bus->curSegment != (busSegment_t *)BUS_SPI_LOCKED);
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} else {
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// Wait for completion
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while (dev->bus->curSegment != (busSegment_t *)BUS_SPI_FREE);
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}
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}
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// Wait for DMA completion
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void spiWait(const extDevice_t *dev)
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{
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// Wait for completion
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while (dev->bus->curSegment != (busSegment_t *)BUS_SPI_FREE);
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}
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// Wait for bus to become free, then read/write block of data
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void spiReadWriteBuf(const extDevice_t *dev, uint8_t *txData, uint8_t *rxData, int len)
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{
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{txData, rxData, len, true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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}
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// Read/Write a block of data, returning false if the bus is busy
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bool spiReadWriteBufRB(const extDevice_t *dev, uint8_t *txData, uint8_t *rxData, int length)
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{
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// Ensure any prior DMA has completed before continuing
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if (spiIsBusy(dev)) {
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return false;
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}
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spiReadWriteBuf(dev, txData, rxData, length);
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return true;
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}
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// Wait for bus to become free, then read/write a single byte
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uint8_t spiReadWrite(const extDevice_t *dev, uint8_t data)
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{
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uint8_t retval;
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{&data, &retval, sizeof(data), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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return retval;
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}
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// Wait for bus to become free, then read/write a single byte from a register
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uint8_t spiReadWriteReg(const extDevice_t *dev, uint8_t reg, uint8_t data)
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{
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uint8_t retval;
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{®, NULL, sizeof(reg), false, NULL},
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{&data, &retval, sizeof(data), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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return retval;
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}
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// Wait for bus to become free, then write a single byte
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void spiWrite(const extDevice_t *dev, uint8_t data)
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{
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{&data, NULL, sizeof(data), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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}
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// Write data to a register
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void spiWriteReg(const extDevice_t *dev, uint8_t reg, uint8_t data)
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{
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{®, NULL, sizeof(reg), false, NULL},
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{&data, NULL, sizeof(data), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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}
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// Write data to a register, returning false if the bus is busy
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bool spiWriteRegRB(const extDevice_t *dev, uint8_t reg, uint8_t data)
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{
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// Ensure any prior DMA has completed before continuing
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if (spiIsBusy(dev)) {
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return false;
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}
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spiWriteReg(dev, reg, data);
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return true;
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}
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// Read a block of data from a register
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void spiReadRegBuf(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint8_t length)
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{
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{®, NULL, sizeof(reg), false, NULL},
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{NULL, data, length, true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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}
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// Read a block of data from a register, returning false if the bus is busy
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bool spiReadRegBufRB(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint8_t length)
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{
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// Ensure any prior DMA has completed before continuing
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if (spiIsBusy(dev)) {
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return false;
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}
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spiReadRegBuf(dev, reg, data, length);
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return true;
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}
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// Read a block of data where the register is ORed with 0x80, returning false if the bus is busy
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bool spiReadRegMskBufRB(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint8_t length)
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{
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return spiReadRegBufRB(dev, reg | 0x80, data, length);
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}
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// Wait for bus to become free, then write a block of data to a register
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void spiWriteRegBuf(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint32_t length)
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{
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{®, NULL, sizeof(reg), false, NULL},
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{data, NULL, length, true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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}
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// Wait for bus to become free, then read a byte from a register
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uint8_t spiReadReg(const extDevice_t *dev, uint8_t reg)
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{
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uint8_t data;
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{®, NULL, sizeof(reg), false, NULL},
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{NULL, &data, sizeof(data), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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return data;
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}
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// Wait for bus to become free, then read a byte of data where the register is ORed with 0x80
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uint8_t spiReadRegMsk(const extDevice_t *dev, uint8_t reg)
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{
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return spiReadReg(dev, reg | 0x80);
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}
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uint16_t spiCalculateDivider(uint32_t freq)
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{
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#if defined(STM32F4) || defined(STM32G4) || defined(STM32F7)
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uint32_t spiClk = SystemCoreClock / 2;
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#elif defined(STM32H7)
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uint32_t spiClk = 100000000;
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#else
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#error "Base SPI clock not defined for this architecture"
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#endif
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uint16_t divisor = 2;
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spiClk >>= 1;
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for (; (spiClk > freq) && (divisor < 256); divisor <<= 1, spiClk >>= 1);
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return divisor;
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}
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// Interrupt handler for SPI receive DMA completion
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static void spiIrqHandler(const extDevice_t *dev)
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{
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busDevice_t *bus = dev->bus;
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busSegment_t *nextSegment;
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if (bus->curSegment->callback) {
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switch(bus->curSegment->callback(dev->callbackArg)) {
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case BUS_BUSY:
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// Repeat the last DMA segment
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bus->curSegment--;
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// Reinitialise the cached init values as segment is not progressing
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spiInternalInitStream(dev, true);
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break;
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case BUS_ABORT:
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bus->curSegment = (busSegment_t *)BUS_SPI_FREE;
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return;
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case BUS_READY:
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default:
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// Advance to the next DMA segment
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break;
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}
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}
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// Advance through the segment list
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nextSegment = bus->curSegment + 1;
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if (nextSegment->len == 0) {
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// If a following transaction has been linked, start it
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if (nextSegment->txData) {
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const extDevice_t *nextDev = (const extDevice_t *)nextSegment->txData;
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busSegment_t *nextSegments = (busSegment_t *)nextSegment->rxData;
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nextSegment->txData = NULL;
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// The end of the segment list has been reached
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spiSequenceStart(nextDev, nextSegments);
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} else {
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// The end of the segment list has been reached, so mark transactions as complete
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bus->curSegment = (busSegment_t *)BUS_SPI_FREE;
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}
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} else {
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bus->curSegment = nextSegment;
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// After the completion of the first segment setup the init structure for the subsequent segment
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if (bus->initSegment) {
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spiInternalInitStream(dev, false);
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bus->initSegment = false;
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}
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// Launch the next transfer
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spiInternalStartDMA(dev);
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// Prepare the init structures ready for the next segment to reduce inter-segment time
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spiInternalInitStream(dev, true);
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}
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}
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// Interrupt handler for SPI receive DMA completion
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static void spiRxIrqHandler(dmaChannelDescriptor_t* descriptor)
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{
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const extDevice_t *dev = (const extDevice_t *)descriptor->userParam;
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if (!dev) {
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return;
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}
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busDevice_t *bus = dev->bus;
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if (bus->curSegment->negateCS) {
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// Negate Chip Select
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IOHi(dev->busType_u.spi.csnPin);
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}
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spiInternalStopDMA(dev);
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#ifdef __DCACHE_PRESENT
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#ifdef STM32H7
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if (bus->curSegment->rxData &&
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((bus->curSegment->rxData < &_dmaram_start__) || (bus->curSegment->rxData >= &_dmaram_end__))) {
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#else
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if (bus->curSegment->rxData) {
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#endif
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// Invalidate the D cache covering the area into which data has been read
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SCB_InvalidateDCache_by_Addr(
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(uint32_t *)((uint32_t)bus->curSegment->rxData & ~CACHE_LINE_MASK),
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(((uint32_t)bus->curSegment->rxData & CACHE_LINE_MASK) +
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bus->curSegment->len - 1 + CACHE_LINE_SIZE) & ~CACHE_LINE_MASK);
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}
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#endif // __DCACHE_PRESENT
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spiIrqHandler(dev);
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}
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#if !defined(STM32G4) && !defined(STM32H7)
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// Interrupt handler for SPI transmit DMA completion
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static void spiTxIrqHandler(dmaChannelDescriptor_t* descriptor)
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{
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const extDevice_t *dev = (const extDevice_t *)descriptor->userParam;
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if (!dev) {
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return;
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}
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busDevice_t *bus = dev->bus;
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spiInternalStopDMA(dev);
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if (bus->curSegment->negateCS) {
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// Negate Chip Select
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IOHi(dev->busType_u.spi.csnPin);
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}
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spiIrqHandler(dev);
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}
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#endif
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// Mark this bus as being SPI and record the first owner to use it
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bool spiSetBusInstance(extDevice_t *dev, uint32_t device)
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{
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if ((device == 0) || (device > SPIDEV_COUNT)) {
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return false;
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}
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dev->bus = &spiBusDevice[SPI_CFG_TO_DEV(device)];
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// By default each device should use SPI DMA if the bus supports it
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dev->useDMA = true;
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if (dev->bus->busType == BUS_TYPE_SPI) {
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// This bus has already been initialised
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dev->bus->deviceCount++;
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return true;
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}
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busDevice_t *bus = dev->bus;
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bus->busType_u.spi.instance = spiInstanceByDevice(SPI_CFG_TO_DEV(device));
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if (bus->busType_u.spi.instance == NULL) {
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return false;
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}
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bus->busType = BUS_TYPE_SPI;
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bus->useDMA = false;
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bus->useAtomicWait = false;
|
|
bus->deviceCount = 1;
|
|
bus->initTx = &dev->initTx;
|
|
bus->initRx = &dev->initRx;
|
|
|
|
return true;
|
|
}
|
|
|
|
void spiInitBusDMA()
|
|
{
|
|
uint32_t device;
|
|
#if defined(STM32F4) && defined(USE_DSHOT_BITBANG)
|
|
/* Check https://www.st.com/resource/en/errata_sheet/dm00037591-stm32f405407xx-and-stm32f415417xx-device-limitations-stmicroelectronics.pdf
|
|
* section 2.1.10 which reports an errata that corruption may occurs on DMA2 if AHB peripherals (eg GPIO ports) are
|
|
* access concurrently with APB peripherals (eg SPI busses). Bitbang DSHOT uses DMA2 to write to GPIO ports. If this
|
|
* is enabled, then don't enable DMA on an SPI bus using DMA2
|
|
*/
|
|
const bool dshotBitbangActive = isDshotBitbangActive(&motorConfig()->dev);
|
|
#endif
|
|
|
|
for (device = 0; device < SPIDEV_COUNT; device++) {
|
|
busDevice_t *bus = &spiBusDevice[device];
|
|
|
|
if (bus->busType != BUS_TYPE_SPI) {
|
|
// This bus is not in use
|
|
continue;
|
|
}
|
|
|
|
dmaIdentifier_e dmaTxIdentifier = DMA_NONE;
|
|
dmaIdentifier_e dmaRxIdentifier = DMA_NONE;
|
|
|
|
int8_t txDmaopt = spiPinConfig(device)->txDmaopt;
|
|
uint8_t txDmaoptMin = 0;
|
|
uint8_t txDmaoptMax = MAX_PERIPHERAL_DMA_OPTIONS - 1;
|
|
|
|
if (txDmaopt != -1) {
|
|
txDmaoptMin = txDmaopt;
|
|
txDmaoptMax = txDmaopt;
|
|
}
|
|
|
|
for (uint8_t opt = txDmaoptMin; opt <= txDmaoptMax; opt++) {
|
|
const dmaChannelSpec_t *dmaTxChannelSpec = dmaGetChannelSpecByPeripheral(DMA_PERIPH_SPI_MOSI, device, opt);
|
|
|
|
if (dmaTxChannelSpec) {
|
|
dmaTxIdentifier = dmaGetIdentifier(dmaTxChannelSpec->ref);
|
|
if (!dmaAllocate(dmaTxIdentifier, OWNER_SPI_MOSI, device + 1)) {
|
|
dmaTxIdentifier = DMA_NONE;
|
|
continue;
|
|
}
|
|
#if defined(STM32F4) && defined(USE_DSHOT_BITBANG)
|
|
if (dshotBitbangActive && (DMA_DEVICE_NO(dmaTxIdentifier) == 2)) {
|
|
dmaTxIdentifier = DMA_NONE;
|
|
break;
|
|
}
|
|
#endif
|
|
bus->dmaTx = dmaGetDescriptorByIdentifier(dmaTxIdentifier);
|
|
bus->dmaTx->stream = DMA_DEVICE_INDEX(dmaTxIdentifier);
|
|
bus->dmaTx->channel = dmaTxChannelSpec->channel;
|
|
|
|
dmaEnable(dmaTxIdentifier);
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
int8_t rxDmaopt = spiPinConfig(device)->rxDmaopt;
|
|
uint8_t rxDmaoptMin = 0;
|
|
uint8_t rxDmaoptMax = MAX_PERIPHERAL_DMA_OPTIONS - 1;
|
|
|
|
if (rxDmaopt != -1) {
|
|
rxDmaoptMin = rxDmaopt;
|
|
rxDmaoptMax = rxDmaopt;
|
|
}
|
|
|
|
for (uint8_t opt = rxDmaoptMin; opt <= rxDmaoptMax; opt++) {
|
|
const dmaChannelSpec_t *dmaRxChannelSpec = dmaGetChannelSpecByPeripheral(DMA_PERIPH_SPI_MISO, device, opt);
|
|
|
|
if (dmaRxChannelSpec) {
|
|
dmaRxIdentifier = dmaGetIdentifier(dmaRxChannelSpec->ref);
|
|
if (!dmaAllocate(dmaRxIdentifier, OWNER_SPI_MISO, device + 1)) {
|
|
dmaRxIdentifier = DMA_NONE;
|
|
continue;
|
|
}
|
|
#if defined(STM32F4) && defined(USE_DSHOT_BITBANG)
|
|
if (dshotBitbangActive && (DMA_DEVICE_NO(dmaRxIdentifier) == 2)) {
|
|
dmaRxIdentifier = DMA_NONE;
|
|
break;
|
|
}
|
|
#endif
|
|
bus->dmaRx = dmaGetDescriptorByIdentifier(dmaRxIdentifier);
|
|
bus->dmaRx->stream = DMA_DEVICE_INDEX(dmaRxIdentifier);
|
|
bus->dmaRx->channel = dmaRxChannelSpec->channel;
|
|
|
|
dmaEnable(dmaRxIdentifier);
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (dmaTxIdentifier && dmaRxIdentifier) {
|
|
// Ensure streams are disabled
|
|
spiInternalResetStream(bus->dmaRx);
|
|
spiInternalResetStream(bus->dmaTx);
|
|
|
|
spiInternalResetDescriptors(bus);
|
|
|
|
/* Note that this driver may be called both from the normal thread of execution, or from USB interrupt
|
|
* handlers, so the DMA completion interrupt must be at a higher priority
|
|
*/
|
|
dmaSetHandler(dmaRxIdentifier, spiRxIrqHandler, NVIC_PRIO_SPI_DMA, 0);
|
|
|
|
bus->useDMA = true;
|
|
#if !defined(STM32G4) && !defined(STM32H7)
|
|
} else if (dmaTxIdentifier) {
|
|
// Transmit on DMA is adequate for OSD so worth having
|
|
bus->dmaTx = dmaGetDescriptorByIdentifier(dmaTxIdentifier);
|
|
bus->dmaRx = (dmaChannelDescriptor_t *)NULL;
|
|
|
|
// Ensure streams are disabled
|
|
spiInternalResetStream(bus->dmaTx);
|
|
|
|
spiInternalResetDescriptors(bus);
|
|
|
|
dmaSetHandler(dmaTxIdentifier, spiTxIrqHandler, NVIC_PRIO_SPI_DMA, 0);
|
|
|
|
bus->useDMA = true;
|
|
#endif
|
|
} else {
|
|
// Disassociate channels from bus
|
|
bus->dmaRx = (dmaChannelDescriptor_t *)NULL;
|
|
bus->dmaTx = (dmaChannelDescriptor_t *)NULL;
|
|
}
|
|
}
|
|
}
|
|
|
|
void spiSetClkDivisor(const extDevice_t *dev, uint16_t divisor)
|
|
{
|
|
((extDevice_t *)dev)->busType_u.spi.speed = divisor;
|
|
}
|
|
|
|
// Set the clock phase/polarity to be used for accesses by the given device
|
|
void spiSetClkPhasePolarity(const extDevice_t *dev, bool leadingEdge)
|
|
{
|
|
((extDevice_t *)dev)->busType_u.spi.leadingEdge = leadingEdge;
|
|
}
|
|
|
|
// Enable/disable DMA on a specific device. Enabled by default.
|
|
void spiDmaEnable(const extDevice_t *dev, bool enable)
|
|
{
|
|
((extDevice_t *)dev)->useDMA = enable;
|
|
}
|
|
|
|
bool spiUseDMA(const extDevice_t *dev)
|
|
{
|
|
// Full DMA only requires both transmit and receive}
|
|
return dev->bus->useDMA && dev->bus->dmaRx && dev->useDMA;
|
|
}
|
|
|
|
bool spiUseMOSI_DMA(const extDevice_t *dev)
|
|
{
|
|
return dev->bus->useDMA && dev->useDMA;
|
|
}
|
|
|
|
void spiBusDeviceRegister(const extDevice_t *dev)
|
|
{
|
|
UNUSED(dev);
|
|
|
|
spiRegisteredDeviceCount++;
|
|
}
|
|
|
|
uint8_t spiGetRegisteredDeviceCount(void)
|
|
{
|
|
return spiRegisteredDeviceCount;
|
|
}
|
|
|
|
uint8_t spiGetExtDeviceCount(const extDevice_t *dev)
|
|
{
|
|
return dev->bus->deviceCount;
|
|
}
|
|
|
|
// DMA transfer setup and start
|
|
void spiSequence(const extDevice_t *dev, busSegment_t *segments)
|
|
{
|
|
busDevice_t *bus = dev->bus;
|
|
|
|
ATOMIC_BLOCK(NVIC_PRIO_MAX) {
|
|
if ((bus->curSegment != (busSegment_t *)BUS_SPI_LOCKED) && spiIsBusy(dev)) {
|
|
/* Defer this transfer to be triggered upon completion of the current transfer. Blocking calls
|
|
* and those from non-interrupt context will have already called spiWaitClaim() so this will
|
|
* only happen for non-blocking calls called from an ISR.
|
|
*/
|
|
busSegment_t *endSegment = bus->curSegment;
|
|
|
|
if (endSegment) {
|
|
// Find the last segment of the current transfer
|
|
for (; endSegment->len; endSegment++);
|
|
|
|
// Record the dev and segments parameters in the terminating segment entry
|
|
endSegment->txData = (uint8_t *)dev;
|
|
endSegment->rxData = (uint8_t *)segments;
|
|
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
spiSequenceStart(dev, segments);
|
|
}
|
|
#endif
|