mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-15 20:35:33 +03:00
290 lines
8.3 KiB
C
290 lines
8.3 KiB
C
/*
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* This file is part of Cleanflight.
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*
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* Cleanflight is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Cleanflight is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Authors:
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* Dominic Clifton/Hydra - Various cleanups for Cleanflight
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* Bill Nesbitt - Code from AutoQuad
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* Hamasaki/Timecop - Initial baseflight code
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <platform.h>
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#include "system.h"
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#include "io.h"
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#include "nvic.h"
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#include "dma.h"
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#include "rcc.h"
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#include "serial.h"
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#include "serial_uart.h"
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#include "serial_uart_impl.h"
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#ifdef USE_UART1
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static uartPort_t uartPort1;
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#endif
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#ifdef USE_UART2
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static uartPort_t uartPort2;
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#endif
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#ifdef USE_UART3
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static uartPort_t uartPort3;
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#endif
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void uartIrqCallback(uartPort_t *s)
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{
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uint16_t SR = s->USARTx->SR;
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if (SR & USART_FLAG_RXNE && !s->rxDMAChannel) {
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// If we registered a callback, pass crap there
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if (s->port.callback) {
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s->port.callback(s->USARTx->DR);
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} else {
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s->port.rxBuffer[s->port.rxBufferHead++] = s->USARTx->DR;
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if (s->port.rxBufferHead >= s->port.rxBufferSize) {
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s->port.rxBufferHead = 0;
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}
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}
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}
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if (SR & USART_FLAG_TXE) {
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if (s->port.txBufferTail != s->port.txBufferHead) {
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s->USARTx->DR = s->port.txBuffer[s->port.txBufferTail++];
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if (s->port.txBufferTail >= s->port.txBufferSize) {
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s->port.txBufferTail = 0;
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}
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} else {
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USART_ITConfig(s->USARTx, USART_IT_TXE, DISABLE);
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}
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}
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}
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// USART1 Tx DMA Handler
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void uart_tx_dma_IRQHandler(dmaChannelDescriptor_t* descriptor)
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{
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uartPort_t *s = (uartPort_t*)(descriptor->userParam);
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DMA_CLEAR_FLAG(descriptor, DMA_IT_TCIF);
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DMA_Cmd(descriptor->channel, DISABLE);
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if (s->port.txBufferHead != s->port.txBufferTail)
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uartStartTxDMA(s);
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else
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s->txDMAEmpty = true;
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}
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#ifdef USE_UART1
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// USART1 - Telemetry (RX/TX by DMA)
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uartPort_t *serialUART1(uint32_t baudRate, portMode_t mode, portOptions_t options)
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{
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uartPort_t *s;
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static volatile uint8_t rx1Buffer[UART1_RX_BUFFER_SIZE];
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static volatile uint8_t tx1Buffer[UART1_TX_BUFFER_SIZE];
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s = &uartPort1;
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s->port.vTable = uartVTable;
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s->port.baudRate = baudRate;
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s->port.rxBuffer = rx1Buffer;
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s->port.txBuffer = tx1Buffer;
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s->port.rxBufferSize = UART1_RX_BUFFER_SIZE;
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s->port.txBufferSize = UART1_TX_BUFFER_SIZE;
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s->USARTx = USART1;
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#ifdef USE_UART1_RX_DMA
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s->rxDMAChannel = DMA1_Channel5;
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s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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#endif
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s->txDMAChannel = DMA1_Channel4;
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s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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RCC_ClockCmd(RCC_APB2(USART1), ENABLE);
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RCC_ClockCmd(RCC_AHB(DMA1), ENABLE);
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// UART1_TX PA9
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// UART1_RX PA10
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if (options & SERIAL_BIDIR) {
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IOInit(IOGetByTag(IO_TAG(PA9)), OWNER_SERIAL, RESOURCE_UART_TXRX, 1);
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IOConfigGPIO(IOGetByTag(IO_TAG(PA9)), IOCFG_AF_OD);
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} else {
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if (mode & MODE_TX) {
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IOInit(IOGetByTag(IO_TAG(PA9)), OWNER_SERIAL, RESOURCE_UART_TX, 1);
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IOConfigGPIO(IOGetByTag(IO_TAG(PA9)), IOCFG_AF_PP);
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}
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if (mode & MODE_RX) {
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IOInit(IOGetByTag(IO_TAG(PA10)), OWNER_SERIAL, RESOURCE_UART_RX, 1);
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IOConfigGPIO(IOGetByTag(IO_TAG(PA10)), IOCFG_IPU);
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}
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}
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// DMA TX Interrupt
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dmaSetHandler(DMA1_CH4_HANDLER, uart_tx_dma_IRQHandler, NVIC_PRIO_SERIALUART1_TXDMA, (uint32_t)&uartPort1);
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#ifndef USE_UART1_RX_DMA
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// RX/TX Interrupt
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NVIC_InitTypeDef NVIC_InitStructure;
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NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(NVIC_PRIO_SERIALUART1);
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(NVIC_PRIO_SERIALUART1);
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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#endif
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return s;
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}
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// USART1 Rx/Tx IRQ Handler
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void USART1_IRQHandler(void)
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{
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uartPort_t *s = &uartPort1;
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uartIrqCallback(s);
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}
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#endif
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#ifdef USE_UART2
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// USART2 - GPS or Spektrum or ?? (RX + TX by IRQ)
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uartPort_t *serialUART2(uint32_t baudRate, portMode_t mode, portOptions_t options)
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{
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uartPort_t *s;
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static volatile uint8_t rx2Buffer[UART2_RX_BUFFER_SIZE];
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static volatile uint8_t tx2Buffer[UART2_TX_BUFFER_SIZE];
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NVIC_InitTypeDef NVIC_InitStructure;
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s = &uartPort2;
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s->port.vTable = uartVTable;
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s->port.baudRate = baudRate;
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s->port.rxBufferSize = UART2_RX_BUFFER_SIZE;
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s->port.txBufferSize = UART2_TX_BUFFER_SIZE;
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s->port.rxBuffer = rx2Buffer;
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s->port.txBuffer = tx2Buffer;
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s->USARTx = USART2;
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s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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RCC_ClockCmd(RCC_APB1(USART2), ENABLE);
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RCC_ClockCmd(RCC_AHB(DMA1), ENABLE);
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// UART2_TX PA2
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// UART2_RX PA3
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if (options & SERIAL_BIDIR) {
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IOInit(IOGetByTag(IO_TAG(PA2)), OWNER_SERIAL, RESOURCE_UART_TXRX, 2);
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IOConfigGPIO(IOGetByTag(IO_TAG(PA2)), IOCFG_AF_OD);
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} else {
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if (mode & MODE_TX) {
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IOInit(IOGetByTag(IO_TAG(PA2)), OWNER_SERIAL, RESOURCE_UART_TX, 2);
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IOConfigGPIO(IOGetByTag(IO_TAG(PA2)), IOCFG_AF_PP);
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}
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if (mode & MODE_RX) {
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IOInit(IOGetByTag(IO_TAG(PA3)), OWNER_SERIAL, RESOURCE_UART_RX, 2);
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IOConfigGPIO(IOGetByTag(IO_TAG(PA3)), IOCFG_IPU);
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}
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}
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// RX/TX Interrupt
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NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(NVIC_PRIO_SERIALUART2);
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(NVIC_PRIO_SERIALUART2);
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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return s;
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}
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// USART2 Rx/Tx IRQ Handler
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void USART2_IRQHandler(void)
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{
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uartPort_t *s = &uartPort2;
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uartIrqCallback(s);
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}
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#endif
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#ifdef USE_UART3
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// USART3
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uartPort_t *serialUART3(uint32_t baudRate, portMode_t mode, portOptions_t options)
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{
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uartPort_t *s;
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static volatile uint8_t rx3Buffer[UART3_RX_BUFFER_SIZE];
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static volatile uint8_t tx3Buffer[UART3_TX_BUFFER_SIZE];
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NVIC_InitTypeDef NVIC_InitStructure;
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s = &uartPort3;
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s->port.vTable = uartVTable;
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s->port.baudRate = baudRate;
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s->port.rxBuffer = rx3Buffer;
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s->port.txBuffer = tx3Buffer;
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s->port.rxBufferSize = UART3_RX_BUFFER_SIZE;
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s->port.txBufferSize = UART3_TX_BUFFER_SIZE;
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s->USARTx = USART3;
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s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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RCC_ClockCmd(RCC_APB1(USART3), ENABLE);
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if (options & SERIAL_BIDIR) {
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IOInit(IOGetByTag(IO_TAG(UART3_TX_PIN)), OWNER_SERIAL, RESOURCE_UART_TXRX, 3);
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IOConfigGPIO(IOGetByTag(IO_TAG(UART3_TX_PIN)), IOCFG_AF_OD);
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} else {
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if (mode & MODE_TX) {
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IOInit(IOGetByTag(IO_TAG(UART3_TX_PIN)), OWNER_SERIAL, RESOURCE_UART_TX, 3);
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IOConfigGPIO(IOGetByTag(IO_TAG(UART3_TX_PIN)), IOCFG_AF_PP);
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}
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if (mode & MODE_RX) {
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IOInit(IOGetByTag(IO_TAG(UART3_RX_PIN)), OWNER_SERIAL, RESOURCE_UART_RX, 3);
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IOConfigGPIO(IOGetByTag(IO_TAG(UART3_RX_PIN)), IOCFG_IPU);
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}
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}
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// RX/TX Interrupt
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NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(NVIC_PRIO_SERIALUART3);
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(NVIC_PRIO_SERIALUART3);
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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return s;
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}
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// USART2 Rx/Tx IRQ Handler
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void USART3_IRQHandler(void)
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{
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uartPort_t *s = &uartPort3;
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uartIrqCallback(s);
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}
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#endif
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