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9eb7d1920b
* stm32h7: add uart4 ph13 and ph14 * stm32h7: increase UARTHARDWARE_MAX_PINS * Update src/platform/STM32/serial_uart_stm32h7xx.c Co-authored-by: Petr Ledvina <ledvinap@gmail.com> * Update src/platform/STM32/serial_uart_stm32h7xx.c Co-authored-by: Petr Ledvina <ledvinap@gmail.com> --------- Co-authored-by: Mark Haslinghuis <mark@numloq.nl> Co-authored-by: Petr Ledvina <ledvinap@gmail.com>
421 lines
14 KiB
C
421 lines
14 KiB
C
/*
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* This file is part of Cleanflight and Betaflight.
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*
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* Cleanflight and Betaflight are free software. You can redistribute
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* this software and/or modify this software under the terms of the
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* GNU General Public License as published by the Free Software
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* Foundation, either version 3 of the License, or (at your option)
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* any later version.
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*
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* Cleanflight and Betaflight are distributed in the hope that they
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* will be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software.
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*
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#if defined(STM32G474xx)
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#include "stm32g4xx.h"
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#include "stm32g4xx_hal.h"
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#include "system_stm32g4xx.h"
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#include "stm32g4xx_ll_spi.h"
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#include "stm32g4xx_ll_gpio.h"
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#include "stm32g4xx_ll_dma.h"
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#include "stm32g4xx_ll_rcc.h"
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#include "stm32g4xx_ll_bus.h"
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#include "stm32g4xx_ll_tim.h"
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#include "stm32g4xx_ll_system.h"
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#include "stm32g4xx_ll_ex.h"
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// Chip Unique ID on G4
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#define U_ID_0 (*(uint32_t*)UID_BASE)
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#define U_ID_1 (*(uint32_t*)(UID_BASE + 4))
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#define U_ID_2 (*(uint32_t*)(UID_BASE + 8))
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#define USE_PIN_AF
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#ifndef STM32G4
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#define STM32G4
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#endif
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#elif defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H723xx) || defined(STM32H725xx) || defined(STM32H730xx)
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#include "stm32h7xx.h"
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#include "stm32h7xx_hal.h"
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#include "system_stm32h7xx.h"
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#include "stm32h7xx_ll_spi.h"
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#include "stm32h7xx_ll_gpio.h"
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#include "stm32h7xx_ll_dma.h"
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#include "stm32h7xx_ll_rcc.h"
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#include "stm32h7xx_ll_bus.h"
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#include "stm32h7xx_ll_tim.h"
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#include "stm32h7xx_ll_system.h"
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#include "stm32h7xx_ll_ex.h"
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// Chip Unique ID on H7
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#define U_ID_0 (*(uint32_t*)UID_BASE)
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#define U_ID_1 (*(uint32_t*)(UID_BASE + 4))
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#define U_ID_2 (*(uint32_t*)(UID_BASE + 8))
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#define USE_PIN_AF
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#ifndef STM32H7
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#define STM32H7
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#endif
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#elif defined(STM32F722xx) || defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F765xx)
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#include "stm32f7xx.h"
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#include "stm32f7xx_hal.h"
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#include "system_stm32f7xx.h"
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#include "stm32f7xx_ll_spi.h"
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#include "stm32f7xx_ll_gpio.h"
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#include "stm32f7xx_ll_dma.h"
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#include "stm32f7xx_ll_rcc.h"
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#include "stm32f7xx_ll_bus.h"
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#include "stm32f7xx_ll_tim.h"
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#include "stm32f7xx_ll_system.h"
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#include "stm32f7xx_ll_ex.h"
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// Chip Unique ID on F7
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#define U_ID_0 (*(uint32_t*)UID_BASE)
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#define U_ID_1 (*(uint32_t*)(UID_BASE + 4))
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#define U_ID_2 (*(uint32_t*)(UID_BASE + 8))
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#define USE_PIN_AF
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#ifndef STM32F7
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#define STM32F7
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#endif
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#elif defined(STM32F40_41xxx) || defined(STM32F411xE) || defined(STM32F446xx)
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#include "stm32f4xx.h"
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// Chip Unique ID on F405
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#define U_ID_0 (*(uint32_t*)0x1fff7a10)
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#define U_ID_1 (*(uint32_t*)0x1fff7a14)
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#define U_ID_2 (*(uint32_t*)0x1fff7a18)
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#ifndef STM32F4
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#define STM32F4
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#endif
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#endif
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#ifdef STM32F4
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#if defined(STM32F40_41xxx)
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#define USE_FAST_DATA
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#endif
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#define USE_RPM_FILTER
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#define USE_DYN_IDLE
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#define USE_DYN_NOTCH_FILTER
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#define USE_ADC_INTERNAL
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#define USE_USB_CDC_HID
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#define USE_USB_MSC
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#define USE_PERSISTENT_MSC_RTC
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#define USE_MCO
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#define USE_DMA_SPEC
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#define USE_PERSISTENT_OBJECTS
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#define USE_LATE_TASK_STATISTICS
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#if defined(STM32F40_41xxx) || defined(STM32F411xE)
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#define USE_OVERCLOCK
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#endif
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#endif // STM32F4
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#ifdef STM32F7
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#define USE_ITCM_RAM
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#define ITCM_RAM_OPTIMISATION "-O2", "-freorder-blocks-algorithm=simple"
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#define USE_FAST_DATA
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#define USE_RPM_FILTER
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#define USE_DYN_IDLE
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#define USE_DYN_NOTCH_FILTER
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#define USE_OVERCLOCK
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#define USE_ADC_INTERNAL
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#define USE_USB_CDC_HID
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#define USE_USB_MSC
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#define USE_PERSISTENT_MSC_RTC
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#define USE_MCO
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#define USE_DMA_SPEC
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#define USE_PERSISTENT_OBJECTS
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#define USE_LATE_TASK_STATISTICS
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#endif // STM32F7
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#ifdef STM32H7
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#ifdef USE_DSHOT
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#define USE_DSHOT_CACHE_MGMT
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#endif
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#define USE_ITCM_RAM
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#define USE_FAST_DATA
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#define USE_RPM_FILTER
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#define USE_DYN_IDLE
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#define USE_DYN_NOTCH_FILTER
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#define USE_ADC_INTERNAL
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#define USE_USB_CDC_HID
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#define USE_DMA_SPEC
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#define USE_PERSISTENT_OBJECTS
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#define USE_DMA_RAM
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#define USE_USB_MSC
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#define USE_RTC_TIME
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#define USE_PERSISTENT_MSC_RTC
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#define USE_LATE_TASK_STATISTICS
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#endif
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#ifdef STM32G4
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#define USE_RPM_FILTER
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#define USE_DYN_IDLE
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#define USE_OVERCLOCK
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#define USE_DYN_NOTCH_FILTER
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#define USE_ADC_INTERNAL
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#define USE_USB_MSC
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#define USE_USB_CDC_HID
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#define USE_MCO
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#define USE_DMA_SPEC
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#define USE_LATE_TASK_STATISTICS
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#endif
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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#define TASK_GYROPID_DESIRED_PERIOD 125 // 125us = 8kHz
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#define SCHEDULER_DELAY_LIMIT 10
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#else
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#define TASK_GYROPID_DESIRED_PERIOD 1000 // 1000us = 1kHz
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#define SCHEDULER_DELAY_LIMIT 100
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#endif
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// Set the default cpu_overclock to the first level (108MHz) for F411
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// Helps with looptime stability as the CPU is borderline when running native gyro sampling
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#if defined(USE_OVERCLOCK) && defined(STM32F411xE)
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#define DEFAULT_CPU_OVERCLOCK 1
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#else
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#define DEFAULT_CPU_OVERCLOCK 0
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#endif
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#if defined(STM32H7)
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// Move ISRs to fast ram to avoid flash latency.
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#define FAST_IRQ_HANDLER FAST_CODE
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#else
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#define FAST_IRQ_HANDLER
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#endif
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#if defined(STM32F4) || defined(STM32G4)
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// F4 can't DMA to/from CCM (core coupled memory) SRAM (where the stack lives)
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// On G4 there is no specific DMA target memory
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#define DMA_DATA_ZERO_INIT
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#define DMA_DATA
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#define STATIC_DMA_DATA_AUTO static
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#elif defined(STM32F7)
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// F7 has no cache coherency issues DMAing to/from DTCM, otherwise buffers must be cache aligned
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#define DMA_DATA_ZERO_INIT FAST_DATA_ZERO_INIT
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#define DMA_DATA FAST_DATA
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#define STATIC_DMA_DATA_AUTO static DMA_DATA
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#else
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// DMA to/from any memory
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#define DMA_DATA_ZERO_INIT __attribute__ ((section(".dmaram_bss"), aligned(32)))
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#define DMA_DATA __attribute__ ((section(".dmaram_data"), aligned(32)))
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#define STATIC_DMA_DATA_AUTO static DMA_DATA
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#endif
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#if defined(STM32F4) || defined(STM32H7)
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// Data in RAM which is guaranteed to not be reset on hot reboot
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#define PERSISTENT __attribute__ ((section(".persistent_data"), aligned(4)))
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#endif
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#ifdef USE_DMA_RAM
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#if defined(STM32H7)
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#define DMA_RAM __attribute__((section(".DMA_RAM"), aligned(32)))
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#define DMA_RW_AXI __attribute__((section(".DMA_RW_AXI"), aligned(32)))
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extern uint8_t _dmaram_start__;
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extern uint8_t _dmaram_end__;
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#elif defined(STM32G4)
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#define DMA_RAM_R __attribute__((section(".DMA_RAM_R")))
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#define DMA_RAM_W __attribute__((section(".DMA_RAM_W")))
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#define DMA_RAM_RW __attribute__((section(".DMA_RAM_RW")))
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#endif
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#else
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#define DMA_RAM
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#define DMA_RW_AXI
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#define DMA_RAM_R
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#define DMA_RAM_W
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#define DMA_RAM_RW
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#endif
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#define USE_TIMER_MGMT
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#define USE_TIMER_AF
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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// speed is packed between modebits 4 and 1,
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// 7 6 5 4 3 2 1 0
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// 0 <pupd-1> <pupd-0> <mode-4> <speed-1> <speed-0> <mode-1> <mode-0>
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// mode-4 is equivalent to STM32F4 otype (pushpull/od)
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#define IO_CONFIG(mode, speed, pupd) ((mode) | ((speed) << 2) | ((pupd) << 5))
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#define IOCFG_OUT_PP IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_LOW, GPIO_NOPULL)
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#define IOCFG_OUT_PP_UP IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_LOW, GPIO_PULLUP)
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#define IOCFG_OUT_PP_25 IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_HIGH, GPIO_NOPULL)
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#define IOCFG_OUT_OD IO_CONFIG(GPIO_MODE_OUTPUT_OD, GPIO_SPEED_FREQ_LOW, GPIO_NOPULL)
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#define IOCFG_AF_PP IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_LOW, GPIO_NOPULL)
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#define IOCFG_AF_PP_PD IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_LOW, GPIO_PULLDOWN)
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#define IOCFG_AF_PP_UP IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_LOW, GPIO_PULLUP)
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#define IOCFG_AF_OD IO_CONFIG(GPIO_MODE_AF_OD, GPIO_SPEED_FREQ_LOW, GPIO_NOPULL)
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#define IOCFG_IPD IO_CONFIG(GPIO_MODE_INPUT, GPIO_SPEED_FREQ_LOW, GPIO_PULLDOWN)
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#define IOCFG_IPU IO_CONFIG(GPIO_MODE_INPUT, GPIO_SPEED_FREQ_LOW, GPIO_PULLUP)
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#define IOCFG_IN_FLOATING IO_CONFIG(GPIO_MODE_INPUT, GPIO_SPEED_FREQ_LOW, GPIO_NOPULL)
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#define IOCFG_IPU_25 IO_CONFIG(GPIO_MODE_INPUT, GPIO_SPEED_FREQ_HIGH, GPIO_PULLUP)
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#elif defined(STM32F4)
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#define IO_CONFIG(mode, speed, otype, pupd) ((mode) | ((speed) << 2) | ((otype) << 4) | ((pupd) << 5))
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#define IOCFG_OUT_PP IO_CONFIG(GPIO_Mode_OUT, 0, GPIO_OType_PP, GPIO_PuPd_NOPULL) // TODO
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#define IOCFG_OUT_PP_UP IO_CONFIG(GPIO_Mode_OUT, 0, GPIO_OType_PP, GPIO_PuPd_UP)
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#define IOCFG_OUT_PP_25 IO_CONFIG(GPIO_Mode_OUT, GPIO_Speed_25MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL)
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#define IOCFG_OUT_OD IO_CONFIG(GPIO_Mode_OUT, 0, GPIO_OType_OD, GPIO_PuPd_NOPULL)
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#define IOCFG_AF_PP IO_CONFIG(GPIO_Mode_AF, 0, GPIO_OType_PP, GPIO_PuPd_NOPULL)
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#define IOCFG_AF_PP_PD IO_CONFIG(GPIO_Mode_AF, 0, GPIO_OType_PP, GPIO_PuPd_DOWN)
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#define IOCFG_AF_PP_UP IO_CONFIG(GPIO_Mode_AF, 0, GPIO_OType_PP, GPIO_PuPd_UP)
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#define IOCFG_AF_OD IO_CONFIG(GPIO_Mode_AF, 0, GPIO_OType_OD, GPIO_PuPd_NOPULL)
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#define IOCFG_IPD IO_CONFIG(GPIO_Mode_IN, 0, 0, GPIO_PuPd_DOWN)
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#define IOCFG_IPU IO_CONFIG(GPIO_Mode_IN, 0, 0, GPIO_PuPd_UP)
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#define IOCFG_IN_FLOATING IO_CONFIG(GPIO_Mode_IN, 0, 0, GPIO_PuPd_NOPULL)
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#define IOCFG_IPU_25 IO_CONFIG(GPIO_Mode_IN, GPIO_Speed_25MHz, 0, GPIO_PuPd_UP)
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#endif
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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#define IO_CONFIG_GET_MODE(cfg) (((cfg) >> 0) & 0x03)
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#define IO_CONFIG_GET_SPEED(cfg) (((cfg) >> 2) & 0x03)
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#define IO_CONFIG_GET_OTYPE(cfg) (((cfg) >> 4) & 0x01)
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#define IO_CONFIG_GET_PULL(cfg) (((cfg) >> 5) & 0x03)
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#endif
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#if defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H723xx) || defined(STM32H725xx)
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#define FLASH_CONFIG_STREAMER_BUFFER_SIZE 32 // Flash word = 256-bits (8 rows, uint32_t per row - 8 x 32)
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#define FLASH_CONFIG_BUFFER_TYPE uint32_t
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#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
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#define FLASH_CONFIG_STREAMER_BUFFER_SIZE 16 // Flash word = 128-bits (4 rows, uint32_t per row - 4 x 32)
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#define FLASH_CONFIG_BUFFER_TYPE uint32_t
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#elif defined(STM32G4)
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#define FLASH_CONFIG_BUFFER_TYPE uint64_t
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#else
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#define FLASH_CONFIG_BUFFER_TYPE uint32_t
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#endif
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#if defined(STM32F4)
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#define SPI_IO_AF_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL)
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#define SPI_IO_AF_SCK_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_DOWN)
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#define SPI_IO_AF_SDI_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_UP)
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#define SPI_IO_CS_CFG IO_CONFIG(GPIO_Mode_OUT, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL)
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#define SPI_IO_CS_HIGH_CFG IO_CONFIG(GPIO_Mode_IN, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_UP)
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#elif defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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#define SPI_IO_AF_CFG IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_NOPULL)
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#define SPI_IO_AF_SCK_CFG_HIGH IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP)
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#define SPI_IO_AF_SCK_CFG_LOW IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLDOWN)
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#define SPI_IO_AF_SDI_CFG IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP)
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#define SPI_IO_CS_CFG IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_NOPULL)
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#define SPI_IO_CS_HIGH_CFG IO_CONFIG(GPIO_MODE_INPUT, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP)
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#else
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#error "Invalid STM MCU defined - requires SPI implementation"
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#endif
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#if defined(STM32F4)
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#define SPIDEV_COUNT 3
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#elif defined(STM32F7)
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#define SPIDEV_COUNT 4
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#elif defined(STM32H7)
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#define SPIDEV_COUNT 6
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#else
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#define SPIDEV_COUNT 4
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#endif
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// Work around different check routines in the libraries for different MCU types
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#if defined(STM32H7)
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#define CHECK_SPI_RX_DATA_AVAILABLE(instance) LL_SPI_IsActiveFlag_RXWNE(instance)
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#define SPI_RX_DATA_REGISTER(base) ((base)->RXDR)
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#else
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#define CHECK_SPI_RX_DATA_AVAILABLE(instance) LL_SPI_IsActiveFlag_RXNE(instance)
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#define SPI_RX_DATA_REGISTER(base) ((base)->DR)
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#endif
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#if defined(STM32F4) || defined(STM32G4)
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#define MAX_SPI_PIN_SEL 2
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#elif defined(STM32F7)
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#define MAX_SPI_PIN_SEL 4
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#elif defined(STM32H7)
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#define MAX_SPI_PIN_SEL 5
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#else
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#error Unknown MCU family
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#endif
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#if defined(STM32F4) || defined(STM32F7)
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#define USE_TX_IRQ_HANDLER
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#endif
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#if defined(STM32H7)
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#define UART_TX_BUFFER_ATTRIBUTE DMA_RAM /* D2 SRAM */
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#define UART_RX_BUFFER_ATTRIBUTE DMA_RAM /* D2 SRAM */
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#elif defined(STM32G4)
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#define UART_TX_BUFFER_ATTRIBUTE DMA_RAM_W /* SRAM MPU NOT_BUFFERABLE */
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#define UART_RX_BUFFER_ATTRIBUTE DMA_RAM_R /* SRAM MPU NOT CACHABLE */
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#elif defined(STM32F7)
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#define UART_TX_BUFFER_ATTRIBUTE FAST_DATA_ZERO_INIT /* DTCM RAM */
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#define UART_RX_BUFFER_ATTRIBUTE FAST_DATA_ZERO_INIT /* DTCM RAM */
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#elif defined(STM32F4)
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#define UART_TX_BUFFER_ATTRIBUTE /* EMPTY */
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#define UART_RX_BUFFER_ATTRIBUTE /* EMPTY */
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#endif
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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// pin AF mode is configured for each pin individually
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#define UART_TRAIT_AF_PIN 1
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#elif defined(STM32F4)
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// all pins on given uart use same AF
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#define UART_TRAIT_AF_PORT 1
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#else
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#error Unknown STM MCU when defining UART_TRAIT_x
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#endif
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#define PLATFORM_TRAIT_RCC 1
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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#define UART_TRAIT_PINSWAP 1
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#endif
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#if defined(STM32F4)
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#define UARTHARDWARE_MAX_PINS 4
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#elif defined(STM32F7)
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#define UARTHARDWARE_MAX_PINS 4
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#elif defined(STM32H7)
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#define UARTHARDWARE_MAX_PINS 6
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#elif defined(STM32G4)
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#define UARTHARDWARE_MAX_PINS 3
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#endif
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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#define UART_REG_RXD(base) ((base)->RDR)
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#define UART_REG_TXD(base) ((base)->TDR)
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#elif defined(STM32F4)
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#define UART_REG_RXD(base) ((base)->DR)
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#define UART_REG_TXD(base) ((base)->DR)
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#endif
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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#define DMA_TRAIT_CHANNEL 1
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#endif
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#define SERIAL_TRAIT_PIN_CONFIG 1
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#define USB_DP_PIN PA12
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