mirror of
https://github.com/betaflight/betaflight.git
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213 lines
6.2 KiB
C
213 lines
6.2 KiB
C
/*
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* This file is part of Cleanflight.
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*
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* Cleanflight is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Cleanflight is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "platform.h"
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#include "drivers/accgyro/accgyro_mpu.h"
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#include "drivers/exti.h"
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#include "drivers/nvic.h"
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#include "drivers/system.h"
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#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
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void SystemClock_Config(void);
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void systemReset(void)
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{
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if (mpuResetFn) {
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mpuResetFn();
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}
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__disable_irq();
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NVIC_SystemReset();
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}
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void systemResetToBootloader(void)
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{
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if (mpuResetFn) {
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mpuResetFn();
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}
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(*(__IO uint32_t *) (BKPSRAM_BASE + 4)) = 0xDEADBEEF; // flag that will be readable after reboot
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__disable_irq();
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NVIC_SystemReset();
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}
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void enableGPIOPowerUsageAndNoiseReductions(void)
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{
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// AHB1
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__HAL_RCC_BKPSRAM_CLK_ENABLE();
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__HAL_RCC_DTCMRAMEN_CLK_ENABLE();
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__HAL_RCC_DMA2_CLK_ENABLE();
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__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
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__HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_GPIOF_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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__HAL_RCC_GPIOH_CLK_ENABLE();
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__HAL_RCC_GPIOI_CLK_ENABLE();
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#ifndef STM32F722xx
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__HAL_RCC_DMA2D_CLK_ENABLE();
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__HAL_RCC_GPIOJ_CLK_ENABLE();
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__HAL_RCC_GPIOK_CLK_ENABLE();
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#endif
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//APB1
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__HAL_RCC_TIM2_CLK_ENABLE();
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__HAL_RCC_TIM3_CLK_ENABLE();
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__HAL_RCC_TIM4_CLK_ENABLE();
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__HAL_RCC_TIM5_CLK_ENABLE();
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__HAL_RCC_TIM6_CLK_ENABLE();
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__HAL_RCC_TIM7_CLK_ENABLE();
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__HAL_RCC_TIM12_CLK_ENABLE();
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__HAL_RCC_TIM13_CLK_ENABLE();
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__HAL_RCC_TIM14_CLK_ENABLE();
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__HAL_RCC_LPTIM1_CLK_ENABLE();
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__HAL_RCC_SPI2_CLK_ENABLE();
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__HAL_RCC_SPI3_CLK_ENABLE();
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__HAL_RCC_USART2_CLK_ENABLE();
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__HAL_RCC_USART3_CLK_ENABLE();
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__HAL_RCC_UART4_CLK_ENABLE();
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__HAL_RCC_UART5_CLK_ENABLE();
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__HAL_RCC_I2C1_CLK_ENABLE();
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__HAL_RCC_I2C2_CLK_ENABLE();
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__HAL_RCC_I2C3_CLK_ENABLE();
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__HAL_RCC_CAN1_CLK_ENABLE();
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__HAL_RCC_DAC_CLK_ENABLE();
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__HAL_RCC_UART7_CLK_ENABLE();
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__HAL_RCC_UART8_CLK_ENABLE();
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#ifndef STM32F722xx
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__HAL_RCC_I2C4_CLK_ENABLE();
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__HAL_RCC_CAN2_CLK_ENABLE();
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__HAL_RCC_CEC_CLK_ENABLE();
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#endif
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//APB2
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__HAL_RCC_TIM1_CLK_ENABLE();
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__HAL_RCC_TIM8_CLK_ENABLE();
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__HAL_RCC_USART1_CLK_ENABLE();
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__HAL_RCC_USART6_CLK_ENABLE();
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__HAL_RCC_ADC1_CLK_ENABLE();
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__HAL_RCC_ADC2_CLK_ENABLE();
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__HAL_RCC_ADC3_CLK_ENABLE();
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__HAL_RCC_SDMMC1_CLK_ENABLE();
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__HAL_RCC_SPI1_CLK_ENABLE();
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__HAL_RCC_SPI4_CLK_ENABLE();
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__HAL_RCC_TIM9_CLK_ENABLE();
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__HAL_RCC_TIM10_CLK_ENABLE();
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__HAL_RCC_TIM11_CLK_ENABLE();
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__HAL_RCC_SPI5_CLK_ENABLE();
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__HAL_RCC_SAI1_CLK_ENABLE();
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__HAL_RCC_SAI2_CLK_ENABLE();
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#ifndef STM32F722xx
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__HAL_RCC_SPI6_CLK_ENABLE();
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#endif
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//
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// GPIO_InitTypeDef GPIO_InitStructure;
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// GPIO_StructInit(&GPIO_InitStructure);
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// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; // default is un-pulled input
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
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// GPIO_InitStructure.GPIO_Pin &= ~(GPIO_Pin_11 | GPIO_Pin_12); // leave USB D+/D- alone
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//
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// GPIO_InitStructure.GPIO_Pin &= ~(GPIO_Pin_13 | GPIO_Pin_14); // leave JTAG pins alone
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// GPIO_Init(GPIOA, &GPIO_InitStructure);
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
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// GPIO_Init(GPIOB, &GPIO_InitStructure);
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
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// GPIO_Init(GPIOC, &GPIO_InitStructure);
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// GPIO_Init(GPIOD, &GPIO_InitStructure);
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// GPIO_Init(GPIOE, &GPIO_InitStructure);
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}
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bool isMPUSoftReset(void)
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{
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if (cachedRccCsrValue & RCC_CSR_SFTRSTF)
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return true;
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else
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return false;
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}
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void systemInit(void)
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{
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checkForBootLoaderRequest();
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//SystemClock_Config();
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// Configure NVIC preempt/priority groups
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HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUPING);
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// cache RCC->CSR value to use it in isMPUSoftReset() and others
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cachedRccCsrValue = RCC->CSR;
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/* Accounts for OP Bootloader, set the Vector Table base address as specified in .ld file */
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//extern void *isr_vector_table_base;
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//NVIC_SetVectorTable((uint32_t)&isr_vector_table_base, 0x0);
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//__HAL_RCC_USB_OTG_FS_CLK_DISABLE;
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//RCC_ClearFlag();
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enableGPIOPowerUsageAndNoiseReductions();
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// Init cycle counter
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cycleCounterInit();
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// SysTick
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//SysTick_Config(SystemCoreClock / 1000);
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HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
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HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
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}
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void(*bootJump)(void);
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void checkForBootLoaderRequest(void)
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{
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uint32_t bt;
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__PWR_CLK_ENABLE();
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__BKPSRAM_CLK_ENABLE();
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HAL_PWR_EnableBkUpAccess();
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bt = (*(__IO uint32_t *) (BKPSRAM_BASE + 4)) ;
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if ( bt == 0xDEADBEEF ) {
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(*(__IO uint32_t *) (BKPSRAM_BASE + 4)) = 0xCAFEFEED; // Reset our trigger
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// Backup SRAM is write-back by default, ensure value actually reaches memory
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// Another solution would be marking BKPSRAM as write-through in Memory Protection Unit settings
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SCB_CleanDCache_by_Addr((uint32_t *) (BKPSRAM_BASE + 4), sizeof(uint32_t));
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void (*SysMemBootJump)(void);
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__SYSCFG_CLK_ENABLE();
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SYSCFG->MEMRMP |= SYSCFG_MEM_BOOT_ADD0 ;
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uint32_t p = (*((uint32_t *) 0x1ff00000));
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__set_MSP(p); //Set the main stack pointer to its defualt values
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SysMemBootJump = (void (*)(void)) (*((uint32_t *) 0x1ff00004)); // Point the PC to the System Memory reset vector (+4)
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SysMemBootJump();
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while (1);
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}
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}
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