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https://github.com/betaflight/betaflight.git
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259 lines
11 KiB
C
259 lines
11 KiB
C
/*
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <inttypes.h>
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#include "pico.h"
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#include "hardware/gpio.h"
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#include "hardware/powman.h"
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#ifndef PICO_POWMAN_DEBUG
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#define PICO_POWMAN_DEBUG 0
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#endif
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#if PICO_POWMAN_DEBUG
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bool powman_debug_printf = false;
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void powman_enable_debug_printf(void) {
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powman_debug_printf = true;
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}
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#define powman_debug(format, args...) if (powman_debug_printf) printf(format, ## args)
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#else
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#define powman_debug(...)
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#endif
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static inline void powman_write(volatile uint32_t *reg, uint32_t value) {
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// Write needs a password in top 16 bits
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invalid_params_if(HARDWARE_POWMAN, value >> 16);
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*reg = POWMAN_PASSWORD_BITS | value;
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}
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void powman_timer_set_ms(uint64_t time_ms) {
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bool was_running = powman_timer_is_running();
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if (was_running) powman_timer_stop();
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powman_write(&powman_hw->set_time_15to0, time_ms & 0xffff);
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powman_write(&powman_hw->set_time_31to16, (time_ms >> 16) & 0xffff);
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powman_write(&powman_hw->set_time_47to32, (time_ms >> 32) & 0xffff);
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powman_write(&powman_hw->set_time_63to48, (time_ms >> 48) & 0xffff);
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if (was_running) powman_timer_start();
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}
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uint64_t powman_timer_get_ms(void) {
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// Need to make sure that the upper 32 bits of the timer
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// don't change, so read that first
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uint32_t hi = powman_hw->read_time_upper;
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uint32_t lo;
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do {
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// Read the lower 32 bits
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lo = powman_hw->read_time_lower;
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// Now read the upper 32 bits again and
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// check that it hasn't incremented. If it has loop around
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// and read the lower 32 bits again to get an accurate value
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uint32_t next_hi = powman_hw->read_time_upper;
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if (hi == next_hi) break;
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hi = next_hi;
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} while (true);
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return ((uint64_t) hi << 32u) | lo;
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}
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void powman_timer_set_1khz_tick_source_lposc(void) {
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powman_timer_set_1khz_tick_source_lposc_with_hz(32768);
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}
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void powman_timer_set_1khz_tick_source_lposc_with_hz(uint32_t lposc_freq_hz) {
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bool was_running = powman_timer_is_running();
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if (was_running) powman_timer_stop();
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uint32_t lposc_freq_khz = lposc_freq_hz / 1000;
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uint32_t lposc_freq_khz_frac16 = (lposc_freq_khz % 1000) * 65536 / 1000;
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powman_write(&powman_hw->lposc_freq_khz_int, lposc_freq_khz);
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powman_write(&powman_hw->lposc_freq_khz_frac, lposc_freq_khz_frac16);
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powman_set_bits(&powman_hw->timer, POWMAN_TIMER_USE_LPOSC_BITS);
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if (was_running) {
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powman_timer_start();
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while(!(powman_hw->timer & POWMAN_TIMER_USING_LPOSC_BITS));
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}
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}
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void powman_timer_set_1khz_tick_source_xosc(void) {
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powman_timer_set_1khz_tick_source_xosc_with_hz(XOSC_HZ);
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}
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void powman_timer_set_1khz_tick_source_xosc_with_hz(uint32_t xosc_freq_hz) {
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bool was_running = powman_timer_is_running();
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if (was_running) powman_timer_stop();
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uint32_t xosc_freq_khz = xosc_freq_hz / 1000;
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uint32_t xosc_freq_khz_frac16 = (xosc_freq_khz % 1000) * 65536 / 1000;
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powman_write(&powman_hw->xosc_freq_khz_int, xosc_freq_khz);
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powman_write(&powman_hw->xosc_freq_khz_frac, xosc_freq_khz_frac16);
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powman_set_bits(&powman_hw->timer, POWMAN_TIMER_USE_XOSC_BITS);
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if (was_running) {
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powman_timer_start();
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while(!(powman_hw->timer & POWMAN_TIMER_USING_XOSC_BITS));
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}
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}
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static void powman_timer_use_gpio(uint32_t gpio, uint32_t use, uint32_t using) {
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bool was_running = powman_timer_is_running();
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if (was_running) powman_timer_stop();
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invalid_params_if(HARDWARE_POWMAN, !((gpio == 12) || (gpio == 14) || (gpio == 20) || (gpio == 22)));
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gpio_set_input_enabled(gpio, true);
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powman_write(&powman_hw->ext_time_ref, gpio);
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powman_set_bits(&powman_hw->timer, use);
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if (was_running) {
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powman_timer_start();
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while(!(powman_hw->timer & using));
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}
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}
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void powman_timer_set_1khz_tick_source_gpio(uint32_t gpio) {
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// todo check if we're using the GPIO setup already?
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powman_timer_use_gpio(gpio, POWMAN_TIMER_USE_GPIO_1KHZ_BITS, POWMAN_TIMER_USING_GPIO_1KHZ_BITS);
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}
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void powman_timer_enable_gpio_1hz_sync(uint32_t gpio) {
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// todo check if we're using the GPIO setup already?
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powman_timer_use_gpio(gpio, POWMAN_TIMER_USE_GPIO_1HZ_BITS, POWMAN_TIMER_USING_GPIO_1HZ_BITS);
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}
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void powman_timer_disable_gpio_1hz_sync(void) {
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powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_USE_GPIO_1HZ_BITS);
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}
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powman_power_state powman_get_power_state(void) {
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uint32_t state_reg = powman_hw->state & POWMAN_STATE_CURRENT_BITS;
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// todo we should have hardware/regs/powman.h values for these
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static_assert(POWMAN_POWER_DOMAIN_SRAM_BANK1 == 0, "");
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static_assert(POWMAN_POWER_DOMAIN_SRAM_BANK0 == 1, "");
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static_assert(POWMAN_POWER_DOMAIN_XIP_CACHE == 2, "");
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static_assert(POWMAN_POWER_DOMAIN_SWITCHED_CORE == 3, "");
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static_assert(POWMAN_STATE_CURRENT_BITS == 0xf, "");
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return (powman_power_state) state_reg;
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}
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// TODO: Should this fail to go to sleep if there is no wakeup alarm
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int powman_set_power_state(powman_power_state state) {
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// Clear req ignored in case it has been set
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powman_clear_bits(&powman_hw->state, POWMAN_STATE_REQ_IGNORED_BITS);
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powman_debug("powman: Requesting state %x\n", state);
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powman_write(&powman_hw->state, (~state << POWMAN_STATE_REQ_LSB) & POWMAN_STATE_REQ_BITS);
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// Has it been ignored?
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if (powman_hw->state & POWMAN_STATE_REQ_IGNORED_BITS) {
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powman_debug("State req ignored because of a pending pwrup req: %"PRIx32"\n", powman_hw->current_pwrup_req);
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return PICO_ERROR_PRECONDITION_NOT_MET;
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}
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bool state_valid = (powman_hw->state & POWMAN_STATE_BAD_SW_REQ_BITS) == 0;
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if (!state_valid) {
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powman_debug("powman: Requested state invalid\n");
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return PICO_ERROR_INVALID_ARG;
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} else {
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powman_debug("powman: Requested state valid\n");
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}
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if (!powman_power_state_is_domain_on(state, POWMAN_POWER_DOMAIN_SWITCHED_CORE)) {
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// If we are turning off switched core then POWMAN_STATE_WAITING_BITS will be
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// set because we are waiting for proc to go to sleep, so return ok and then the proc
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// can go to sleep
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// Note if the powerdown is being blocked by a pending pwrup request we will break out of this and return a failure
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// Clk pow is slow so can take a few clk_pow cycles for waiting to turn up
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for (int i = 0; i < 100; i++) {
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if (powman_hw->state & POWMAN_STATE_WAITING_BITS) {
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return PICO_OK;
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}
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}
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// If it hasn't turned up then false
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powman_debug("powman: STATE_WAITING hasn't turned up\n");
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return PICO_ERROR_TIMEOUT;
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}
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// Wait while the state is changing then return true as we will be in the new state
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powman_debug("powman: waiting for state change\n");
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while(powman_hw->state & POWMAN_STATE_CHANGING_BITS) tight_loop_contents();
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powman_debug("powman: state changed to %x\n", state);
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return PICO_OK;
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}
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bool powman_configure_wakeup_state(powman_power_state sleep_state, powman_power_state wakeup_state) {
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// When powman wakes up it can keep the state of the sram0 and sram1 banks. Note, it can't
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// explicitly
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bool valid = powman_power_state_is_domain_on(wakeup_state, POWMAN_POWER_DOMAIN_XIP_CACHE);
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valid &= powman_power_state_is_domain_on(wakeup_state, POWMAN_POWER_DOMAIN_SWITCHED_CORE);
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valid &= powman_power_state_is_domain_on(sleep_state, POWMAN_POWER_DOMAIN_SRAM_BANK0) ==
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powman_power_state_is_domain_on(wakeup_state, POWMAN_POWER_DOMAIN_SRAM_BANK0);
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valid &= powman_power_state_is_domain_on(sleep_state, POWMAN_POWER_DOMAIN_SRAM_BANK1) ==
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powman_power_state_is_domain_on(wakeup_state, POWMAN_POWER_DOMAIN_SRAM_BANK1);
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if (valid) {
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powman_clear_bits(&powman_hw->seq_cfg, POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_BITS | POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_BITS);
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uint32_t seq_cfg_set = 0;
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if (!powman_power_state_is_domain_on(sleep_state, POWMAN_POWER_DOMAIN_SRAM_BANK0)) seq_cfg_set |= POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_BITS;
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if (!powman_power_state_is_domain_on(sleep_state, POWMAN_POWER_DOMAIN_SRAM_BANK1)) seq_cfg_set |= POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_BITS;
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powman_set_bits(&powman_hw->seq_cfg, seq_cfg_set);
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}
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return valid;
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}
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void powman_timer_enable_alarm_at_ms(uint64_t alarm_time_ms) {
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powman_set_bits(&powman_hw->inte, POWMAN_INTE_TIMER_BITS);
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powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_ALARM_ENAB_BITS);
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// Alarm must be disabled to set the alarm time
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powman_write(&powman_hw->alarm_time_15to0, alarm_time_ms & 0xffff);
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powman_write(&powman_hw->alarm_time_31to16, (alarm_time_ms >> 16) & 0xffff);
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powman_write(&powman_hw->alarm_time_47to32, (alarm_time_ms >> 32) & 0xffff);
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powman_write(&powman_hw->alarm_time_63to48, (alarm_time_ms >> 48) & 0xffff);
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powman_clear_alarm();
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// TODO: Assuming pwrup on alarm has no bad side effects if already powered up
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powman_set_bits(&powman_hw->timer, POWMAN_TIMER_ALARM_ENAB_BITS);
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}
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void powman_timer_disable_alarm(void) {
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powman_clear_bits(&powman_hw->inte, POWMAN_INTE_TIMER_BITS);
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powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_ALARM_ENAB_BITS);
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}
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void powman_enable_alarm_wakeup_at_ms(uint64_t alarm_time_ms) {
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powman_timer_enable_alarm_at_ms(alarm_time_ms);
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powman_set_bits(&powman_hw->timer, POWMAN_TIMER_PWRUP_ON_ALARM_BITS);
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}
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void powman_disable_alarm_wakeup(void) {
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powman_timer_disable_alarm();
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powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_PWRUP_ON_ALARM_BITS);
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}
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void powman_enable_gpio_wakeup(uint gpio_wakeup_num, uint32_t gpio, bool edge, bool high) {
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invalid_params_if(HARDWARE_POWMAN, gpio_wakeup_num >= count_of(powman_hw->pwrup));
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// Need to make sure pad is input enabled
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gpio_set_input_enabled(gpio, true);
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// Set up gpio hardware for what we want
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uint32_t pwrup = (edge ? POWMAN_PWRUP0_MODE_VALUE_EDGE : POWMAN_PWRUP0_MODE_VALUE_LEVEL) << POWMAN_PWRUP0_MODE_LSB;
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pwrup |= (high ? POWMAN_PWRUP0_DIRECTION_BITS : 0);
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pwrup |= gpio << POWMAN_PWRUP0_SOURCE_LSB;
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powman_write(&powman_hw->pwrup[gpio_wakeup_num], pwrup);
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// Clear the status bit in case an edge is already latched
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powman_clear_bits(&powman_hw->pwrup[gpio_wakeup_num], POWMAN_PWRUP0_STATUS_BITS);
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// Important to enable it separately to allow the gpio to change
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powman_set_bits(&powman_hw->pwrup[gpio_wakeup_num], POWMAN_PWRUP0_ENABLE_BITS);
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}
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void powman_disable_gpio_wakeup(uint gpio_wakeup_num) {
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invalid_params_if(HARDWARE_POWMAN, gpio_wakeup_num >= count_of(powman_hw->pwrup));
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powman_clear_bits(&powman_hw->pwrup[gpio_wakeup_num], POWMAN_PWRUP0_ENABLE_BITS);
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}
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void powman_disable_all_wakeups(void) {
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for (uint i = 0; i < count_of(powman_hw->pwrup); i++) {
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powman_disable_gpio_wakeup(i);
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}
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powman_disable_alarm_wakeup();
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}
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