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142 lines
5.3 KiB
C
142 lines
5.3 KiB
C
/*
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modified version of StdPeriph function is located here.
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TODO - what license does apply here?
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original file was lincesed under MCD-ST Liberty SW License Agreement V2
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http://www.st.com/software_license_agreement_liberty_v2
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include "platform.h"
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#include "common/utils.h"
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#include "stm32f4xx.h"
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#include "rcc.h"
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#include "timer.h"
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/**
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* @brief Selects the TIM Output Compare Mode.
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* @note This function does NOT disable the selected channel before changing the Output
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* Compare Mode.
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* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
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* @param TIM_Channel: specifies the TIM Channel
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* This parameter can be one of the following values:
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* @arg TIM_Channel_1: TIM Channel 1
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* @arg TIM_Channel_2: TIM Channel 2
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* @arg TIM_Channel_3: TIM Channel 3
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* @arg TIM_Channel_4: TIM Channel 4
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* @param TIM_OCMode: specifies the TIM Output Compare Mode.
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* This parameter can be one of the following values:
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* @arg TIM_OCMode_Timing
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* @arg TIM_OCMode_Active
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* @arg TIM_OCMode_Toggle
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* @arg TIM_OCMode_PWM1
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* @arg TIM_OCMode_PWM2
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* @arg TIM_ForcedAction_Active
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* @arg TIM_ForcedAction_InActive
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* @retval None
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*/
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#define CCMR_Offset ((uint16_t)0x0018)
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const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
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{ .TIMx = TIM1, .rcc = RCC_APB2(TIM1), .inputIrq = TIM1_CC_IRQn},
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{ .TIMx = TIM2, .rcc = RCC_APB1(TIM2), .inputIrq = TIM2_IRQn},
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{ .TIMx = TIM3, .rcc = RCC_APB1(TIM3), .inputIrq = TIM3_IRQn},
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{ .TIMx = TIM4, .rcc = RCC_APB1(TIM4), .inputIrq = TIM4_IRQn},
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{ .TIMx = TIM5, .rcc = RCC_APB1(TIM5), .inputIrq = TIM5_IRQn},
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{ .TIMx = TIM6, .rcc = RCC_APB1(TIM6), .inputIrq = 0},
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{ .TIMx = TIM7, .rcc = RCC_APB1(TIM7), .inputIrq = 0},
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#ifndef STM32F411xE
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{ .TIMx = TIM8, .rcc = RCC_APB2(TIM8), .inputIrq = TIM8_CC_IRQn},
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#endif
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{ .TIMx = TIM9, .rcc = RCC_APB2(TIM9), .inputIrq = TIM1_BRK_TIM9_IRQn},
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{ .TIMx = TIM10, .rcc = RCC_APB2(TIM10), .inputIrq = TIM1_UP_TIM10_IRQn},
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{ .TIMx = TIM11, .rcc = RCC_APB2(TIM11), .inputIrq = TIM1_TRG_COM_TIM11_IRQn},
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#ifndef STM32F411xE
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{ .TIMx = TIM12, .rcc = RCC_APB1(TIM12), .inputIrq = TIM8_BRK_TIM12_IRQn},
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{ .TIMx = TIM13, .rcc = RCC_APB1(TIM13), .inputIrq = TIM8_UP_TIM13_IRQn},
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{ .TIMx = TIM14, .rcc = RCC_APB1(TIM14), .inputIrq = TIM8_TRG_COM_TIM14_IRQn},
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#endif
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};
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/*
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need a mapping from dma and timers to pins, and the values should all be set here to the dmaMotors array.
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this mapping could be used for both these motors and for led strip.
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only certain pins have OC output (already used in normal PWM et al) but then
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there are only certain DMA streams/channels available for certain timers and channels.
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*** (this may highlight some hardware limitations on some targets) ***
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DMA1
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Channel Stream0 Stream1 Stream2 Stream3 Stream4 Stream5 Stream6 Stream7
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0
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1
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2 TIM4_CH1 TIM4_CH2 TIM4_CH3
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3 TIM2_CH3 TIM2_CH1 TIM2_CH1 TIM2_CH4
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TIM2_CH4
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4
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5 TIM3_CH4 TIM3_CH1 TIM3_CH2 TIM3_CH3
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6 TIM5_CH3 TIM5_CH4 TIM5_CH1 TIM5_CH4 TIM5_CH2
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7
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DMA2
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Channel Stream0 Stream1 Stream2 Stream3 Stream4 Stream5 Stream6 Stream7
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0 TIM8_CH1 TIM1_CH1
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TIM8_CH2 TIM1_CH2
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TIM8_CH3 TIM1_CH3
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1
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2
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3
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4
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5
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6 TIM1_CH1 TIM1_CH2 TIM1_CH1 TIM1_CH4 TIM1_CH3
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7 TIM8_CH1 TIM8_CH2 TIM8_CH3 TIM8_CH4
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*/
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uint8_t timerClockDivisor(TIM_TypeDef *tim)
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{
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#if defined (STM32F40_41xxx)
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if (tim == TIM8) return 1;
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#endif
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if (tim == TIM1 || tim == TIM9 || tim == TIM10 || tim == TIM11) {
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return 1;
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} else {
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return 2;
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}
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}
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void TIM_SelectOCxM_NoDisable(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
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{
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uint32_t tmp = 0;
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/* Check the parameters */
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assert_param(IS_TIM_LIST8_PERIPH(TIMx));
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assert_param(IS_TIM_CHANNEL(TIM_Channel));
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assert_param(IS_TIM_OCM(TIM_OCMode));
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tmp = (uint32_t) TIMx;
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tmp += CCMR_Offset;
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if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) {
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tmp += (TIM_Channel>>1);
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/* Reset the OCxM bits in the CCMRx register */
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*(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
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/* Configure the OCxM bits in the CCMRx register */
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*(__IO uint32_t *) tmp |= TIM_OCMode;
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} else {
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tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
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/* Reset the OCxM bits in the CCMRx register */
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*(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
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/* Configure the OCxM bits in the CCMRx register */
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*(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
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}
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}
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