mirror of
https://github.com/betaflight/betaflight.git
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466 lines
No EOL
17 KiB
C
466 lines
No EOL
17 KiB
C
/*
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* This file is part of Cleanflight.
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*
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* Cleanflight is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Cleanflight is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <platform.h>
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#include "common/utils.h"
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#if defined(STM32F1)
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#define DEF_TIM(tim, chan, pin, flags, out) {\
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tim,\
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IO_TAG(pin),\
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EXPAND(DEF_CHAN_ ## chan),\
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flags,\
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(DEF_CHAN_ ## chan ## _OUTPUT | out),\
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CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _CHANNEL),\
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CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _HANDLER)\
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}
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#define DEF_DMA_CHANNEL(tim, chan) CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _CHANNEL)
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#define DEF_DMA_HANDLER(tim, chan) CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _HANDLER)
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/* add the DMA mappings here for F1 */
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#define DEF_TIM_DMA__TIM1_CH1 DMA1_CH2
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#define DEF_TIM_DMA__TIM1_CH2 DMA_NONE
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#define DEF_TIM_DMA__TIM1_CH3 DMA1_CH6
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#define DEF_TIM_DMA__TIM1_CH4 DMA1_CH4
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#define DEF_TIM_DMA__TIM2_CH1 DMA1_CH5
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#define DEF_TIM_DMA__TIM2_CH2 DMA1_CH7
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#define DEF_TIM_DMA__TIM2_CH3 DMA1_CH1
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#define DEF_TIM_DMA__TIM2_CH4 DMA1_CH7
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#define DEF_TIM_DMA__TIM3_CH1 DMA1_CH6
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#define DEF_TIM_DMA__TIM3_CH2 DMA_NONE
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#define DEF_TIM_DMA__TIM3_CH3 DMA1_CH2
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#define DEF_TIM_DMA__TIM3_CH4 DMA1_CH3
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#define DEF_TIM_DMA__TIM4_CH1 DMA1_CH1
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#define DEF_TIM_DMA__TIM4_CH2 DMA1_CH4
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#define DEF_TIM_DMA__TIM4_CH3 DMA1_CH5
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#define DEF_TIM_DMA__TIM4_CH4 DMA_NONE
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#elif defined(STM32F3)
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#define DEF_TIM(tim, chan, pin, flags, out) {\
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tim,\
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IO_TAG(pin),\
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EXPAND(DEF_CHAN_ ## chan),\
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flags,\
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(DEF_CHAN_ ## chan ## _OUTPUT | out),\
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EXPAND(GPIO_AF__ ## pin ## _ ## tim ## _ ## chan),\
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CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _CHANNEL),\
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CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _HANDLER)\
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}
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#define DEF_DMA_CHANNEL(tim, chan) CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _CHANNEL)
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#define DEF_DMA_HANDLER(tim, chan) CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _HANDLER)
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/* add the DMA mappings here */
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#define DEF_TIM_DMA__TIM1_CH1 DMA1_CH2
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#define DEF_TIM_DMA__TIM1_CH2 DMA1_CH3
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#define DEF_TIM_DMA__TIM1_CH4 DMA1_CH4
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#define DEF_TIM_DMA__TIM1_CH1N DMA1_CH2
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#define DEF_TIM_DMA__TIM1_CH2N DMA1_CH3
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#define DEF_TIM_DMA__TIM1_TRIG DMA1_CH4
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#define DEF_TIM_DMA__TIM1_COM DMA1_CH4
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#define DEF_TIM_DMA__TIM1_UP DMA1_CH5
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#define DEF_TIM_DMA__TIM1_CH3 DMA1_CH6
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#define DEF_TIM_DMA__TIM2_CH3 DMA1_CH1
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#define DEF_TIM_DMA__TIM2_UP DMA1_CH2
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#define DEF_TIM_DMA__TIM2_CH1 DMA1_CH5
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#define DEF_TIM_DMA__TIM2_CH2 DMA1_CH7
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#define DEF_TIM_DMA__TIM2_CH4 DMA1_CH7
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#define DEF_TIM_DMA__TIM3_CH2 DMA_NONE
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#define DEF_TIM_DMA__TIM3_CH3 DMA1_CH2
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#define DEF_TIM_DMA__TIM3_CH4 DMA1_CH3
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#define DEF_TIM_DMA__TIM3_UP DMA1_CH3
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#define DEF_TIM_DMA__TIM3_CH1 DMA1_CH6
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#define DEF_TIM_DMA__TIM3_TRIG DMA1_CH6
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#define DEF_TIM_DMA__TIM4_CH1 DMA1_CH1
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#define DEF_TIM_DMA__TIM4_CH2 DMA1_CH4
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#define DEF_TIM_DMA__TIM4_CH3 DMA1_CH5
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#define DEF_TIM_DMA__TIM4_UP DMA1_CH7
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#define DEF_TIM_DMA__TIM4_CH4 DMA_NONE
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#define DEF_TIM_DMA__TIM15_CH1 DMA1_CH5
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#define DEF_TIM_DMA__TIM15_CH2 DMA_NONE
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#define DEF_TIM_DMA__TIM15_UP DMA1_CH5
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#define DEF_TIM_DMA__TIM15_TRIG DMA1_CH5
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#define DEF_TIM_DMA__TIM15_COM DMA1_CH5
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#define DEF_TIM_DMA__TIM15_CH1N DMA1_CH5
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#ifdef REMAP_TIM16_DMA
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#define DEF_TIM_DMA__TIM16_CH1 DMA1_CH6
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#define DEF_TIM_DMA__TIM16_UP DMA1_CH6
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#else
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#define DEF_TIM_DMA__TIM16_CH1 DMA1_CH3
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#define DEF_TIM_DMA__TIM16_UP DMA1_CH3
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#endif
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#ifdef REMAP_TIM17_DMA
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#define DEF_TIM_DMA__TIM17_CH1 DMA1_CH7
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#define DEF_TIM_DMA__TIM17_UP DMA1_CH7
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#else
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#define DEF_TIM_DMA__TIM17_CH1 DMA1_CH1
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#define DEF_TIM_DMA__TIM17_UP DMA1_CH1
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#endif
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#define DEF_TIM_DMA__TIM8_CH3 DMA2_CH1
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#define DEF_TIM_DMA__TIM8_UP DMA2_CH1
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#define DEF_TIM_DMA__TIM8_CH4 DMA2_CH2
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#define DEF_TIM_DMA__TIM8_TRIG DMA2_CH2
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#define DEF_TIM_DMA__TIM8_COM DMA2_CH2
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#define DEF_TIM_DMA__TIM8_CH1 DMA2_CH3
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#define DEF_TIM_DMA__TIM8_CH1N DMA2_CH3
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#define DEF_TIM_DMA__TIM8_CH2 DMA2_CH5
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#define DEF_TIM_DMA__TIM8_CH2N DMA2_CH5
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#define GPIO_AF(p, t) CONCAT(GPIO_AF__, p, _, t)
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#define GPIO_AF__PA0_TIM2_CH1 GPIO_AF_1
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#define GPIO_AF__PA1_TIM2_CH2 GPIO_AF_1
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#define GPIO_AF__PA2_TIM2_CH3 GPIO_AF_1
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#define GPIO_AF__PA3_TIM2_CH4 GPIO_AF_1
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#define GPIO_AF__PA5_TIM2_CH1 GPIO_AF_1
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#define GPIO_AF__PA6_TIM16_CH1 GPIO_AF_1
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#define GPIO_AF__PA7_TIM17_CH1 GPIO_AF_1
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#define GPIO_AF__PA12_TIM16_CH1 GPIO_AF_1
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#define GPIO_AF__PA13_TIM16_CH1N GPIO_AF_1
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#define GPIO_AF__PA15_TIM2_CH1 GPIO_AF_1
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#define GPIO_AF__PA4_TIM3_CH2 GPIO_AF_2
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#define GPIO_AF__PA6_TIM3_CH1 GPIO_AF_2
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#define GPIO_AF__PA7_TIM3_CH2 GPIO_AF_2
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#define GPIO_AF__PA15_TIM8_CH1 GPIO_AF_2
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#define GPIO_AF__PA7_TIM8_CH1N GPIO_AF_4
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#define GPIO_AF__PA14_TIM4_CH2 GPIO_AF_5
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#define GPIO_AF__PA7_TIM1_CH1N GPIO_AF_6
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#define GPIO_AF__PA8_TIM1_CH1 GPIO_AF_6
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#define GPIO_AF__PA9_TIM1_CH2 GPIO_AF_6
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#define GPIO_AF__PA10_TIM1_CH3 GPIO_AF_6
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#define GPIO_AF__PA11_TIM1_CH1N GPIO_AF_6
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#define GPIO_AF__PA12_TIM1_CH2N GPIO_AF_6
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#define GPIO_AF__PA1_TIM15_CH1N GPIO_AF_9
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#define GPIO_AF__PA2_TIM15_CH1 GPIO_AF_9
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#define GPIO_AF__PA3_TIM15_CH2 GPIO_AF_9
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#define GPIO_AF__PA9_TIM2_CH3 GPIO_AF_10
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#define GPIO_AF__PA10_TIM2_CH4 GPIO_AF_10
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#define GPIO_AF__PA11_TIM4_CH1 GPIO_AF_10
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#define GPIO_AF__PA12_TIM4_CH2 GPIO_AF_10
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#define GPIO_AF__PA13_TIM4_CH3 GPIO_AF_10
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#define GPIO_AF__PA11_TIM1_CH4 GPIO_AF_11
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#define GPIO_AF__PB3_TIM2_CH2 GPIO_AF_1
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#define GPIO_AF__PB4_TIM16_CH1 GPIO_AF_1
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#define GPIO_AF__PB6_TIM16_CH1N GPIO_AF_1
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#define GPIO_AF__PB7_TIM17_CH1N GPIO_AF_1
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#define GPIO_AF__PB8_TIM16_CH1 GPIO_AF_1
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#define GPIO_AF__PB9_TIM17_CH1 GPIO_AF_1
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#define GPIO_AF__PB10_TIM2_CH3 GPIO_AF_1
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#define GPIO_AF__PB11_TIM2_CH4 GPIO_AF_1
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#define GPIO_AF__PB14_TIM15_CH1 GPIO_AF_1
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#define GPIO_AF__PB15_TIM15_CH2 GPIO_AF_1
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#define GPIO_AF__PB0_TIM3_CH3 GPIO_AF_2
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#define GPIO_AF__PB1_TIM3_CH4 GPIO_AF_2
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#define GPIO_AF__PB4_TIM3_CH1 GPIO_AF_2
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#define GPIO_AF__PB5_TIM3_CH2 GPIO_AF_2
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#define GPIO_AF__PB6_TIM4_CH1 GPIO_AF_2
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#define GPIO_AF__PB7_TIM4_CH2 GPIO_AF_2
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#define GPIO_AF__PB8_TIM4_CH3 GPIO_AF_2
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#define GPIO_AF__PB9_TIM4_CH4 GPIO_AF_2
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#define GPIO_AF__PB15_TIM15_CH1N GPIO_AF_2
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#define GPIO_AF__PB0_TIM8_CH2N GPIO_AF_4
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#define GPIO_AF__PB1_TIM8_CH3N GPIO_AF_4
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#define GPIO_AF__PB3_TIM8_CH1N GPIO_AF_4
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#define GPIO_AF__PB4_TIM8_CH2N GPIO_AF_4
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#define GPIO_AF__PB15_TIM1_CH3N GPIO_AF_4
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#define GPIO_AF__PB6_TIM8_CH1 GPIO_AF_5
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#define GPIO_AF__PB0_TIM1_CH2N GPIO_AF_6
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#define GPIO_AF__PB1_TIM1_CH3N GPIO_AF_6
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#define GPIO_AF__PB13_TIM1_CH1N GPIO_AF_6
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#define GPIO_AF__PB14_TIM1_CH2N GPIO_AF_6
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#define GPIO_AF__PB5_TIM17_CH1 GPIO_AF_10
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#define GPIO_AF__PB7_TIM3_CH4 GPIO_AF_10
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#define GPIO_AF__PB8_TIM8_CH2 GPIO_AF_10
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#define GPIO_AF__PB9_TIM8_CH3 GPIO_AF_10
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#define GPIO_AF__PC6_TIM3_CH1 GPIO_AF_2
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#define GPIO_AF__PC7_TIM3_CH2 GPIO_AF_2
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#define GPIO_AF__PC8_TIM3_CH3 GPIO_AF_2
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#define GPIO_AF__PC9_TIM3_CH4 GPIO_AF_2
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#define GPIO_AF__PC6_TIM8_CH1 GPIO_AF_4
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#define GPIO_AF__PC7_TIM8_CH2 GPIO_AF_4
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#define GPIO_AF__PC8_TIM8_CH3 GPIO_AF_4
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#define GPIO_AF__PC9_TIM8_CH4 GPIO_AF_4
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#define GPIO_AF__PC10_TIM8_CH1N GPIO_AF_4
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#define GPIO_AF__PC11_TIM8_CH2N GPIO_AF_4
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#define GPIO_AF__PC12_TIM8_CH3N GPIO_AF_4
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#define GPIO_AF__PC13_TIM8_CH1N GPIO_AF_4
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#define GPIO_AF__PD3_TIM2_CH1 GPIO_AF_2
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#define GPIO_AF__PD4_TIM2_CH2 GPIO_AF_2
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#define GPIO_AF__PD6_TIM2_CH4 GPIO_AF_2
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#define GPIO_AF__PD7_TIM2_CH3 GPIO_AF_2
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#define GPIO_AF__PD12_TIM4_CH1 GPIO_AF_2
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#define GPIO_AF__PD13_TIM4_CH2 GPIO_AF_2
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#define GPIO_AF__PD14_TIM4_CH3 GPIO_AF_2
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#define GPIO_AF__PD15_TIM4_CH4 GPIO_AF_2
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#define GPIO_AF__PD1_TIM8_CH4 GPIO_AF_4
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#define GPIO_AF__PF9_TIM15_CH1 GPIO_AF_3
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#define GPIO_AF__PF10_TIM15_CH2 GPIO_AF_3
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#elif defined(STM32F4)
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#define DMA_OPT_FIRST 0
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#define DMA_OPT_SECOND 0
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#define DMA_OPT_THIRD 0
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#define DEF_TIM(tim, chan, pin, flags, out, dmaopt) {\
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tim,\
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IO_TAG(pin),\
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EXPAND(DEF_CHAN_ ## chan),\
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flags,\
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(DEF_CHAN_ ## chan ## _OUTPUT | out),\
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EXPAND(GPIO_AF_## tim),\
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CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## __ ## tim ## _ ## chan), _STREAM),\
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EXPAND(DEF_TIM_DMA_CHN_ ## dmaopt ## __ ## tim ## _ ## chan),\
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CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## __ ## tim ## _ ## chan), _HANDLER)\
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}
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#define DEF_DMA_CHANNEL(tim, chan, dmaopt) EXPAND(DEF_TIM_DMA_CHN_ ## dmaopt ## __ ## tim ## _ ## chan)
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#define DEF_DMA_STREAM(tim, chan, dmaopt) CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## __ ## tim ## _ ## chan), _STREAM)
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#define DEF_DMA_HANDLER(tim, chan, dmaopt) CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## __ ## tim ## _ ## chan), _HANDLER)
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/* F4 Stream Mappings */
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#define DEF_TIM_DMA_STR_0__TIM1_CH1 DMA2_ST6
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#define DEF_TIM_DMA_STR_1__TIM1_CH1 DMA2_ST1
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#define DEF_TIM_DMA_STR_2__TIM1_CH1 DMA2_ST3
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#define DEF_TIM_DMA_STR_0__TIM1_CH1N DMA2_ST6
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#define DEF_TIM_DMA_STR_1__TIM1_CH1N DMA2_ST1
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#define DEF_TIM_DMA_STR_2__TIM1_CH1N DMA2_ST3
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#define DEF_TIM_DMA_STR_0__TIM1_CH2 DMA2_ST6
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#define DEF_TIM_DMA_STR_1__TIM1_CH2 DMA2_ST2
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#define DEF_TIM_DMA_STR_0__TIM1_CH2N DMA2_ST6
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#define DEF_TIM_DMA_STR_1__TIM1_CH2N DMA2_ST2
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#define DEF_TIM_DMA_STR_0__TIM1_CH3 DMA2_ST6
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#define DEF_TIM_DMA_STR_1__TIM1_CH3 DMA2_ST6
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#define DEF_TIM_DMA_STR_0__TIM1_CH3N DMA2_ST6
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#define DEF_TIM_DMA_STR_1__TIM1_CH3N DMA2_ST6
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#define DEF_TIM_DMA_STR_0__TIM1_CH4 DMA2_ST4
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#define DEF_TIM_DMA_STR_0__TIM2_CH1 DMA1_ST5
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#define DEF_TIM_DMA_STR_0__TIM2_CH2 DMA1_ST6
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#define DEF_TIM_DMA_STR_0__TIM2_CH3 DMA1_ST1
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#define DEF_TIM_DMA_STR_0__TIM2_CH4 DMA1_ST7
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#define DEF_TIM_DMA_STR_1__TIM2_CH4 DMA1_ST6
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#define DEF_TIM_DMA_STR_0__TIM3_CH1 DMA1_ST4
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#define DEF_TIM_DMA_STR_0__TIM3_CH2 DMA1_ST5
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#define DEF_TIM_DMA_STR_0__TIM3_CH3 DMA1_ST7
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#define DEF_TIM_DMA_STR_0__TIM3_CH4 DMA1_ST2
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#define DEF_TIM_DMA_STR_0__TIM4_CH1 DMA1_ST0
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#define DEF_TIM_DMA_STR_0__TIM4_CH2 DMA1_ST4
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#define DEF_TIM_DMA_STR_0__TIM4_CH3 DMA1_ST7
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#define DEF_TIM_DMA_STR_0__TIM4_CH4 DMA1_ST3
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#define DEF_TIM_DMA_STR_0__TIM5_CH1 DMA1_ST2
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#define DEF_TIM_DMA_STR_0__TIM5_CH2 DMA1_ST4
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#define DEF_TIM_DMA_STR_0__TIM5_CH3 DMA1_ST0
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#define DEF_TIM_DMA_STR_0__TIM5_CH4 DMA1_ST1
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#define DEF_TIM_DMA_STR_1__TIM5_CH4 DMA1_ST3
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#define DEF_TIM_DMA_STR_0__TIM8_CH1 DMA2_ST2
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#define DEF_TIM_DMA_STR_1__TIM8_CH1 DMA2_ST2
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#define DEF_TIM_DMA_STR_0__TIM8_CH1N DMA2_ST2
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#define DEF_TIM_DMA_STR_1__TIM8_CH1N DMA2_ST2
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#define DEF_TIM_DMA_STR_0__TIM8_CH2 DMA2_ST3
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#define DEF_TIM_DMA_STR_1__TIM8_CH2 DMA2_ST2
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#define DEF_TIM_DMA_STR_0__TIM8_CH2N DMA2_ST3
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#define DEF_TIM_DMA_STR_1__TIM8_CH2N DMA2_ST2
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#define DEF_TIM_DMA_STR_0__TIM8_CH3 DMA2_ST2
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#define DEF_TIM_DMA_STR_1__TIM8_CH3 DMA2_ST4
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#define DEF_TIM_DMA_STR_0__TIM8_CH3N DMA2_ST2
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#define DEF_TIM_DMA_STR_1__TIM8_CH3N DMA2_ST4
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#define DEF_TIM_DMA_STR_0__TIM8_CH4 DMA2_ST7
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#define DEF_TIM_DMA_STR_0__TIM9_CH1 DMA_NONE
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#define DEF_TIM_DMA_STR_0__TIM9_CH2 DMA_NONE
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#define DEF_TIM_DMA_STR_0__TIM10_CH1 DMA_NONE
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#define DEF_TIM_DMA_STR_0__TIM11_CH1 DMA_NONE
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#define DEF_TIM_DMA_STR_0__TIM12_CH1 DMA_NONE
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#define DEF_TIM_DMA_STR_0__TIM12_CH2 DMA_NONE
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#define DEF_TIM_DMA_STR_0__TIM13_CH1 DMA_NONE
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#define DEF_TIM_DMA_STR_0__TIM14_CH1 DMA_NONE
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/* F4 Channel Mappings */
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#define DEF_TIM_DMA_CHN_0__TIM1_CH1 DMA_Channel_0
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#define DEF_TIM_DMA_CHN_1__TIM1_CH1 DMA_Channel_6
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#define DEF_TIM_DMA_CHN_2__TIM1_CH1 DMA_Channel_6
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#define DEF_TIM_DMA_CHN_0__TIM1_CH1N DMA_Channel_0
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#define DEF_TIM_DMA_CHN_1__TIM1_CH1N DMA_Channel_6
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#define DEF_TIM_DMA_CHN_2__TIM1_CH1N DMA_Channel_6
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#define DEF_TIM_DMA_CHN_0__TIM1_CH2 DMA_Channel_0
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#define DEF_TIM_DMA_CHN_1__TIM1_CH2 DMA_Channel_6
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#define DEF_TIM_DMA_CHN_0__TIM1_CH2N DMA_Channel_0
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#define DEF_TIM_DMA_CHN_1__TIM1_CH2N DMA_Channel_6
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#define DEF_TIM_DMA_CHN_0__TIM1_CH3 DMA_Channel_0
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#define DEF_TIM_DMA_CHN_1__TIM1_CH3 DMA_Channel_6
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#define DEF_TIM_DMA_CHN_0__TIM1_CH3N DMA_Channel_0
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#define DEF_TIM_DMA_CHN_1__TIM1_CH3N DMA_Channel_6
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#define DEF_TIM_DMA_CHN_0__TIM1_CH4 DMA_Channel_6
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#define DEF_TIM_DMA_CHN_0__TIM2_CH1 DMA_Channel_3
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#define DEF_TIM_DMA_CHN_0__TIM2_CH2 DMA_Channel_3
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#define DEF_TIM_DMA_CHN_0__TIM2_CH3 DMA_Channel_3
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#define DEF_TIM_DMA_CHN_0__TIM2_CH4 DMA_Channel_3
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#define DEF_TIM_DMA_CHN_1__TIM2_CH4 DMA_Channel_3
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#define DEF_TIM_DMA_CHN_0__TIM3_CH1 DMA_Channel_5
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#define DEF_TIM_DMA_CHN_0__TIM3_CH2 DMA_Channel_5
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#define DEF_TIM_DMA_CHN_0__TIM3_CH3 DMA_Channel_5
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#define DEF_TIM_DMA_CHN_0__TIM3_CH4 DMA_Channel_5
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#define DEF_TIM_DMA_CHN_0__TIM4_CH1 DMA_Channel_2
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#define DEF_TIM_DMA_CHN_0__TIM4_CH2 DMA_Channel_2
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#define DEF_TIM_DMA_CHN_0__TIM4_CH3 DMA_Channel_2
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#define DEF_TIM_DMA_CHN_0__TIM4_CH4 DMA_Channel_2
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#define DEF_TIM_DMA_CHN_0__TIM5_CH1 DMA_Channel_6
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#define DEF_TIM_DMA_CHN_0__TIM5_CH2 DMA_Channel_6
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#define DEF_TIM_DMA_CHN_0__TIM5_CH3 DMA_Channel_6
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#define DEF_TIM_DMA_CHN_0__TIM5_CH4 DMA_Channel_6
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#define DEF_TIM_DMA_CHN_1__TIM5_CH4 DMA_Channel_6
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#define DEF_TIM_DMA_CHN_0__TIM8_CH1 DMA_Channel_0
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#define DEF_TIM_DMA_CHN_1__TIM8_CH1 DMA_Channel_7
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#define DEF_TIM_DMA_CHN_0__TIM8_CH1N DMA_Channel_0
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#define DEF_TIM_DMA_CHN_1__TIM8_CH1N DMA_Channel_7
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#define DEF_TIM_DMA_CHN_0__TIM8_CH2 DMA_Channel_0
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#define DEF_TIM_DMA_CHN_1__TIM8_CH2 DMA_Channel_7
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#define DEF_TIM_DMA_CHN_0__TIM8_CH2N DMA_Channel_0
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#define DEF_TIM_DMA_CHN_1__TIM8_CH2N DMA_Channel_7
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#define DEF_TIM_DMA_CHN_0__TIM8_CH3 DMA_Channel_0
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#define DEF_TIM_DMA_CHN_1__TIM8_CH3 DMA_Channel_7
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#define DEF_TIM_DMA_CHN_0__TIM8_CH3N DMA_Channel_0
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#define DEF_TIM_DMA_CHN_1__TIM8_CH3N DMA_Channel_7
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#define DEF_TIM_DMA_CHN_0__TIM8_CH4 DMA_Channel_7
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#define DEF_TIM_DMA_CHN_0__TIM9_CH1 0
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#define DEF_TIM_DMA_CHN_0__TIM9_CH2 0
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#define DEF_TIM_DMA_CHN_0__TIM10_CH1 0
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#define DEF_TIM_DMA_CHN_0__TIM11_CH1 0
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#define DEF_TIM_DMA_CHN_0__TIM12_CH1 0
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#define DEF_TIM_DMA_CHN_0__TIM12_CH2 0
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#define DEF_TIM_DMA_CHN_0__TIM13_CH1 0
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#define DEF_TIM_DMA_CHN_0__TIM14_CH1 0
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#define DMA1_ST0_STREAM DMA1_Stream0
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#define DMA1_ST1_STREAM DMA1_Stream1
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#define DMA1_ST2_STREAM DMA1_Stream2
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#define DMA1_ST3_STREAM DMA1_Stream3
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#define DMA1_ST4_STREAM DMA1_Stream4
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#define DMA1_ST5_STREAM DMA1_Stream5
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#define DMA1_ST6_STREAM DMA1_Stream6
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#define DMA1_ST7_STREAM DMA1_Stream7
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#define DMA2_ST0_STREAM DMA2_Stream0
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#define DMA2_ST1_STREAM DMA2_Stream1
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#define DMA2_ST2_STREAM DMA2_Stream2
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#define DMA2_ST3_STREAM DMA2_Stream3
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#define DMA2_ST4_STREAM DMA2_Stream4
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#define DMA2_ST5_STREAM DMA2_Stream5
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#define DMA2_ST6_STREAM DMA2_Stream6
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#define DMA2_ST7_STREAM DMA2_Stream7
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#endif
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/**** Common Defines across all targets ****/
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#define DMA_NONE_CHANNEL NULL
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#define DMA_NONE_STREAM NULL
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#define DEF_TIM_CHAN(chan) DEF_CHAN_ ## chan
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#define DEF_TIM_OUTPUT(chan, out) ( DEF_CHAN_ ## chan ## _OUTPUT | out )
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#define DMA_NONE_HANDLER 0
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#define DEF_CHAN_CH1 TIM_Channel_1
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#define DEF_CHAN_CH2 TIM_Channel_2
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#define DEF_CHAN_CH3 TIM_Channel_3
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#define DEF_CHAN_CH4 TIM_Channel_4
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#define DEF_CHAN_CH1N TIM_Channel_1
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#define DEF_CHAN_CH2N TIM_Channel_2
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#define DEF_CHAN_CH3N TIM_Channel_3
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#define DEF_CHAN_CH4N TIM_Channel_4
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#define DEF_CHAN_CH1_OUTPUT TIMER_OUTPUT_NONE
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#define DEF_CHAN_CH2_OUTPUT TIMER_OUTPUT_NONE
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#define DEF_CHAN_CH3_OUTPUT TIMER_OUTPUT_NONE
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#define DEF_CHAN_CH4_OUTPUT TIMER_OUTPUT_NONE
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#define DEF_CHAN_CH1N_OUTPUT TIMER_OUTPUT_N_CHANNEL
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#define DEF_CHAN_CH2N_OUTPUT TIMER_OUTPUT_N_CHANNEL
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#define DEF_CHAN_CH3N_OUTPUT TIMER_OUTPUT_N_CHANNEL
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#define DEF_CHAN_CH4N_OUTPUT TIMER_OUTPUT_N_CHANNEL
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#define DMA1_CH1_CHANNEL DMA1_Channel1
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#define DMA1_CH2_CHANNEL DMA1_Channel2
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#define DMA1_CH3_CHANNEL DMA1_Channel3
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#define DMA1_CH4_CHANNEL DMA1_Channel4
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#define DMA1_CH5_CHANNEL DMA1_Channel5
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#define DMA1_CH6_CHANNEL DMA1_Channel6
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#define DMA1_CH7_CHANNEL DMA1_Channel7
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#define DMA2_CH1_CHANNEL DMA2_Channel1
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#define DMA2_CH2_CHANNEL DMA2_Channel2
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#define DMA2_CH3_CHANNEL DMA2_Channel3
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#define DMA2_CH4_CHANNEL DMA2_Channel4
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#define DMA2_CH5_CHANNEL DMA2_Channel5
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#define DMA2_CH6_CHANNEL DMA2_Channel6
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#define DMA2_CH7_CHANNEL DMA2_Channel7 |