mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-17 05:15:25 +03:00
308 lines
9 KiB
C
308 lines
9 KiB
C
/*
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* This file is part of Cleanflight.
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*
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* Cleanflight is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Cleanflight is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "platform.h"
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#include "drivers/accgyro/accgyro_mpu.h"
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#include "drivers/exti.h"
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#include "drivers/nvic.h"
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#include "drivers/persistent.h"
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#include "drivers/system.h"
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void SystemClock_Config(void);
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void enablePeripherialClocks(void)
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{
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__HAL_RCC_MDMA_CLK_ENABLE();
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__HAL_RCC_QSPI_CLK_ENABLE();
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// AHB1
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__HAL_RCC_DMA1_CLK_ENABLE();
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__HAL_RCC_DMA2_CLK_ENABLE();
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__HAL_RCC_ADC12_CLK_ENABLE();
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// USB clock will be enabled by vcpXXX/usbd_conf.c
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// Note that enabling both ULPI and non-ULPI does not work.
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// AHB2
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__HAL_RCC_D2SRAM1_CLK_ENABLE();
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__HAL_RCC_D2SRAM2_CLK_ENABLE();
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__HAL_RCC_D2SRAM3_CLK_ENABLE();
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// AHB4
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_GPIOF_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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__HAL_RCC_GPIOH_CLK_ENABLE();
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__HAL_RCC_GPIOI_CLK_ENABLE();
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__HAL_RCC_GPIOJ_CLK_ENABLE();
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__HAL_RCC_GPIOK_CLK_ENABLE();
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__HAL_RCC_BDMA_CLK_ENABLE();
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__HAL_RCC_ADC3_CLK_ENABLE();
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// APB3
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// APB1
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__HAL_RCC_TIM2_CLK_ENABLE();
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__HAL_RCC_TIM3_CLK_ENABLE();
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__HAL_RCC_TIM4_CLK_ENABLE();
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__HAL_RCC_TIM5_CLK_ENABLE();
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__HAL_RCC_TIM6_CLK_ENABLE();
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__HAL_RCC_TIM7_CLK_ENABLE();
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__HAL_RCC_TIM12_CLK_ENABLE();
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__HAL_RCC_TIM13_CLK_ENABLE();
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__HAL_RCC_TIM14_CLK_ENABLE();
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__HAL_RCC_LPTIM1_CLK_ENABLE();
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__HAL_RCC_SPI2_CLK_ENABLE();
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__HAL_RCC_SPI3_CLK_ENABLE();
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__HAL_RCC_USART2_CLK_ENABLE();
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__HAL_RCC_USART3_CLK_ENABLE();
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__HAL_RCC_UART4_CLK_ENABLE();
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__HAL_RCC_UART5_CLK_ENABLE();
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__HAL_RCC_I2C1_CLK_ENABLE();
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__HAL_RCC_I2C2_CLK_ENABLE();
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__HAL_RCC_I2C3_CLK_ENABLE();
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__HAL_RCC_DAC12_CLK_ENABLE();
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__HAL_RCC_UART7_CLK_ENABLE();
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__HAL_RCC_UART8_CLK_ENABLE();
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__HAL_RCC_CRS_CLK_ENABLE();
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// APB2
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__HAL_RCC_TIM1_CLK_ENABLE();
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__HAL_RCC_TIM8_CLK_ENABLE();
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__HAL_RCC_USART1_CLK_ENABLE();
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__HAL_RCC_USART6_CLK_ENABLE();
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__HAL_RCC_SPI1_CLK_ENABLE();
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__HAL_RCC_SPI4_CLK_ENABLE();
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__HAL_RCC_TIM15_CLK_ENABLE();
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__HAL_RCC_TIM16_CLK_ENABLE();
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__HAL_RCC_TIM17_CLK_ENABLE();
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__HAL_RCC_SPI5_CLK_ENABLE();
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// APB4
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__HAL_RCC_SYSCFG_CLK_ENABLE();
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__HAL_RCC_LPUART1_CLK_ENABLE();
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__HAL_RCC_SPI6_CLK_ENABLE();
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__HAL_RCC_I2C4_CLK_ENABLE();
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__HAL_RCC_LPTIM2_CLK_ENABLE();
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__HAL_RCC_LPTIM3_CLK_ENABLE();
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__HAL_RCC_LPTIM4_CLK_ENABLE();
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__HAL_RCC_LPTIM5_CLK_ENABLE();
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__HAL_RCC_COMP12_CLK_ENABLE();
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__HAL_RCC_VREF_CLK_ENABLE();
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}
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void enableGPIOPowerUsageAndNoiseReductions(void)
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{
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// GPIO initialization, copied from drivers/system_stm32f7xx.c
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// ... It was commented out.
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// Where does F7 initializes the GPIO pins? It doesn't do it at all???
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//
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// GPIO_InitTypeDef GPIO_InitStructure;
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// GPIO_StructInit(&GPIO_InitStructure);
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// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; // default is un-pulled input
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
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// GPIO_InitStructure.GPIO_Pin &= ~(GPIO_Pin_11 | GPIO_Pin_12); // leave USB D+/D- alone
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//
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// GPIO_InitStructure.GPIO_Pin &= ~(GPIO_Pin_13 | GPIO_Pin_14); // leave JTAG pins alone
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// GPIO_Init(GPIOA, &GPIO_InitStructure);
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
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// GPIO_Init(GPIOB, &GPIO_InitStructure);
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
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// GPIO_Init(GPIOC, &GPIO_InitStructure);
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// GPIO_Init(GPIOD, &GPIO_InitStructure);
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// GPIO_Init(GPIOE, &GPIO_InitStructure);
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}
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void configureMasterClockOutputs(void)
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{
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// Initialize pins for MCO1 and MCO2 for clock testing/verification
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GPIO_InitTypeDef GPIO_InitStruct;
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GPIO_InitStruct.Pin = GPIO_PIN_8;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = GPIO_PIN_9;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
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HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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}
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bool isMPUSoftReset(void)
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{
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if (cachedRccCsrValue & RCC_RSR_SFTRSTF)
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return true;
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else
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return false;
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}
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void systemInit(void)
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{
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#ifdef USE_ITCM_RAM
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// Mark ITCM-RAM as read-only
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HAL_MPU_Disable();
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// "For Cortex®-M7, TCMs memories always behave as Non-cacheable, Non-shared normal memories, irrespective of the memory type attributes defined in the MPU for a memory region containing addresses held in the TCM"
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// See AN4838
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MPU_Region_InitTypeDef MPU_InitStruct;
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.BaseAddress = 0x00000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_64KB;
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MPU_InitStruct.AccessPermission = MPU_REGION_PRIV_RO_URO;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER0;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.SubRegionDisable = 0x00;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
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#endif
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// Configure NVIC preempt/priority groups
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HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUPING);
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// cache RCC->RSR value to use it in isMPUSoftReset() and others
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cachedRccCsrValue = RCC->RSR;
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/* Accounts for OP Bootloader, set the Vector Table base address as specified in .ld file */
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//extern void *isr_vector_table_base;
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//NVIC_SetVectorTable((uint32_t)&isr_vector_table_base, 0x0);
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//__HAL_RCC_USB_OTG_FS_CLK_DISABLE;
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//RCC_ClearFlag();
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enablePeripherialClocks();
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enableGPIOPowerUsageAndNoiseReductions();
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#ifdef USE_MCO_OUTPUTS
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configureMasterClockOutputs();
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#endif
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// Init cycle counter
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cycleCounterInit();
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// SysTick is updated whenever HAL_RCC_ClockConfig is called.
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}
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void systemReset(void)
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{
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SCB_DisableDCache();
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SCB_DisableICache();
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__disable_irq();
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NVIC_SystemReset();
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}
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void forcedSystemResetWithoutDisablingCaches(void)
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{
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persistentObjectWrite(PERSISTENT_OBJECT_RESET_REASON, RESET_FORCED);
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__disable_irq();
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NVIC_SystemReset();
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}
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void systemResetToBootloader(bootloaderRequestType_e requestType)
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{
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switch (requestType) {
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#if defined(USE_FLASH_BOOT_LOADER)
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case BOOTLOADER_REQUEST_FLASH:
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persistentObjectWrite(PERSISTENT_OBJECT_RESET_REASON, RESET_BOOTLOADER_REQUEST_FLASH);
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break;
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#endif
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case BOOTLOADER_REQUEST_ROM:
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default:
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persistentObjectWrite(PERSISTENT_OBJECT_RESET_REASON, RESET_BOOTLOADER_REQUEST_ROM);
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break;
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}
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__disable_irq();
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NVIC_SystemReset();
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}
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static uint32_t bootloaderRequest;
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void systemCheckResetReason(void)
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{
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bootloaderRequest = persistentObjectRead(PERSISTENT_OBJECT_RESET_REASON);
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switch (bootloaderRequest) {
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#if defined(USE_FLASH_BOOT_LOADER)
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case RESET_BOOTLOADER_REQUEST_FLASH:
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#endif
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case RESET_BOOTLOADER_REQUEST_ROM:
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persistentObjectWrite(PERSISTENT_OBJECT_RESET_REASON, RESET_BOOTLOADER_POST);
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break;
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case RESET_FORCED:
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persistentObjectWrite(PERSISTENT_OBJECT_RESET_REASON, RESET_NONE);
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return;
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case RESET_NONE:
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if (!(RCC->RSR & RCC_RSR_SFTRSTF)) {
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// Direct hard reset case
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return;
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}
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// Soft reset; boot loader may have been active with BOOT pin pulled high.
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FALLTHROUGH;
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case RESET_BOOTLOADER_POST:
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// Boot loader activity magically prevents SysTick from interrupting.
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// Issue a soft reset to prevent the condition.
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forcedSystemResetWithoutDisablingCaches(); // observed that disabling dcache after cold boot with BOOT pin high causes segfault.
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}
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void (*SysMemBootJump)(void);
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__SYSCFG_CLK_ENABLE();
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uint32_t p = (*((uint32_t *) 0x1ff09800));
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__set_MSP(p); //Set the main stack pointer to its defualt values
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SysMemBootJump = (void (*)(void)) (*((uint32_t *) 0x1ff09804)); // Point the PC to the System Memory reset vector (+4)
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SysMemBootJump();
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while (1);
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}
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