mirror of
https://github.com/iNavFlight/inav.git
synced 2025-07-23 16:25:26 +03:00
Add actual stack watermarking to startup code; add stack status to CLI status
This commit is contained in:
parent
65e37cd476
commit
7cc049a3c6
9 changed files with 599 additions and 478 deletions
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@ -19,6 +19,7 @@
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extern char _estack; // end of stack, declared in .LD file
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extern char _estack; // end of stack, declared in .LD file
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extern char _Min_Stack_Size; // declared in .LD file
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extern char _Min_Stack_Size; // declared in .LD file
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static uint32_t _Used_Stack_Size;
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/*
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/*
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* The ARM processor uses a full descending stack. This means the stack pointer holds the address
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* The ARM processor uses a full descending stack. This means the stack pointer holds the address
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@ -54,11 +55,25 @@ void taskStackCheck(void)
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break;
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break;
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}
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}
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}
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}
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_Used_Stack_Size = (uint32_t)stackHighMem - (uint32_t)p;
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#ifdef DEBUG_STACK
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#ifdef DEBUG_STACK
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debug[0] = (uint32_t)stackHighMem & 0xffff;
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debug[0] = (uint32_t)stackHighMem & 0xffff;
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debug[1] = (uint32_t)stackLowMem & 0xffff;
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debug[1] = (uint32_t)stackLowMem & 0xffff;
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debug[2] = (uint32_t)stackCurrent & 0xffff;
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debug[2] = (uint32_t)stackCurrent & 0xffff;
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debug[3] = (uint32_t)p & 0xffff; // watermark
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debug[3] = (uint32_t)p & 0xffff;
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#endif
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#endif
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}
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}
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uint32_t getTotalStackSize(void)
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{
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return (uint32_t)&_Min_Stack_Size;
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}
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uint32_t getUsedStackSize(void)
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{
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return _Used_Stack_Size;
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}
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#endif
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#endif
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23
src/main/drivers/stack_check.h
Executable file
23
src/main/drivers/stack_check.h
Executable file
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@ -0,0 +1,23 @@
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/*
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* This file is part of Cleanflight.
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*
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* Cleanflight is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Cleanflight is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#ifdef STACK_CHECK
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uint32_t getTotalStackSize(void);
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uint32_t getUsedStackSize(void);
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#endif
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@ -52,6 +52,7 @@
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#include "drivers/timer.h"
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#include "drivers/timer.h"
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#include "drivers/pwm_rx.h"
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#include "drivers/pwm_rx.h"
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#include "drivers/sdcard.h"
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#include "drivers/sdcard.h"
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#include "drivers/stack_check.h"
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#include "drivers/buf_writer.h"
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#include "drivers/buf_writer.h"
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@ -2817,6 +2818,10 @@ static void cliStatus(char *cmdline)
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const uint16_t i2cErrorCounter = 0;
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const uint16_t i2cErrorCounter = 0;
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#endif
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#endif
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#ifdef STACK_CHECK
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cliPrintf("Used stack: %d, Total stack: %d\r\n", getUsedStackSize(), getTotalStackSize());
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#endif
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cliPrintf("Cycle Time: %d, I2C Errors: %d, config size: %d\r\n", cycleTime, i2cErrorCounter, sizeof(master_t));
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cliPrintf("Cycle Time: %d, I2C Errors: %d, config size: %d\r\n", cycleTime, i2cErrorCounter, sizeof(master_t));
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}
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}
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@ -98,6 +98,19 @@ LoopFillZerobss:
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cmp r2, r3
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cmp r2, r3
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bcc FillZerobss
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bcc FillZerobss
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/* Mark the heap and stack */
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ldr r2, =_heap_stack_begin
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b LoopMarkHeapStack
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MarkHeapStack:
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movs r3, 0xa5a5a5a5
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str r3, [r2], #4
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LoopMarkHeapStack:
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ldr r3, = _heap_stack_end
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cmp r2, r3
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bcc MarkHeapStack
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/* Call the clock system intitialization function.*/
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/* Call the clock system intitialization function.*/
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bl SystemInit
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bl SystemInit
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/* Call the application's entry point.*/
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/* Call the application's entry point.*/
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@ -105,7 +118,7 @@ LoopFillZerobss:
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/* Atollic update, branch LoopForever */
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/* Atollic update, branch LoopForever */
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LoopForever:
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LoopForever:
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b LoopForever
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b LoopForever
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.equ RCC_APB2ENR, 0x40021018 // HJI - TC bootloader entry on reset mod
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.equ RCC_APB2ENR, 0x40021018 // HJI - TC bootloader entry on reset mod
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.equ GPIO_AFIO_MASK, 0x00000009 // HJI - TC bootloader entry on reset mod
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.equ GPIO_AFIO_MASK, 0x00000009 // HJI - TC bootloader entry on reset mod
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.equ GPIOB_CRL, 0x40010C00 // HJI - TC bootloader entry on reset mod
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.equ GPIOB_CRL, 0x40010C00 // HJI - TC bootloader entry on reset mod
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@ -117,27 +130,27 @@ Reboot_Loader: // HJI - TC bootloader entry on reset mod
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ldr r6, =RCC_APB2ENR // HJI - TC bootloader entry on reset mod
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ldr r6, =RCC_APB2ENR // HJI - TC bootloader entry on reset mod
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ldr r0, =GPIO_AFIO_MASK // HJI - TC bootloader entry on reset mod
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ldr r0, =GPIO_AFIO_MASK // HJI - TC bootloader entry on reset mod
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str R0, [r6]; // HJI - TC bootloader entry on reset mod
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str R0, [r6]; // HJI - TC bootloader entry on reset mod
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// MAPR pt1 // HJI - TC bootloader entry on reset mod
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// MAPR pt1 // HJI - TC bootloader entry on reset mod
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ldr r0, =AFIO_MAPR // HJI - TC bootloader entry on reset mod
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ldr r0, =AFIO_MAPR // HJI - TC bootloader entry on reset mod
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ldr r1, [r0] // HJI - TC bootloader entry on reset mod
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ldr r1, [r0] // HJI - TC bootloader entry on reset mod
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bic r1, r1, #0x0F000000 // HJI - TC bootloader entry on reset mod
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bic r1, r1, #0x0F000000 // HJI - TC bootloader entry on reset mod
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str r1, [r0] // HJI - TC bootloader entry on reset mod
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str r1, [r0] // HJI - TC bootloader entry on reset mod
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// MAPR pt2 // HJI - TC bootloader entry on reset mod
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// MAPR pt2 // HJI - TC bootloader entry on reset mod
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lsls r1, r0, #9 // HJI - TC bootloader entry on reset mod
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lsls r1, r0, #9 // HJI - TC bootloader entry on reset mod
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str r1, [r0] // HJI - TC bootloader entry on reset mod
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str r1, [r0] // HJI - TC bootloader entry on reset mod
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// BRR // HJI - TC bootloader entry on reset mod
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// BRR // HJI - TC bootloader entry on reset mod
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ldr r4, =GPIOB_BRR // HJI - TC bootloader entry on reset mod
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ldr r4, =GPIOB_BRR // HJI - TC bootloader entry on reset mod
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movs r0, #0x18 // HJI - TC bootloader entry on reset mod
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movs r0, #0x18 // HJI - TC bootloader entry on reset mod
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str r0, [r4] // HJI - TC bootloader entry on reset mod
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str r0, [r4] // HJI - TC bootloader entry on reset mod
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// CRL // HJI - TC bootloader entry on reset mod
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// CRL // HJI - TC bootloader entry on reset mod
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ldr r1, =GPIOB_CRL // HJI - TC bootloader entry on reset mod
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ldr r1, =GPIOB_CRL // HJI - TC bootloader entry on reset mod
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ldr r0, =0x44433444 // HJI - TC bootloader entry on reset mod
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ldr r0, =0x44433444 // HJI - TC bootloader entry on reset mod
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str r0, [r1] // HJI - TC bootloader entry on reset mod
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str r0, [r1] // HJI - TC bootloader entry on reset mod
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// Reboot to ROM // HJI - TC bootloader entry on reset mod
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// Reboot to ROM // HJI - TC bootloader entry on reset mod
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ldr r0, =0x1FFFF000 // HJI - TC bootloader entry on reset mod
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ldr r0, =0x1FFFF000 // HJI - TC bootloader entry on reset mod
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ldr sp,[r0, #0] // HJI - TC bootloader entry on reset mod
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ldr sp,[r0, #0] // HJI - TC bootloader entry on reset mod
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@ -97,6 +97,19 @@ LoopFillZerobss:
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cmp r2, r3
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cmp r2, r3
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bcc FillZerobss
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bcc FillZerobss
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/* Mark the heap and stack */
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ldr r2, =_heap_stack_begin
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b LoopMarkHeapStack
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MarkHeapStack:
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movs r3, 0xa5a5a5a5
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str r3, [r2], #4
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LoopMarkHeapStack:
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ldr r3, = _heap_stack_end
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cmp r2, r3
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bcc MarkHeapStack
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/* Call the clock system intitialization function.*/
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/* Call the clock system intitialization function.*/
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bl SystemInit
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bl SystemInit
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/* Call the application's entry point.*/
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/* Call the application's entry point.*/
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/* Atollic update, branch LoopForever */
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/* Atollic update, branch LoopForever */
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LoopForever:
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LoopForever:
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b LoopForever
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b LoopForever
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.equ RCC_APB2ENR, 0x40021018 // HJI - TC bootloader entry on reset mod
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.equ RCC_APB2ENR, 0x40021018 // HJI - TC bootloader entry on reset mod
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.equ GPIO_AFIO_MASK, 0x00000009 // HJI - TC bootloader entry on reset mod
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.equ GPIO_AFIO_MASK, 0x00000009 // HJI - TC bootloader entry on reset mod
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.equ GPIOB_CRL, 0x40010C00 // HJI - TC bootloader entry on reset mod
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.equ GPIOB_CRL, 0x40010C00 // HJI - TC bootloader entry on reset mod
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@ -116,27 +129,27 @@ Reboot_Loader: // HJI - TC bootloader entry on reset mod
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ldr r6, =RCC_APB2ENR // HJI - TC bootloader entry on reset mod
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ldr r6, =RCC_APB2ENR // HJI - TC bootloader entry on reset mod
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ldr r0, =GPIO_AFIO_MASK // HJI - TC bootloader entry on reset mod
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ldr r0, =GPIO_AFIO_MASK // HJI - TC bootloader entry on reset mod
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str R0, [r6]; // HJI - TC bootloader entry on reset mod
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str R0, [r6]; // HJI - TC bootloader entry on reset mod
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// MAPR pt1 // HJI - TC bootloader entry on reset mod
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// MAPR pt1 // HJI - TC bootloader entry on reset mod
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ldr r0, =AFIO_MAPR // HJI - TC bootloader entry on reset mod
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ldr r0, =AFIO_MAPR // HJI - TC bootloader entry on reset mod
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ldr r1, [r0] // HJI - TC bootloader entry on reset mod
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ldr r1, [r0] // HJI - TC bootloader entry on reset mod
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bic r1, r1, #0x0F000000 // HJI - TC bootloader entry on reset mod
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bic r1, r1, #0x0F000000 // HJI - TC bootloader entry on reset mod
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str r1, [r0] // HJI - TC bootloader entry on reset mod
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str r1, [r0] // HJI - TC bootloader entry on reset mod
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// MAPR pt2 // HJI - TC bootloader entry on reset mod
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// MAPR pt2 // HJI - TC bootloader entry on reset mod
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lsls r1, r0, #9 // HJI - TC bootloader entry on reset mod
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lsls r1, r0, #9 // HJI - TC bootloader entry on reset mod
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str r1, [r0] // HJI - TC bootloader entry on reset mod
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str r1, [r0] // HJI - TC bootloader entry on reset mod
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// BRR // HJI - TC bootloader entry on reset mod
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// BRR // HJI - TC bootloader entry on reset mod
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ldr r4, =GPIOB_BRR // HJI - TC bootloader entry on reset mod
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ldr r4, =GPIOB_BRR // HJI - TC bootloader entry on reset mod
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movs r0, #0x18 // HJI - TC bootloader entry on reset mod
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movs r0, #0x18 // HJI - TC bootloader entry on reset mod
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str r0, [r4] // HJI - TC bootloader entry on reset mod
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str r0, [r4] // HJI - TC bootloader entry on reset mod
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// CRL // HJI - TC bootloader entry on reset mod
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// CRL // HJI - TC bootloader entry on reset mod
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ldr r1, =GPIOB_CRL // HJI - TC bootloader entry on reset mod
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ldr r1, =GPIOB_CRL // HJI - TC bootloader entry on reset mod
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ldr r0, =0x44433444 // HJI - TC bootloader entry on reset mod
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ldr r0, =0x44433444 // HJI - TC bootloader entry on reset mod
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str r0, [r1] // HJI - TC bootloader entry on reset mod
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str r0, [r1] // HJI - TC bootloader entry on reset mod
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// Reboot to ROM // HJI - TC bootloader entry on reset mod
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// Reboot to ROM // HJI - TC bootloader entry on reset mod
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ldr r0, =0x1FFFF000 // HJI - TC bootloader entry on reset mod
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ldr r0, =0x1FFFF000 // HJI - TC bootloader entry on reset mod
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ldr sp,[r0, #0] // HJI - TC bootloader entry on reset mod
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ldr sp,[r0, #0] // HJI - TC bootloader entry on reset mod
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cmp r2, r3
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cmp r2, r3
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bcc FillZerobss
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bcc FillZerobss
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/* Mark the heap and stack */
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ldr r2, =_heap_stack_begin
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b LoopMarkHeapStack
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MarkHeapStack:
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movs r3, 0xa5a5a5a5
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str r3, [r2], #4
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LoopMarkHeapStack:
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ldr r3, = _heap_stack_end
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cmp r2, r3
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bcc MarkHeapStack
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/* Call the clock system intitialization function.*/
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/* Call the clock system intitialization function.*/
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bl SystemInit
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bl SystemInit
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/* Call the application's entry point.*/
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/* Call the application's entry point.*/
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cmp r2, r3
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cmp r2, r3
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bcc FillZerobss
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bcc FillZerobss
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/* Mark the heap and stack */
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ldr r2, =_heap_stack_begin
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b LoopMarkHeapStack
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MarkHeapStack:
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movs r3, 0xa5a5a5a5
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str r3, [r2], #4
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LoopMarkHeapStack:
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ldr r3, = _heap_stack_end
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cmp r2, r3
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bcc MarkHeapStack
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/* Call the clock system intitialization function.*/
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/* Call the clock system intitialization function.*/
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bl SystemInit
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bl SystemInit
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/* Call the application's entry point.*/
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/* Call the application's entry point.*/
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@ -4,14 +4,14 @@
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* @author MCD Application Team
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* @author MCD Application Team
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* @version V1.6.1
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* @version V1.6.1
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* @date 21-October-2015
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* @date 21-October-2015
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* @brief STM32F40xxx/41xxx Devices vector table for Atollic TrueSTUDIO toolchain.
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* @brief STM32F40xxx/41xxx Devices vector table for Atollic TrueSTUDIO toolchain.
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* Same as startup_stm32f40_41xxx.s and maintained for legacy purpose
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* Same as startup_stm32f40_41xxx.s and maintained for legacy purpose
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* This module performs:
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* This module performs:
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* - Set the initial SP
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Set the vector table entries with the exceptions ISR address
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* - Configure the clock system and the external SRAM mounted on
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* - Configure the clock system and the external SRAM mounted on
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* STM324xG-EVAL board to be used as data memory (optional,
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* STM324xG-EVAL board to be used as data memory (optional,
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* to be enabled by user)
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* to be enabled by user)
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* - Branches to main in the C library (which eventually
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* - Branches to main in the C library (which eventually
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* calls main()).
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* calls main()).
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*
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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*
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* Unless required by applicable law or agreed to in writing, software
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* limitations under the License.
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*
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*
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******************************************************************************
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******************************************************************************
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*/
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*/
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.syntax unified
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.syntax unified
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.cpu cortex-m4
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.cpu cortex-m4
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.fpu softvfp
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.fpu softvfp
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.global Default_Handler
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.global Default_Handler
|
||||||
.global irq_stack
|
.global irq_stack
|
||||||
|
|
||||||
/* start address for the initialization values of the .data section.
|
/* start address for the initialization values of the .data section.
|
||||||
defined in linker script */
|
defined in linker script */
|
||||||
.word _sidata
|
.word _sidata
|
||||||
/* start address for the .data section. defined in linker script */
|
/* start address for the .data section. defined in linker script */
|
||||||
.word _sdata
|
.word _sdata
|
||||||
/* end address for the .data section. defined in linker script */
|
/* end address for the .data section. defined in linker script */
|
||||||
.word _edata
|
.word _edata
|
||||||
|
@ -63,7 +63,7 @@ defined in linker script */
|
||||||
* @brief This is the code that gets called when the processor first
|
* @brief This is the code that gets called when the processor first
|
||||||
* starts execution following a reset event. Only the absolutely
|
* starts execution following a reset event. Only the absolutely
|
||||||
* necessary set is performed, after which the application
|
* necessary set is performed, after which the application
|
||||||
* supplied main() routine is called.
|
* supplied main() routine is called.
|
||||||
* @param None
|
* @param None
|
||||||
* @retval : None
|
* @retval : None
|
||||||
*/
|
*/
|
||||||
|
@ -71,7 +71,7 @@ defined in linker script */
|
||||||
.section .text.Reset_Handler
|
.section .text.Reset_Handler
|
||||||
.weak Reset_Handler
|
.weak Reset_Handler
|
||||||
.type Reset_Handler, %function
|
.type Reset_Handler, %function
|
||||||
Reset_Handler:
|
Reset_Handler:
|
||||||
ldr r0, =0x2001FFFC // mj666
|
ldr r0, =0x2001FFFC // mj666
|
||||||
ldr r1, =0xDEADBEEF // mj666
|
ldr r1, =0xDEADBEEF // mj666
|
||||||
ldr r2, [r0, #0] // mj666
|
ldr r2, [r0, #0] // mj666
|
||||||
|
@ -79,7 +79,7 @@ Reset_Handler:
|
||||||
cmp r2, r1 // mj666
|
cmp r2, r1 // mj666
|
||||||
beq Reboot_Loader // mj666
|
beq Reboot_Loader // mj666
|
||||||
|
|
||||||
/* Copy the data segment initializers from flash to SRAM */
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
movs r1, #0
|
movs r1, #0
|
||||||
b LoopCopyDataInit
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
@ -88,7 +88,7 @@ CopyDataInit:
|
||||||
ldr r3, [r3, r1]
|
ldr r3, [r3, r1]
|
||||||
str r3, [r0, r1]
|
str r3, [r0, r1]
|
||||||
adds r1, r1, #4
|
adds r1, r1, #4
|
||||||
|
|
||||||
LoopCopyDataInit:
|
LoopCopyDataInit:
|
||||||
ldr r0, =_sdata
|
ldr r0, =_sdata
|
||||||
ldr r3, =_edata
|
ldr r3, =_edata
|
||||||
|
@ -97,16 +97,29 @@ LoopCopyDataInit:
|
||||||
bcc CopyDataInit
|
bcc CopyDataInit
|
||||||
ldr r2, =_sbss
|
ldr r2, =_sbss
|
||||||
b LoopFillZerobss
|
b LoopFillZerobss
|
||||||
/* Zero fill the bss segment. */
|
/* Zero fill the bss segment. */
|
||||||
FillZerobss:
|
FillZerobss:
|
||||||
movs r3, #0
|
movs r3, #0
|
||||||
str r3, [r2], #4
|
str r3, [r2], #4
|
||||||
|
|
||||||
LoopFillZerobss:
|
LoopFillZerobss:
|
||||||
ldr r3, = _ebss
|
ldr r3, = _ebss
|
||||||
cmp r2, r3
|
cmp r2, r3
|
||||||
bcc FillZerobss
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Mark the heap and stack */
|
||||||
|
ldr r2, =_heap_stack_begin
|
||||||
|
b LoopMarkHeapStack
|
||||||
|
|
||||||
|
MarkHeapStack:
|
||||||
|
movs r3, 0xa5a5a5a5
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopMarkHeapStack:
|
||||||
|
ldr r3, = _heap_stack_end
|
||||||
|
cmp r2, r3
|
||||||
|
bcc MarkHeapStack
|
||||||
|
|
||||||
/*FPU settings*/
|
/*FPU settings*/
|
||||||
ldr r0, =0xE000ED88 /* Enable CP10,CP11 */
|
ldr r0, =0xE000ED88 /* Enable CP10,CP11 */
|
||||||
ldr r1,[r0]
|
ldr r1,[r0]
|
||||||
|
@ -114,11 +127,11 @@ LoopFillZerobss:
|
||||||
str r1,[r0]
|
str r1,[r0]
|
||||||
|
|
||||||
/* Call the clock system intitialization function.*/
|
/* Call the clock system intitialization function.*/
|
||||||
bl SystemInit
|
bl SystemInit
|
||||||
|
|
||||||
/* Call the application's entry point.*/
|
/* Call the application's entry point.*/
|
||||||
bl main
|
bl main
|
||||||
bx lr
|
bx lr
|
||||||
|
|
||||||
LoopForever:
|
LoopForever:
|
||||||
b LoopForever
|
b LoopForever
|
||||||
|
@ -134,11 +147,11 @@ Reboot_Loader: // mj666
|
||||||
.size Reset_Handler, .-Reset_Handler
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief This is the code that gets called when the processor receives an
|
* @brief This is the code that gets called when the processor receives an
|
||||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
* the system state for examination by a debugger.
|
* the system state for examination by a debugger.
|
||||||
* @param None
|
* @param None
|
||||||
* @retval None
|
* @retval None
|
||||||
*/
|
*/
|
||||||
.section .text.Default_Handler,"ax",%progbits
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
Default_Handler:
|
Default_Handler:
|
||||||
|
@ -150,7 +163,7 @@ Infinite_Loop:
|
||||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
* must be placed on this to ensure that it ends up at physical address
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
* 0x0000.0000.
|
* 0x0000.0000.
|
||||||
*
|
*
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
.section .irqstack,"aw",%progbits
|
.section .irqstack,"aw",%progbits
|
||||||
irq_stack:
|
irq_stack:
|
||||||
|
@ -159,8 +172,8 @@ Infinite_Loop:
|
||||||
.section .isr_vector,"a",%progbits
|
.section .isr_vector,"a",%progbits
|
||||||
.type g_pfnVectors, %object
|
.type g_pfnVectors, %object
|
||||||
.size g_pfnVectors, .-g_pfnVectors
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
g_pfnVectors:
|
g_pfnVectors:
|
||||||
.word irq_stack+1024
|
.word irq_stack+1024
|
||||||
.word Reset_Handler
|
.word Reset_Handler
|
||||||
|
@ -178,107 +191,107 @@ g_pfnVectors:
|
||||||
.word 0
|
.word 0
|
||||||
.word PendSV_Handler
|
.word PendSV_Handler
|
||||||
.word SysTick_Handler
|
.word SysTick_Handler
|
||||||
|
|
||||||
/* External Interrupts */
|
/* External Interrupts */
|
||||||
.word WWDG_IRQHandler /* Window WatchDog */
|
.word WWDG_IRQHandler /* Window WatchDog */
|
||||||
.word PVD_IRQHandler /* PVD through EXTI Line detection */
|
.word PVD_IRQHandler /* PVD through EXTI Line detection */
|
||||||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||||
.word FLASH_IRQHandler /* FLASH */
|
.word FLASH_IRQHandler /* FLASH */
|
||||||
.word RCC_IRQHandler /* RCC */
|
.word RCC_IRQHandler /* RCC */
|
||||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||||
.word CAN1_TX_IRQHandler /* CAN1 TX */
|
.word CAN1_TX_IRQHandler /* CAN1 TX */
|
||||||
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
|
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
|
||||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||||
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||||
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
||||||
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
||||||
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
.word TIM2_IRQHandler /* TIM2 */
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
.word TIM3_IRQHandler /* TIM3 */
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
.word TIM4_IRQHandler /* TIM4 */
|
.word TIM4_IRQHandler /* TIM4 */
|
||||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
.word SPI1_IRQHandler /* SPI1 */
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
.word SPI2_IRQHandler /* SPI2 */
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
.word USART1_IRQHandler /* USART1 */
|
.word USART1_IRQHandler /* USART1 */
|
||||||
.word USART2_IRQHandler /* USART2 */
|
.word USART2_IRQHandler /* USART2 */
|
||||||
.word USART3_IRQHandler /* USART3 */
|
.word USART3_IRQHandler /* USART3 */
|
||||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
||||||
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||||
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||||
.word FSMC_IRQHandler /* FSMC */
|
.word FSMC_IRQHandler /* FSMC */
|
||||||
.word SDIO_IRQHandler /* SDIO */
|
.word SDIO_IRQHandler /* SDIO */
|
||||||
.word TIM5_IRQHandler /* TIM5 */
|
.word TIM5_IRQHandler /* TIM5 */
|
||||||
.word SPI3_IRQHandler /* SPI3 */
|
.word SPI3_IRQHandler /* SPI3 */
|
||||||
.word UART4_IRQHandler /* UART4 */
|
.word UART4_IRQHandler /* UART4 */
|
||||||
.word UART5_IRQHandler /* UART5 */
|
.word UART5_IRQHandler /* UART5 */
|
||||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||||
.word TIM7_IRQHandler /* TIM7 */
|
.word TIM7_IRQHandler /* TIM7 */
|
||||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||||
.word ETH_IRQHandler /* Ethernet */
|
.word ETH_IRQHandler /* Ethernet */
|
||||||
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||||
.word CAN2_TX_IRQHandler /* CAN2 TX */
|
.word CAN2_TX_IRQHandler /* CAN2 TX */
|
||||||
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
||||||
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
||||||
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
|
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
|
||||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||||
.word USART6_IRQHandler /* USART6 */
|
.word USART6_IRQHandler /* USART6 */
|
||||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||||
.word DCMI_IRQHandler /* DCMI */
|
.word DCMI_IRQHandler /* DCMI */
|
||||||
.word CRYP_IRQHandler /* CRYP crypto */
|
.word CRYP_IRQHandler /* CRYP crypto */
|
||||||
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||||
.word FPU_IRQHandler /* FPU */
|
.word FPU_IRQHandler /* FPU */
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
*
|
*
|
||||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
* As they are weak aliases, any function with the same name will override
|
* As they are weak aliases, any function with the same name will override
|
||||||
* this definition.
|
* this definition.
|
||||||
*
|
*
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
.weak NMI_Handler
|
.weak NMI_Handler
|
||||||
.thumb_set NMI_Handler,Default_Handler
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
.weak HardFault_Handler
|
.weak HardFault_Handler
|
||||||
.thumb_set HardFault_Handler,Default_Handler
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
.weak MemManage_Handler
|
.weak MemManage_Handler
|
||||||
.thumb_set MemManage_Handler,Default_Handler
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
.weak BusFault_Handler
|
.weak BusFault_Handler
|
||||||
.thumb_set BusFault_Handler,Default_Handler
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
@ -295,252 +308,252 @@ g_pfnVectors:
|
||||||
.thumb_set PendSV_Handler,Default_Handler
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
.weak SysTick_Handler
|
.weak SysTick_Handler
|
||||||
.thumb_set SysTick_Handler,Default_Handler
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
.weak WWDG_IRQHandler
|
.weak WWDG_IRQHandler
|
||||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak PVD_IRQHandler
|
.weak PVD_IRQHandler
|
||||||
.thumb_set PVD_IRQHandler,Default_Handler
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TAMP_STAMP_IRQHandler
|
.weak TAMP_STAMP_IRQHandler
|
||||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak RTC_WKUP_IRQHandler
|
.weak RTC_WKUP_IRQHandler
|
||||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak FLASH_IRQHandler
|
.weak FLASH_IRQHandler
|
||||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak RCC_IRQHandler
|
.weak RCC_IRQHandler
|
||||||
.thumb_set RCC_IRQHandler,Default_Handler
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI0_IRQHandler
|
.weak EXTI0_IRQHandler
|
||||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI1_IRQHandler
|
.weak EXTI1_IRQHandler
|
||||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI2_IRQHandler
|
.weak EXTI2_IRQHandler
|
||||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI3_IRQHandler
|
.weak EXTI3_IRQHandler
|
||||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI4_IRQHandler
|
.weak EXTI4_IRQHandler
|
||||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA1_Stream0_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream1_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream2_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream3_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream4_IRQHandler
|
.weak DMA1_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream4_IRQHandler
|
||||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA1_Stream5_IRQHandler
|
.weak DMA1_Stream5_IRQHandler
|
||||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA1_Stream6_IRQHandler
|
.weak DMA1_Stream6_IRQHandler
|
||||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak ADC_IRQHandler
|
.weak ADC_IRQHandler
|
||||||
.thumb_set ADC_IRQHandler,Default_Handler
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak CAN1_TX_IRQHandler
|
.weak CAN1_TX_IRQHandler
|
||||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak CAN1_RX0_IRQHandler
|
.weak CAN1_RX0_IRQHandler
|
||||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak CAN1_RX1_IRQHandler
|
.weak CAN1_RX1_IRQHandler
|
||||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak CAN1_SCE_IRQHandler
|
.weak CAN1_SCE_IRQHandler
|
||||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI9_5_IRQHandler
|
.weak EXTI9_5_IRQHandler
|
||||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM1_BRK_TIM9_IRQHandler
|
.weak TIM1_BRK_TIM9_IRQHandler
|
||||||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM1_UP_TIM10_IRQHandler
|
.weak TIM1_UP_TIM10_IRQHandler
|
||||||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM1_CC_IRQHandler
|
.weak TIM1_CC_IRQHandler
|
||||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM2_IRQHandler
|
.weak TIM2_IRQHandler
|
||||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM3_IRQHandler
|
.weak TIM3_IRQHandler
|
||||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM4_IRQHandler
|
.weak TIM4_IRQHandler
|
||||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak I2C1_EV_IRQHandler
|
.weak I2C1_EV_IRQHandler
|
||||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak I2C1_ER_IRQHandler
|
.weak I2C1_ER_IRQHandler
|
||||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak I2C2_EV_IRQHandler
|
.weak I2C2_EV_IRQHandler
|
||||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak I2C2_ER_IRQHandler
|
.weak I2C2_ER_IRQHandler
|
||||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak SPI1_IRQHandler
|
.weak SPI1_IRQHandler
|
||||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak SPI2_IRQHandler
|
.weak SPI2_IRQHandler
|
||||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak USART1_IRQHandler
|
.weak USART1_IRQHandler
|
||||||
.thumb_set USART1_IRQHandler,Default_Handler
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak USART2_IRQHandler
|
.weak USART2_IRQHandler
|
||||||
.thumb_set USART2_IRQHandler,Default_Handler
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak USART3_IRQHandler
|
.weak USART3_IRQHandler
|
||||||
.thumb_set USART3_IRQHandler,Default_Handler
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI15_10_IRQHandler
|
.weak EXTI15_10_IRQHandler
|
||||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak RTC_Alarm_IRQHandler
|
.weak RTC_Alarm_IRQHandler
|
||||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak OTG_FS_WKUP_IRQHandler
|
.weak OTG_FS_WKUP_IRQHandler
|
||||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM8_BRK_TIM12_IRQHandler
|
.weak TIM8_BRK_TIM12_IRQHandler
|
||||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM8_UP_TIM13_IRQHandler
|
.weak TIM8_UP_TIM13_IRQHandler
|
||||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM8_CC_IRQHandler
|
.weak TIM8_CC_IRQHandler
|
||||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA1_Stream7_IRQHandler
|
.weak DMA1_Stream7_IRQHandler
|
||||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak FSMC_IRQHandler
|
.weak FSMC_IRQHandler
|
||||||
.thumb_set FSMC_IRQHandler,Default_Handler
|
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak SDIO_IRQHandler
|
.weak SDIO_IRQHandler
|
||||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM5_IRQHandler
|
.weak TIM5_IRQHandler
|
||||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak SPI3_IRQHandler
|
.weak SPI3_IRQHandler
|
||||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak UART4_IRQHandler
|
.weak UART4_IRQHandler
|
||||||
.thumb_set UART4_IRQHandler,Default_Handler
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak UART5_IRQHandler
|
.weak UART5_IRQHandler
|
||||||
.thumb_set UART5_IRQHandler,Default_Handler
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM6_DAC_IRQHandler
|
.weak TIM6_DAC_IRQHandler
|
||||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM7_IRQHandler
|
.weak TIM7_IRQHandler
|
||||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream0_IRQHandler
|
.weak DMA2_Stream0_IRQHandler
|
||||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream1_IRQHandler
|
.weak DMA2_Stream1_IRQHandler
|
||||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream2_IRQHandler
|
.weak DMA2_Stream2_IRQHandler
|
||||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream3_IRQHandler
|
.weak DMA2_Stream3_IRQHandler
|
||||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream4_IRQHandler
|
.weak DMA2_Stream4_IRQHandler
|
||||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak ETH_IRQHandler
|
.weak ETH_IRQHandler
|
||||||
.thumb_set ETH_IRQHandler,Default_Handler
|
.thumb_set ETH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak ETH_WKUP_IRQHandler
|
.weak ETH_WKUP_IRQHandler
|
||||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak CAN2_TX_IRQHandler
|
.weak CAN2_TX_IRQHandler
|
||||||
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak CAN2_RX0_IRQHandler
|
.weak CAN2_RX0_IRQHandler
|
||||||
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak CAN2_RX1_IRQHandler
|
.weak CAN2_RX1_IRQHandler
|
||||||
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak CAN2_SCE_IRQHandler
|
.weak CAN2_SCE_IRQHandler
|
||||||
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak OTG_FS_IRQHandler
|
.weak OTG_FS_IRQHandler
|
||||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream5_IRQHandler
|
.weak DMA2_Stream5_IRQHandler
|
||||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream6_IRQHandler
|
.weak DMA2_Stream6_IRQHandler
|
||||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream7_IRQHandler
|
.weak DMA2_Stream7_IRQHandler
|
||||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak USART6_IRQHandler
|
.weak USART6_IRQHandler
|
||||||
.thumb_set USART6_IRQHandler,Default_Handler
|
.thumb_set USART6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak I2C3_EV_IRQHandler
|
.weak I2C3_EV_IRQHandler
|
||||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak I2C3_ER_IRQHandler
|
.weak I2C3_ER_IRQHandler
|
||||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak OTG_HS_EP1_IN_IRQHandler
|
.weak OTG_HS_EP1_IN_IRQHandler
|
||||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak OTG_HS_WKUP_IRQHandler
|
.weak OTG_HS_WKUP_IRQHandler
|
||||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak OTG_HS_IRQHandler
|
.weak OTG_HS_IRQHandler
|
||||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DCMI_IRQHandler
|
.weak DCMI_IRQHandler
|
||||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak CRYP_IRQHandler
|
.weak CRYP_IRQHandler
|
||||||
.thumb_set CRYP_IRQHandler,Default_Handler
|
.thumb_set CRYP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak HASH_RNG_IRQHandler
|
.weak HASH_RNG_IRQHandler
|
||||||
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak FPU_IRQHandler
|
.weak FPU_IRQHandler
|
||||||
.thumb_set FPU_IRQHandler,Default_Handler
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
@ -36,7 +36,7 @@
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
.syntax unified
|
.syntax unified
|
||||||
.cpu cortex-m4
|
.cpu cortex-m4
|
||||||
.fpu softvfp
|
.fpu softvfp
|
||||||
|
@ -46,10 +46,10 @@
|
||||||
.global Default_Handler
|
.global Default_Handler
|
||||||
.global irq_stack
|
.global irq_stack
|
||||||
|
|
||||||
/* start address for the initialization values of the .data section.
|
/* start address for the initialization values of the .data section.
|
||||||
defined in linker script */
|
defined in linker script */
|
||||||
.word _sidata
|
.word _sidata
|
||||||
/* start address for the .data section. defined in linker script */
|
/* start address for the .data section. defined in linker script */
|
||||||
.word _sdata
|
.word _sdata
|
||||||
/* end address for the .data section. defined in linker script */
|
/* end address for the .data section. defined in linker script */
|
||||||
.word _edata
|
.word _edata
|
||||||
|
@ -63,7 +63,7 @@ defined in linker script */
|
||||||
* @brief This is the code that gets called when the processor first
|
* @brief This is the code that gets called when the processor first
|
||||||
* starts execution following a reset event. Only the absolutely
|
* starts execution following a reset event. Only the absolutely
|
||||||
* necessary set is performed, after which the application
|
* necessary set is performed, after which the application
|
||||||
* supplied main() routine is called.
|
* supplied main() routine is called.
|
||||||
* @param None
|
* @param None
|
||||||
* @retval : None
|
* @retval : None
|
||||||
*/
|
*/
|
||||||
|
@ -71,7 +71,7 @@ defined in linker script */
|
||||||
.section .text.Reset_Handler
|
.section .text.Reset_Handler
|
||||||
.weak Reset_Handler
|
.weak Reset_Handler
|
||||||
.type Reset_Handler, %function
|
.type Reset_Handler, %function
|
||||||
Reset_Handler:
|
Reset_Handler:
|
||||||
ldr r0, =0x2001FFFC // mj666
|
ldr r0, =0x2001FFFC // mj666
|
||||||
ldr r1, =0xDEADBEEF // mj666
|
ldr r1, =0xDEADBEEF // mj666
|
||||||
ldr r2, [r0, #0] // mj666
|
ldr r2, [r0, #0] // mj666
|
||||||
|
@ -79,7 +79,7 @@ Reset_Handler:
|
||||||
cmp r2, r1 // mj666
|
cmp r2, r1 // mj666
|
||||||
beq Reboot_Loader // mj666
|
beq Reboot_Loader // mj666
|
||||||
|
|
||||||
/* Copy the data segment initializers from flash to SRAM */
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
movs r1, #0
|
movs r1, #0
|
||||||
b LoopCopyDataInit
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
@ -88,7 +88,7 @@ CopyDataInit:
|
||||||
ldr r3, [r3, r1]
|
ldr r3, [r3, r1]
|
||||||
str r3, [r0, r1]
|
str r3, [r0, r1]
|
||||||
adds r1, r1, #4
|
adds r1, r1, #4
|
||||||
|
|
||||||
LoopCopyDataInit:
|
LoopCopyDataInit:
|
||||||
ldr r0, =_sdata
|
ldr r0, =_sdata
|
||||||
ldr r3, =_edata
|
ldr r3, =_edata
|
||||||
|
@ -97,16 +97,29 @@ LoopCopyDataInit:
|
||||||
bcc CopyDataInit
|
bcc CopyDataInit
|
||||||
ldr r2, =_sbss
|
ldr r2, =_sbss
|
||||||
b LoopFillZerobss
|
b LoopFillZerobss
|
||||||
/* Zero fill the bss segment. */
|
/* Zero fill the bss segment. */
|
||||||
FillZerobss:
|
FillZerobss:
|
||||||
movs r3, #0
|
movs r3, #0
|
||||||
str r3, [r2], #4
|
str r3, [r2], #4
|
||||||
|
|
||||||
LoopFillZerobss:
|
LoopFillZerobss:
|
||||||
ldr r3, = _ebss
|
ldr r3, = _ebss
|
||||||
cmp r2, r3
|
cmp r2, r3
|
||||||
bcc FillZerobss
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Mark the heap and stack */
|
||||||
|
ldr r2, =_heap_stack_begin
|
||||||
|
b LoopMarkHeapStack
|
||||||
|
|
||||||
|
MarkHeapStack:
|
||||||
|
movs r3, 0xa5a5a5a5
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopMarkHeapStack:
|
||||||
|
ldr r3, = _heap_stack_end
|
||||||
|
cmp r2, r3
|
||||||
|
bcc MarkHeapStack
|
||||||
|
|
||||||
/*FPU settings*/
|
/*FPU settings*/
|
||||||
ldr r0, =0xE000ED88 /* Enable CP10,CP11 */
|
ldr r0, =0xE000ED88 /* Enable CP10,CP11 */
|
||||||
ldr r1,[r0]
|
ldr r1,[r0]
|
||||||
|
@ -114,11 +127,11 @@ LoopFillZerobss:
|
||||||
str r1,[r0]
|
str r1,[r0]
|
||||||
|
|
||||||
/* Call the clock system intitialization function.*/
|
/* Call the clock system intitialization function.*/
|
||||||
bl SystemInit
|
bl SystemInit
|
||||||
|
|
||||||
/* Call the application's entry point.*/
|
/* Call the application's entry point.*/
|
||||||
bl main
|
bl main
|
||||||
bx lr
|
bx lr
|
||||||
|
|
||||||
LoopForever:
|
LoopForever:
|
||||||
b LoopForever
|
b LoopForever
|
||||||
|
@ -133,11 +146,11 @@ Reboot_Loader: // mj666
|
||||||
.size Reset_Handler, .-Reset_Handler
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief This is the code that gets called when the processor receives an
|
* @brief This is the code that gets called when the processor receives an
|
||||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
* the system state for examination by a debugger.
|
* the system state for examination by a debugger.
|
||||||
* @param None
|
* @param None
|
||||||
* @retval None
|
* @retval None
|
||||||
*/
|
*/
|
||||||
.section .text.Default_Handler,"ax",%progbits
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
Default_Handler:
|
Default_Handler:
|
||||||
|
@ -149,7 +162,7 @@ Infinite_Loop:
|
||||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
* must be placed on this to ensure that it ends up at physical address
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
* 0x0000.0000.
|
* 0x0000.0000.
|
||||||
*
|
*
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
.section .irqstack,"aw",%progbits
|
.section .irqstack,"aw",%progbits
|
||||||
irq_stack:
|
irq_stack:
|
||||||
|
@ -158,7 +171,7 @@ Infinite_Loop:
|
||||||
.section .isr_vector,"a",%progbits
|
.section .isr_vector,"a",%progbits
|
||||||
.type g_pfnVectors, %object
|
.type g_pfnVectors, %object
|
||||||
.size g_pfnVectors, .-g_pfnVectors
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
g_pfnVectors:
|
g_pfnVectors:
|
||||||
.word irq_stack+1024
|
.word irq_stack+1024
|
||||||
|
@ -177,82 +190,82 @@ g_pfnVectors:
|
||||||
.word 0
|
.word 0
|
||||||
.word PendSV_Handler
|
.word PendSV_Handler
|
||||||
.word SysTick_Handler
|
.word SysTick_Handler
|
||||||
|
|
||||||
/* External Interrupts */
|
/* External Interrupts */
|
||||||
.word WWDG_IRQHandler /* Window WatchDog */
|
.word WWDG_IRQHandler /* Window WatchDog */
|
||||||
.word PVD_IRQHandler /* PVD through EXTI Line detection */
|
.word PVD_IRQHandler /* PVD through EXTI Line detection */
|
||||||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||||
.word FLASH_IRQHandler /* FLASH */
|
.word FLASH_IRQHandler /* FLASH */
|
||||||
.word RCC_IRQHandler /* RCC */
|
.word RCC_IRQHandler /* RCC */
|
||||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||||
.word 0 /* CAN1 TX */
|
.word 0 /* CAN1 TX */
|
||||||
.word 0 /* CAN1 RX0 */
|
.word 0 /* CAN1 RX0 */
|
||||||
.word 0 /* CAN1 RX1 */
|
.word 0 /* CAN1 RX1 */
|
||||||
.word 0 /* CAN1 SCE */
|
.word 0 /* CAN1 SCE */
|
||||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||||
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
||||||
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
||||||
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
.word TIM2_IRQHandler /* TIM2 */
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
.word TIM3_IRQHandler /* TIM3 */
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
.word TIM4_IRQHandler /* TIM4 */
|
.word TIM4_IRQHandler /* TIM4 */
|
||||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
.word SPI1_IRQHandler /* SPI1 */
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
.word SPI2_IRQHandler /* SPI2 */
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
.word USART1_IRQHandler /* USART1 */
|
.word USART1_IRQHandler /* USART1 */
|
||||||
.word USART2_IRQHandler /* USART2 */
|
.word USART2_IRQHandler /* USART2 */
|
||||||
.word 0 /* USART3 */
|
.word 0 /* USART3 */
|
||||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
||||||
.word 0 /* TIM8 Break and TIM12 */
|
.word 0 /* TIM8 Break and TIM12 */
|
||||||
.word 0 /* TIM8 Update and TIM13 */
|
.word 0 /* TIM8 Update and TIM13 */
|
||||||
.word 0 /* TIM8 Trigger and Commutation and TIM14 */
|
.word 0 /* TIM8 Trigger and Commutation and TIM14 */
|
||||||
.word 0 /* TIM8 Capture Compare */
|
.word 0 /* TIM8 Capture Compare */
|
||||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||||
.word 0 /* FSMC */
|
.word 0 /* FSMC */
|
||||||
.word SDIO_IRQHandler /* SDIO */
|
.word SDIO_IRQHandler /* SDIO */
|
||||||
.word TIM5_IRQHandler /* TIM5 */
|
.word TIM5_IRQHandler /* TIM5 */
|
||||||
.word SPI3_IRQHandler /* SPI3 */
|
.word SPI3_IRQHandler /* SPI3 */
|
||||||
.word 0 /* UART4 */
|
.word 0 /* UART4 */
|
||||||
.word 0 /* UART5 */
|
.word 0 /* UART5 */
|
||||||
.word 0 /* TIM6 and DAC1&2 underrun errors */
|
.word 0 /* TIM6 and DAC1&2 underrun errors */
|
||||||
.word 0 /* TIM7 */
|
.word 0 /* TIM7 */
|
||||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||||
.word 0 /* Ethernet */
|
.word 0 /* Ethernet */
|
||||||
.word 0 /* Ethernet Wakeup through EXTI line */
|
.word 0 /* Ethernet Wakeup through EXTI line */
|
||||||
.word 0 /* CAN2 TX */
|
.word 0 /* CAN2 TX */
|
||||||
.word 0 /* CAN2 RX0 */
|
.word 0 /* CAN2 RX0 */
|
||||||
.word 0 /* CAN2 RX1 */
|
.word 0 /* CAN2 RX1 */
|
||||||
.word 0 /* CAN2 SCE */
|
.word 0 /* CAN2 SCE */
|
||||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||||
.word USART6_IRQHandler /* USART6 */
|
.word USART6_IRQHandler /* USART6 */
|
||||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||||
.word 0 /* USB OTG HS End Point 1 Out */
|
.word 0 /* USB OTG HS End Point 1 Out */
|
||||||
.word 0 /* USB OTG HS End Point 1 In */
|
.word 0 /* USB OTG HS End Point 1 In */
|
||||||
.word 0 /* USB OTG HS Wakeup through EXTI */
|
.word 0 /* USB OTG HS Wakeup through EXTI */
|
||||||
|
@ -267,20 +280,20 @@ g_pfnVectors:
|
||||||
.word SPI5_IRQHandler /* SPI5 */
|
.word SPI5_IRQHandler /* SPI5 */
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
*
|
*
|
||||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
* As they are weak aliases, any function with the same name will override
|
* As they are weak aliases, any function with the same name will override
|
||||||
* this definition.
|
* this definition.
|
||||||
*
|
*
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
.weak NMI_Handler
|
.weak NMI_Handler
|
||||||
.thumb_set NMI_Handler,Default_Handler
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
.weak HardFault_Handler
|
.weak HardFault_Handler
|
||||||
.thumb_set HardFault_Handler,Default_Handler
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
.weak MemManage_Handler
|
.weak MemManage_Handler
|
||||||
.thumb_set MemManage_Handler,Default_Handler
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
.weak BusFault_Handler
|
.weak BusFault_Handler
|
||||||
.thumb_set BusFault_Handler,Default_Handler
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
@ -297,172 +310,172 @@ g_pfnVectors:
|
||||||
.thumb_set PendSV_Handler,Default_Handler
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
.weak SysTick_Handler
|
.weak SysTick_Handler
|
||||||
.thumb_set SysTick_Handler,Default_Handler
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
.weak WWDG_IRQHandler
|
.weak WWDG_IRQHandler
|
||||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak PVD_IRQHandler
|
.weak PVD_IRQHandler
|
||||||
.thumb_set PVD_IRQHandler,Default_Handler
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TAMP_STAMP_IRQHandler
|
.weak TAMP_STAMP_IRQHandler
|
||||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak RTC_WKUP_IRQHandler
|
.weak RTC_WKUP_IRQHandler
|
||||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak FLASH_IRQHandler
|
.weak FLASH_IRQHandler
|
||||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak RCC_IRQHandler
|
.weak RCC_IRQHandler
|
||||||
.thumb_set RCC_IRQHandler,Default_Handler
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI0_IRQHandler
|
.weak EXTI0_IRQHandler
|
||||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI1_IRQHandler
|
.weak EXTI1_IRQHandler
|
||||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI2_IRQHandler
|
.weak EXTI2_IRQHandler
|
||||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI3_IRQHandler
|
.weak EXTI3_IRQHandler
|
||||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI4_IRQHandler
|
.weak EXTI4_IRQHandler
|
||||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA1_Stream0_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream1_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream2_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream3_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream4_IRQHandler
|
.weak DMA1_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream4_IRQHandler
|
||||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA1_Stream5_IRQHandler
|
.weak DMA1_Stream5_IRQHandler
|
||||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA1_Stream6_IRQHandler
|
.weak DMA1_Stream6_IRQHandler
|
||||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak ADC_IRQHandler
|
.weak ADC_IRQHandler
|
||||||
.thumb_set ADC_IRQHandler,Default_Handler
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI9_5_IRQHandler
|
.weak EXTI9_5_IRQHandler
|
||||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM1_BRK_TIM9_IRQHandler
|
.weak TIM1_BRK_TIM9_IRQHandler
|
||||||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM1_UP_TIM10_IRQHandler
|
.weak TIM1_UP_TIM10_IRQHandler
|
||||||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM1_CC_IRQHandler
|
.weak TIM1_CC_IRQHandler
|
||||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM2_IRQHandler
|
.weak TIM2_IRQHandler
|
||||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM3_IRQHandler
|
.weak TIM3_IRQHandler
|
||||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM4_IRQHandler
|
.weak TIM4_IRQHandler
|
||||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak I2C1_EV_IRQHandler
|
.weak I2C1_EV_IRQHandler
|
||||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak I2C1_ER_IRQHandler
|
.weak I2C1_ER_IRQHandler
|
||||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak I2C2_EV_IRQHandler
|
.weak I2C2_EV_IRQHandler
|
||||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak I2C2_ER_IRQHandler
|
.weak I2C2_ER_IRQHandler
|
||||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak SPI1_IRQHandler
|
.weak SPI1_IRQHandler
|
||||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak SPI2_IRQHandler
|
.weak SPI2_IRQHandler
|
||||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak USART1_IRQHandler
|
.weak USART1_IRQHandler
|
||||||
.thumb_set USART1_IRQHandler,Default_Handler
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak USART2_IRQHandler
|
.weak USART2_IRQHandler
|
||||||
.thumb_set USART2_IRQHandler,Default_Handler
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak EXTI15_10_IRQHandler
|
.weak EXTI15_10_IRQHandler
|
||||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak RTC_Alarm_IRQHandler
|
.weak RTC_Alarm_IRQHandler
|
||||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak OTG_FS_WKUP_IRQHandler
|
.weak OTG_FS_WKUP_IRQHandler
|
||||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA1_Stream7_IRQHandler
|
.weak DMA1_Stream7_IRQHandler
|
||||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak SDIO_IRQHandler
|
.weak SDIO_IRQHandler
|
||||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM5_IRQHandler
|
.weak TIM5_IRQHandler
|
||||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak SPI3_IRQHandler
|
.weak SPI3_IRQHandler
|
||||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream0_IRQHandler
|
.weak DMA2_Stream0_IRQHandler
|
||||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream1_IRQHandler
|
.weak DMA2_Stream1_IRQHandler
|
||||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream2_IRQHandler
|
.weak DMA2_Stream2_IRQHandler
|
||||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream3_IRQHandler
|
.weak DMA2_Stream3_IRQHandler
|
||||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream4_IRQHandler
|
.weak DMA2_Stream4_IRQHandler
|
||||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak OTG_FS_IRQHandler
|
.weak OTG_FS_IRQHandler
|
||||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream5_IRQHandler
|
.weak DMA2_Stream5_IRQHandler
|
||||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream6_IRQHandler
|
.weak DMA2_Stream6_IRQHandler
|
||||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA2_Stream7_IRQHandler
|
.weak DMA2_Stream7_IRQHandler
|
||||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak USART6_IRQHandler
|
.weak USART6_IRQHandler
|
||||||
.thumb_set USART6_IRQHandler,Default_Handler
|
.thumb_set USART6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak I2C3_EV_IRQHandler
|
.weak I2C3_EV_IRQHandler
|
||||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak I2C3_ER_IRQHandler
|
.weak I2C3_ER_IRQHandler
|
||||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak FPU_IRQHandler
|
.weak FPU_IRQHandler
|
||||||
.thumb_set FPU_IRQHandler,Default_Handler
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak SPI4_IRQHandler
|
.weak SPI4_IRQHandler
|
||||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue