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Code Issues Wiki Activity

Drop F3 codebase

Browse source
This commit is contained in:
Pawel Spychalski (DzikuVx) 2022-05-26 19:56:59 +02:00
parent 2c8a25d67a
commit 9983f99d03
298 changed files with 23 additions and 310056 deletions
Download patch file Download diff file Expand all files Collapse all files

1
cmake/stm32.cmake
View file

@ -1,5 +1,4 @@
include(stm32-bootloader)
include(stm32f3)
include(stm32f4)
include(stm32f7)
include(stm32h7)

16
cmake/stm32f3-usb.cmake
View file

@ -1,16 +0,0 @@
set(STM32_USBFS_DIR "${MAIN_LIB_DIR}/main/STM32_USB-FS-Device_Driver")
set(STM32_USBFS_SRC
usb_core.c
usb_init.c
usb_int.c
usb_mem.c
usb_regs.c
usb_sil.c
)
list(TRANSFORM STM32_USBFS_SRC PREPEND "${STM32_USBFS_DIR}/src/")
set(STM32F3_USB_INCLUDE_DIRS
${STM32_USBFS_DIR}/inc
)
set(STM32F3_USB_SRC ${STM32_USBFS_SRC})

97
cmake/stm32f3.cmake
View file

@ -1,97 +0,0 @@
include(cortex-m4f)
include(stm32-stdperiph)
include(stm32f3-usb)
set(STM32F3_STDPERIPH_DIR "${MAIN_LIB_DIR}/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver")
set(STM32F3_CMSIS_DEVICE_DIR "${MAIN_LIB_DIR}/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x")
set(STM32F3_CMSIS_DRIVERS_DIR "${MAIN_LIB_DIR}/main/STM32F3/Drivers/CMSIS")
set(STM32F3_VCP_DIR "${MAIN_SRC_DIR}/vcp")
set(STM32F3_STDPERIPH_SRC_EXCLUDES
stm32f30x_crc.c
stm32f30x_can.c
)
set(STM32F3_STDPERIPH_SRC_DIR "${STM32F3_STDPERIPH_DIR}/src")
glob_except(STM32F3_STDPERIPH_SRC "${STM32F3_STDPERIPH_SRC_DIR}/*.c" "${STM32F3_STDPERIPH_SRC_EXCLUDES}")
main_sources(STM32F3_SRC
target/system_stm32f30x.c
config/config_streamer_stm32f3.c
config/config_streamer_ram.c
config/config_streamer_extflash.c
drivers/adc_stm32f30x.c
drivers/bus_i2c_stm32f30x.c
drivers/dma_stm32f3xx.c
drivers/serial_uart_stm32f30x.c
drivers/system_stm32f30x.c
drivers/timer_impl_stdperiph.c
drivers/timer_stm32f30x.c
)
set(STM32F3_VCP_SRC
hw_config.c
stm32_it.c
usb_desc.c
usb_endp.c
usb_istr.c
usb_prop.c
usb_pwr.c
)
list(TRANSFORM STM32F3_VCP_SRC PREPEND "${STM32F3_VCP_DIR}/")
set(STM32F3_INCLUDE_DIRS
"${CMSIS_INCLUDE_DIR}"
"${CMSIS_DSP_INCLUDE_DIR}"
"${STM32F3_STDPERIPH_DIR}/inc"
"${STM32F3_CMSIS_DEVICE_DIR}"
"${STM32F3_CMSIS_DRIVERS_DIR}"
"${STM32F3_VCP_DIR}"
)
set(STM32F3_DEFINITIONS
${CORTEX_M4F_DEFINITIONS}
STM32F3
USE_STDPERIPH_DRIVER
)
set(STM32F303CC_DEFINITIONS
STM32F303
STM32F303xC
MCU_FLASH_SIZE=256
)
function(target_stm32f3xx)
# F3 targets don't support MSC and use -Os instead of -O2 to save size
target_stm32(
SOURCES ${STM32_STDPERIPH_SRC} ${STM32F3_STDPERIPH_SRC} ${STM32F3_SRC}
COMPILE_DEFINITIONS ${STM32F3_DEFINITIONS}
COMPILE_OPTIONS ${CORTEX_M4F_COMMON_OPTIONS} ${CORTEX_M4F_COMPILE_OPTIONS}
INCLUDE_DIRECTORIES ${STM32F3_INCLUDE_DIRS}
LINK_OPTIONS ${CORTEX_M4F_COMMON_OPTIONS} ${CORTEX_M4F_LINK_OPTIONS}
VCP_SOURCES ${STM32F3_USB_SRC} ${STM32F3_VCP_SRC}
VCP_INCLUDE_DIRECTORIES ${STM32F3_USB_INCLUDE_DIRS}
DISABLE_MSC
OPTIMIZATION -Os
OPENOCD_TARGET stm32f3x
${ARGN}
)
endfunction()
function(target_stm32f303xc name)
target_stm32f3xx(
NAME ${name}
STARTUP startup_stm32f30x_md_gcc.S
COMPILE_DEFINITIONS ${STM32F303CC_DEFINITIONS}
LINKER_SCRIPT stm32_flash_f303xc
SVD STM32F303
${ARGN}
)
endfunction()

40381
dev/svd/STM32F303.svd
View file

File diff suppressed because it is too large Load diff

1
docs/boards/AlienFlight.md
View file

@ -21,7 +21,6 @@ https://micro-motor-warehouse.com
Here are the general hardware specifications for this boards:
- STM32F303CCT6 MCU (ALIENFLIGHTF3)
- STM32F405RGT6 MCU (ALIENFLIGHTF4)
- STM32F711RET6 MCU (ALIENFLIGHTNGF7)
- MPU6050/6500/9250/ICM-20602 accelerometer/gyro(/mag) sensor unit

1
docs/development/Cmake usage.md
View file

@ -26,7 +26,6 @@ target_stm32f405xg(QUARKVISION HSE_MHZ 16)
As of inav 4.1, the following target hardware platforms are recognised:
* stm32f303xc
* stm32f405xg
* stm32f411xe
* stm32f427xg

1
fake_travis_build.sh
View file

@ -8,7 +8,6 @@ targets=("PUBLISHMETA=True" \
"TARGET=MOTOLAB" \
"TARGET=RMDO" \
"TARGET=SPARKY" \
"TARGET=STM32F3DISCOVERY" \
"TARGET=RCEXPLORERF3" )
#fake a travis build environment
export TRAVIS_BUILD_NUMBER=$(date +%s)

422
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/TrueSTUDIO/startup_stm32f302x8.s
View file

@ -1,422 +0,0 @@
/**
******************************************************************************
* @file startup_stm32f302x8.s
* @author MCD Application Team
* @version V1.1.1
* @date 28-March-2014
* @brief stm32f30x vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TS_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word 0
.word 0
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word 0
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SPI3_IRQHandler
.word 0
.word 0
.word TIM6_DAC_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word COMP2_IRQHandler
.word COMP4_6_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word USBWakeUp_RMP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_IRQHandler
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TS_IRQHandler
.thumb_set EXTI2_TS_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak COMP2_IRQHandler
.thumb_set COMP2_IRQHandler,Default_Handler
.weak COMP4_6_IRQHandler
.thumb_set COMP4_6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak USBWakeUp_RMP_IRQHandler
.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

469
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/TrueSTUDIO/startup_stm32f303xc.s
View file

@ -1,469 +0,0 @@
/**
******************************************************************************
* @file startup_stm32f303xC.s
* @author MCD Application Team
* @version V1.1.1
* @date 28-March-2014
* @brief stm32f30x vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TS_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word 0
.word 0
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ADC4_IRQHandler
.word 0
.word 0
.word COMP1_2_3_IRQHandler
.word COMP4_5_6_IRQHandler
.word COMP7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word USBWakeUp_RMP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_IRQHandler
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TS_IRQHandler
.thumb_set EXTI2_TS_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ADC4_IRQHandler
.thumb_set ADC4_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_5_6_IRQHandler
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
.weak COMP7_IRQHandler
.thumb_set COMP7_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak USBWakeUp_RMP_IRQHandler
.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

469
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/TrueSTUDIO/startup_stm32f30x.s
View file

@ -1,469 +0,0 @@
/**
******************************************************************************
* @file startup_stm32f30x.s
* @author MCD Application Team
* @version V1.1.1
* @date 28-March-2014
* @brief stm32f30x vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TS_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word 0
.word 0
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ADC4_IRQHandler
.word 0
.word 0
.word COMP1_2_3_IRQHandler
.word COMP4_5_6_IRQHandler
.word COMP7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word USBWakeUp_RMP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_IRQHandler
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TS_IRQHandler
.thumb_set EXTI2_TS_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ADC4_IRQHandler
.thumb_set ADC4_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_5_6_IRQHandler
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
.weak COMP7_IRQHandler
.thumb_set COMP7_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak USBWakeUp_RMP_IRQHandler
.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

420
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/TrueSTUDIO/startup_stm32f334x8.s
View file

@ -1,420 +0,0 @@
/**
******************************************************************************
* @file startup_stm32f334x8.s
* @author MCD Application Team
* @version V1.1.1
* @date 28-March-2014
* @brief stm32f30x vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TS_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word 0
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word 0
.word 0
.word SPI1_IRQHandler
.word 0
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word TIM6_DAC1_IRQHandler
.word TIM7_DAC2_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word COMP2_IRQHandler
.word COMP4_6_IRQHandler
.word 0
.word HRTIM1_Master_IRQHandler
.word HRTIM1_TIMA_IRQHandler
.word HRTIM1_TIMB_IRQHandler
.word HRTIM1_TIMC_IRQHandler
.word HRTIM1_TIMD_IRQHandler
.word HRTIM1_TIME_IRQHandler
.word HRTIM1_FLT_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_IRQHandler
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TS_IRQHandler
.thumb_set EXTI2_TS_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM6_DAC1_IRQHandler
.thumb_set TIM6_DAC1_IRQHandler,Default_Handler
.weak TIM7_DAC2_IRQHandler
.thumb_set TIM7_DAC2_IRQHandler,Default_Handler
.weak COMP2_IRQHandler
.thumb_set COMP2_IRQHandler,Default_Handler
.weak COMP4_6_IRQHandler
.thumb_set COMP4_6_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

367
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/arm/startup_stm32f302x8.s
View file

@ -1,367 +0,0 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f302x8.s
;* Author : MCD Application Team
;* Version : V1.1.1
;* Date : 28-March-2014
;* Description : STM32F302x8 devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD 0 ; Reserved
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP2_IRQHandler ; COMP2
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_TS_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT COMP2_IRQHandler [WEAK]
EXPORT COMP4_6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_TS_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
SPI3_IRQHandler
TIM6_DAC_IRQHandler
COMP2_IRQHandler
COMP4_6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
USBWakeUp_RMP_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

399
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/arm/startup_stm32f303xc.s
View file

@ -1,399 +0,0 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f303xc.s
;* Author : MCD Application Team
;* Version : V1.1.1
;* Date : 28-March-2014
;* Description : STM32F303xC devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_TS_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ADC4_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_5_6_IRQHandler [WEAK]
EXPORT COMP7_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_TS_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ADC4_IRQHandler
COMP1_2_3_IRQHandler
COMP4_5_6_IRQHandler
COMP7_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
USBWakeUp_RMP_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

399
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/arm/startup_stm32f30x.s
View file

@ -1,399 +0,0 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f30x.s
;* Author : MCD Application Team
;* Version : V1.1.1
;* Date : 28-March-2014
;* Description : STM32F30x devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_TS_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ADC4_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_5_6_IRQHandler [WEAK]
EXPORT COMP7_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_TS_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ADC4_IRQHandler
COMP1_2_3_IRQHandler
COMP4_5_6_IRQHandler
COMP7_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
USBWakeUp_RMP_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

368
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/arm/startup_stm32f334x8.s
View file

@ -1,368 +0,0 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f334x8.s
;* Author : MCD Application Team
;* Version : V1.1.1
;* Date : 28-March-2014
;* Description : STM32F334 devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1 and EXTI Line 25
DCD USART2_IRQHandler ; USART2 and EXTI Line 26
DCD USART3_IRQHandler ; USART3 and EXTI Line 28
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP2_IRQHandler ; COMP2
DCD COMP4_6_IRQHandler ; COMP4, COMP6
DCD 0 ; Reserved
DCD HRTIM1_Master_IRQHandler ; HRTIM1 master timer
DCD HRTIM1_TIMA_IRQHandler ; Reserved
DCD HRTIM1_TIMB_IRQHandler ; Reserved
DCD HRTIM1_TIMC_IRQHandler ; Reserved
DCD HRTIM1_TIMD_IRQHandler ; Reserved
DCD HRTIM1_TIME_IRQHandler ; Reserved
DCD HRTIM1_FLT_IRQHandler ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_TS_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIM6_DAC1_IRQHandler [WEAK]
EXPORT TIM7_DAC2_IRQHandler [WEAK]
EXPORT COMP2_IRQHandler [WEAK]
EXPORT COMP4_6_IRQHandler [WEAK]
EXPORT HRTIM1_Master_IRQHandler [WEAK]
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_TS_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
TIM6_DAC1_IRQHandler
TIM7_DAC2_IRQHandler
COMP2_IRQHandler
COMP4_6_IRQHandler
HRTIM1_Master_IRQHandler
HRTIM1_TIMA_IRQHandler
HRTIM1_TIMB_IRQHandler
HRTIM1_TIMC_IRQHandler
HRTIM1_TIMD_IRQHandler
HRTIM1_TIME_IRQHandler
HRTIM1_FLT_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

465
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/gcc_ride7/startup_stm32f30x.s
View file

@ -1,465 +0,0 @@
/**
******************************************************************************
* @file startup_stm32f30x.s
* @author MCD Application Team
* @version V1.1.1
* @date 28-March-2014
* @brief STM32F30x Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system and the external SRAM mounted on
* STM3230C-EVAL board to be used as data memory (optional,
* to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TS_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word 0
.word 0
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ADC4_IRQHandler
.word 0
.word 0
.word COMP1_2_3_IRQHandler
.word COMP4_5_6_IRQHandler
.word COMP7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word USBWakeUp_RMP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_IRQHandler
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TS_IRQHandler
.thumb_set EXTI2_TS_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ADC4_IRQHandler
.thumb_set ADC4_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_5_6_IRQHandler
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
.weak COMP7_IRQHandler
.thumb_set COMP7_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak USBWakeUp_RMP_IRQHandler
.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

473
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/iar/startup_stm32f302x8.s
View file

@ -1,473 +0,0 @@
;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f302x8.s
;* Author : MCD Application Team
;* Version : V1.1.1
;* Date : 28-March-2014
;* Description : STM32F302x8 devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
;* You may not use this file except in compliance with the License.
;* You may obtain a copy of the License at:
;*
;* http://www.st.com/software_license_agreement_liberty_v2
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD 0 ; Reserved
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP2_IRQHandler ; COMP2
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_STAMP_IRQHandler
B TAMPER_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_TS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_TS_IRQHandler
B EXTI2_TS_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK COMP2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP2_IRQHandler
B COMP2_IRQHandler
PUBWEAK COMP4_6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP4_6_IRQHandler
B COMP4_6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK USBWakeUp_RMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_RMP_IRQHandler
B USBWakeUp_RMP_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

554
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/iar/startup_stm32f303xc.s
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@ -1,554 +0,0 @@
;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f303xc.s
;* Author : MCD Application Team
;* Version : V1.1.1
;* Date : 28-March-2014
;* Description : STM32F303xC devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
;* You may not use this file except in compliance with the License.
;* You may obtain a copy of the License at:
;*
;* http://www.st.com/software_license_agreement_liberty_v2
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_STAMP_IRQHandler
B TAMPER_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_TS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_TS_IRQHandler
B EXTI2_TS_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ADC4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC4_IRQHandler
B ADC4_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_5_6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP4_5_6_IRQHandler
B COMP4_5_6_IRQHandler
PUBWEAK COMP7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP7_IRQHandler
B COMP7_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK USBWakeUp_RMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_RMP_IRQHandler
B USBWakeUp_RMP_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

554
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/iar/startup_stm32f30x.s
View file

@ -1,554 +0,0 @@
;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f30x.s
;* Author : MCD Application Team
;* Version : V1.1.1
;* Date : 28-March-2014
;* Description : STM32F30x devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
;* You may not use this file except in compliance with the License.
;* You may obtain a copy of the License at:
;*
;* http://www.st.com/software_license_agreement_liberty_v2
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_STAMP_IRQHandler
B TAMPER_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_TS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_TS_IRQHandler
B EXTI2_TS_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ADC4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC4_IRQHandler
B ADC4_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_5_6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP4_5_6_IRQHandler
B COMP4_5_6_IRQHandler
PUBWEAK COMP7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP7_IRQHandler
B COMP7_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK USBWakeUp_RMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_RMP_IRQHandler
B USBWakeUp_RMP_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

474
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/startup/iar/startup_stm32f334x8.s
View file

@ -1,474 +0,0 @@
;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f334x8.s
;* Author : MCD Application Team
;* Version : V1.1.1
;* Date : 28-March-2014
;* Description : STM32F334x8 devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
;* You may not use this file except in compliance with the License.
;* You may obtain a copy of the License at:
;*
;* http://www.st.com/software_license_agreement_liberty_v2
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event through EXTI Line 23
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1 through EXTI Line 25
DCD USART2_IRQHandler ; USART2 through EXTI Line 26
DCD USART3_IRQHandler ; USART3 through EXTI Line 28
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP2_IRQHandler ; COMP2
DCD COMP4_6_IRQHandler ; COMP4, COMP6
DCD 0 ; Reserved
DCD HRTIM1_Master_IRQHandler ; HRTIM1 master timer
DCD HRTIM1_TIMA_IRQHandler ; HRTIM1 timer A
DCD HRTIM1_TIMB_IRQHandler ; HRTIM1 timer B
DCD HRTIM1_TIMC_IRQHandler ; HRTIM1 timer C
DCD HRTIM1_TIMD_IRQHandler ; HRTIM1 timer D
DCD HRTIM1_TIME_IRQHandler ; HRTIM1 timer E
DCD HRTIM1_FLT_IRQHandler ; HRTIM1 fault
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_STAMP_IRQHandler
B TAMPER_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_TS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_TS_IRQHandler
B EXTI2_TS_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK TIM6_DAC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC1_IRQHandler
B TIM6_DAC1_IRQHandler
PUBWEAK TIM7_DAC2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_DAC2_IRQHandler
B TIM7_DAC2_IRQHandler
PUBWEAK COMP2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP2_IRQHandler
B COMP2_IRQHandler
PUBWEAK COMP4_6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP4_6_IRQHandler
B COMP4_6_IRQHandler
PUBWEAK HRTIM1_Master_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_Master_IRQHandler
B HRTIM1_Master_IRQHandler
PUBWEAK HRTIM1_TIMA_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_TIMA_IRQHandler
B HRTIM1_TIMA_IRQHandler
PUBWEAK HRTIM1_TIMB_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_TIMB_IRQHandler
B HRTIM1_TIMB_IRQHandler
PUBWEAK HRTIM1_TIMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_TIMC_IRQHandler
B HRTIM1_TIMC_IRQHandler
PUBWEAK HRTIM1_TIMD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_TIMD_IRQHandler
B HRTIM1_TIMD_IRQHandler
PUBWEAK HRTIM1_TIME_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_TIME_IRQHandler
B HRTIM1_TIME_IRQHandler
PUBWEAK HRTIM1_FLT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_FLT_IRQHandler
B HRTIM1_FLT_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

7695
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x.h
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82
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_conf.h
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@ -1,82 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_conf.h
* @author MCD Application Team
* @version V1.1.0
* @date 20-September-2012
* @brief Library configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30X_CONF_H
#define __STM32F30X_CONF_H
/* Includes ------------------------------------------------------------------*/
/* Comment the line below to disable peripheral header file inclusion */
#include "stm32f30x_adc.h"
//#include "stm32f30x_can.h"
//#include "stm32f30x_crc.h"
#include "stm32f30x_comp.h"
#include "stm32f30x_dac.h"
#include "stm32f30x_dbgmcu.h"
#include "stm32f30x_dma.h"
#include "stm32f30x_exti.h"
#include "stm32f30x_flash.h"
#include "stm32f30x_gpio.h"
#include "stm32f30x_syscfg.h"
#include "stm32f30x_i2c.h"
#include "stm32f30x_iwdg.h"
#include "stm32f30x_opamp.h"
#include "stm32f30x_pwr.h"
#include "stm32f30x_rcc.h"
#include "stm32f30x_rtc.h"
#include "stm32f30x_spi.h"
#include "stm32f30x_tim.h"
#include "stm32f30x_usart.h"
#include "stm32f30x_wwdg.h"
#include "stm32f30x_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
/* #define USE_FULL_ASSERT 1 */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function which reports
* the name of the source file and the source line number of the call
* that failed. If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#endif /* __STM32F30X_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

535
lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_gpio.c
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@ -1,535 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_gpio.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral:
* + Initialization and Configuration functions
* + GPIO Read and Write functions
* + GPIO Alternate functions configuration functions
*
* @verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
(#) Configure the GPIO pin(s) using GPIO_Init()
Four possible configuration are available for each pin:
(++) Input: Floating, Pull-up, Pull-down.
(++) Output: Push-Pull (Pull-up, Pull-down or no Pull),
Open Drain (Pull-up, Pull-down or no Pull).
In output mode, the speed is configurable: Low, Medium, Fast or High.
(++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull),
Open Drain (Pull-up, Pull-down or no Pull).
(++) Analog: required mode when a pin is to be used as ADC channel,
DAC output or comparator input.
(#) Peripherals alternate function:
(++) For ADC, DAC and comparators, configure the desired pin in
analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
(++) For other peripherals (TIM, USART...):
(+++) Connect the pin to the desired peripherals' Alternate
Function (AF) using GPIO_PinAFConfig() function.
(+++) Configure the desired pin in alternate function mode using
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
(+++) Select the type, pull-up/pull-down and output speed via
GPIO_PuPd, GPIO_OType and GPIO_Speed members.
(+++) Call GPIO_Init() function.
(#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
(#) To set/reset the level of a pin configured in output mode use
GPIO_SetBits()/GPIO_ResetBits()
(#) During and just after reset, the alternate functions are not active
and the GPIO pins are configured in input floating mode (except JTAG pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
general-purpose (PC14 and PC15, respectively) when the LSE
oscillator is off. The LSE has priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose
(PF0 and PF1 respectively) when the HSE oscillator is off. The HSE has
the priority over the GPIO function.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_gpio.h"
#include "stm32f30x_rcc.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup GPIO
* @brief GPIO driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Functions
* @{
*/
/** @defgroup GPIO_Group1 Initialization and Configuration
* @brief Initialization and Configuration
*
@verbatim
===============================================================================
##### Initialization and Configuration #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the GPIOx peripheral registers to their default reset
* values.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @retval None
*/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
if(GPIOx == GPIOA)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
}
else if(GPIOx == GPIOB)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
}
else if(GPIOx == GPIOC)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
}
else if(GPIOx == GPIOD)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
}
else if(GPIOx == GPIOE)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
}
else
{
if(GPIOx == GPIOF)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
}
}
}
/**
* @brief Initializes the GPIOx peripheral according to the specified
* parameters in the GPIO_InitStruct.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO
* peripheral.
* @note GPIO_Pin: selects the pin to be configured:
* GPIO_Pin_0->GPIO_Pin_15 for GPIOA, GPIOB, GPIOC, GPIOD and GPIOE;
* GPIO_Pin_0->GPIO_Pin_2, GPIO_Pin_4, GPIO_Pin_6, GPIO_Pin_9
* and GPIO_Pin_10 for GPIOF.
* @retval None
*/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
uint32_t tmpreg = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
/*-------------------------- Configure the port pins -----------------------*/
/*-- GPIO Mode Configuration --*/
for (pinpos = 0x00; pinpos < 0x10; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
/* Get the port pins position */
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if (currentpin == pos)
{
if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
{
/* Check Speed mode parameters */
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
/* Speed mode configuration */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
/* Check Output mode parameters */
assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
/* Output mode configuration */
GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
}
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
/* Use temporary variable to update PUPDR register configuration, to avoid
unexpected transition in the GPIO pin configuration. */
tmpreg = GPIOx->PUPDR;
tmpreg &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
tmpreg |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
GPIOx->PUPDR = tmpreg;
}
}
}
/**
* @brief Fills each GPIO_InitStruct member with its default value.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
}
/**
* @brief Locks GPIO Pins configuration registers.
* The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx: where x can be (A or B or D) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint32_t tmp = 0x00010000;
/* Check the parameters */
assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
tmp |= GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Reset LCKK bit */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Read LCKK bit */
tmp = GPIOx->LCKR;
/* Read LCKK bit */
tmp = GPIOx->LCKR;
}
/**
* @}
*/
/** @defgroup GPIO_Group2 GPIO Read and Write
* @brief GPIO Read and Write
*
@verbatim
===============================================================================
##### GPIO Read and Write #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* @note This parameter can be GPIO_Pin_x where x can be :
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
* (0..2, 4, 6, 9..10) for GPIOF.
* @retval The input port pin value.
*/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @retval The input port pin value.
*/
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint16_t)GPIOx->IDR);
}
/**
* @brief Reads the specified output data port bit.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_Pin: Specifies the port bit to read.
* @note This parameter can be GPIO_Pin_x where x can be :
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
* (0..2, 4, 6, 9..10) for GPIOF.
* @retval The output port pin value.
*/
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/**
* @brief Reads the specified GPIO output data port.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @retval GPIO output data port value.
*/
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint16_t)GPIOx->ODR);
}
/**
* @brief Sets the selected data port bits.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* @note This parameter can be GPIO_Pin_x where x can be :
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
* (0..2, 4, 6, 9..10) for GPIOF.
* @retval None
*/
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BSRR = GPIO_Pin;
}
/**
* @brief Clears the selected data port bits.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* @note This parameter can be GPIO_Pin_x where x can be :
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
* (0..2, 4, 6, 9..10) for GPIOF.
* @retval None
*/
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BRR = GPIO_Pin;
}
/**
* @brief Sets or clears the selected data port bit.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* @note This parameter can be GPIO_Pin_x where x can be :
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
* (0..2, 4, 6, 9..10) for GPIOF.
* @param BitVal: specifies the value to be written to the selected bit.
* This parameter can be one of the BitAction enumeration values:
* @arg Bit_RESET: to clear the port pin
* @arg Bit_SET: to set the port pin
* @retval None
*/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_BIT_ACTION(BitVal));
if (BitVal != Bit_RESET)
{
GPIOx->BSRR = GPIO_Pin;
}
else
{
GPIOx->BRR = GPIO_Pin ;
}
}
/**
* @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param PortVal: specifies the value to be written to the port output data
* register.
* @retval None
*/
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
GPIOx->ODR = PortVal;
}
/**
* @}
*/
/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
* @brief GPIO Alternate functions configuration functions
*
@verbatim
===============================================================================
##### GPIO Alternate functions configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_PinSource: specifies the pin for the Alternate function.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* @param GPIO_AF: selects the pin to be used as Alternate function.
* This parameter can be one of the following value:
* @arg GPIO_AF_0: JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT, MCO, NJTRST,
* TRACED, TRACECK.
* @arg GPIO_AF_1: OUT, TIM2, TIM15, TIM16, TIM17.
* @arg GPIO_AF_2: COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16.
* @arg GPIO_AF_3: COMP7_OUT, TIM8, TIM15, Touch, HRTIM.
* @arg GPIO_AF_4: I2C1, I2C2, TIM1, TIM8, TIM16, TIM17.
* @arg GPIO_AF_5: IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5
* @arg GPIO_AF_6: IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8
* @arg GPIO_AF_7: AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT, USART1,
* USART2, USART3.
* @arg GPIO_AF_8: COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT, COMP5_OUT,
* COMP6_OUT.
* @arg GPIO_AF_9: AOP4_OUT, CAN, TIM1, TIM8, TIM15.
* @arg GPIO_AF_10: AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17.
* @arg GPIO_AF_11: TIM1, TIM8.
* @arg GPIO_AF_12: TIM1, HRTIM.
* @arg GPIO_AF_13: HRTIM, AOP2_OUT.
* @arg GPIO_AF_14: USBDM, USBDP.
* @arg GPIO_AF_15: OUT.
* @note The pin should already been configured in Alternate Function mode(AF)
* using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
* @note Refer to the Alternate function mapping table in the device datasheet
* for the detailed mapping of the system and peripherals alternate
* function I/O pins.
* @retval None
*/
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
{
uint32_t temp = 0x00;
uint32_t temp_2 = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
assert_param(IS_GPIO_AF(GPIO_AF));
temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_gpio.h
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@ -1,400 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_gpio.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_GPIO_H
#define __STM32F30x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
((PERIPH) == GPIOB) || \
((PERIPH) == GPIOC) || \
((PERIPH) == GPIOD) || \
((PERIPH) == GPIOE) || \
((PERIPH) == GPIOF))
#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
((PERIPH) == GPIOB) || \
((PERIPH) == GPIOD))
/** @defgroup Configuration_Mode_enumeration
* @{
*/
typedef enum
{
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
}GPIOMode_TypeDef;
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
/**
* @}
*/
/** @defgroup Output_type_enumeration
* @{
*/
typedef enum
{
GPIO_OType_PP = 0x00,
GPIO_OType_OD = 0x01
}GPIOOType_TypeDef;
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
/**
* @}
*/
/** @defgroup Output_Maximum_frequency_enumeration
* @{
*/
typedef enum
{
GPIO_Speed_Level_1 = 0x01, /*!< Fast Speed */
GPIO_Speed_Level_2 = 0x02, /*!< Meduim Speed */
GPIO_Speed_Level_3 = 0x03 /*!< High Speed */
}GPIOSpeed_TypeDef;
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
((SPEED) == GPIO_Speed_Level_3))
/**
* @}
*/
/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
* @{
*/
typedef enum
{
GPIO_PuPd_NOPULL = 0x00,
GPIO_PuPd_UP = 0x01,
GPIO_PuPd_DOWN = 0x02
}GPIOPuPd_TypeDef;
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
((PUPD) == GPIO_PuPd_DOWN))
/**
* @}
*/
/** @defgroup Bit_SET_and_Bit_RESET_enumeration
* @{
*/
typedef enum
{
Bit_RESET = 0,
Bit_SET
}BitAction;
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
/**
* @}
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
This parameter can be a value of @ref GPIOOType_TypeDef */
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
This parameter can be a value of @ref GPIOPuPd_TypeDef */
}GPIO_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants
* @{
*/
/** @defgroup GPIO_pins_define
* @{
*/
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \
((PIN) == GPIO_Pin_2) || \
((PIN) == GPIO_Pin_3) || \
((PIN) == GPIO_Pin_4) || \
((PIN) == GPIO_Pin_5) || \
((PIN) == GPIO_Pin_6) || \
((PIN) == GPIO_Pin_7) || \
((PIN) == GPIO_Pin_8) || \
((PIN) == GPIO_Pin_9) || \
((PIN) == GPIO_Pin_10) || \
((PIN) == GPIO_Pin_11) || \
((PIN) == GPIO_Pin_12) || \
((PIN) == GPIO_Pin_13) || \
((PIN) == GPIO_Pin_14) || \
((PIN) == GPIO_Pin_15))
/**
* @}
*/
/** @defgroup GPIO_Pin_sources
* @{
*/
#define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07)
#define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A)
#define GPIO_PinSource11 ((uint8_t)0x0B)
#define GPIO_PinSource12 ((uint8_t)0x0C)
#define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F)
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
((PINSOURCE) == GPIO_PinSource1) || \
((PINSOURCE) == GPIO_PinSource2) || \
((PINSOURCE) == GPIO_PinSource3) || \
((PINSOURCE) == GPIO_PinSource4) || \
((PINSOURCE) == GPIO_PinSource5) || \
((PINSOURCE) == GPIO_PinSource6) || \
((PINSOURCE) == GPIO_PinSource7) || \
((PINSOURCE) == GPIO_PinSource8) || \
((PINSOURCE) == GPIO_PinSource9) || \
((PINSOURCE) == GPIO_PinSource10) || \
((PINSOURCE) == GPIO_PinSource11) || \
((PINSOURCE) == GPIO_PinSource12) || \
((PINSOURCE) == GPIO_PinSource13) || \
((PINSOURCE) == GPIO_PinSource14) || \
((PINSOURCE) == GPIO_PinSource15))
/**
* @}
*/
/** @defgroup GPIO_Alternate_function_selection_define
* @{
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF_0 ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT,
MCO, NJTRST, TRACED, TRACECK */
/**
* @brief AF 1 selection
*/
#define GPIO_AF_1 ((uint8_t)0x01) /* OUT, TIM2, TIM15, TIM16, TIM17 */
/**
* @brief AF 2 selection
*/
#define GPIO_AF_2 ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 */
/**
* @brief AF 3 selection
*/
#define GPIO_AF_3 ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch, HRTIM1 */
/**
* @brief AF 4 selection
*/
#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */
/**
* @brief AF 5 selection
*/
#define GPIO_AF_5 ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */
/**
* @brief AF 6 selection
*/
#define GPIO_AF_6 ((uint8_t)0x06) /* IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */
/**
* @brief AF 7 selection
*/
#define GPIO_AF_7 ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT,
USART1, USART2, USART3 */
/**
* @brief AF 8 selection
*/
#define GPIO_AF_8 ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT,
COMP5_OUT, COMP6_OUT */
/**
* @brief AF 9 selection
*/
#define GPIO_AF_9 ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */
/**
* @brief AF 10 selection
*/
#define GPIO_AF_10 ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */
/**
* @brief AF 11 selection
*/
#define GPIO_AF_11 ((uint8_t)0x0B) /* TIM1, TIM8 */
/**
* @brief AF 12 selection
*/
#define GPIO_AF_12 ((uint8_t)0x0C) /* TIM1, HRTIM1 */
/**
* @brief AF 13 selection
*/
#define GPIO_AF_13 ((uint8_t)0x0D) /* HRTIM1, AOP2_OUT */
/**
* @brief AF 14 selection
*/
#define GPIO_AF_14 ((uint8_t)0x0E) /* USBDM, USBDP */
/**
* @brief AF 15 selection
*/
#define GPIO_AF_15 ((uint8_t)0x0F) /* OUT */
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
((AF) == GPIO_AF_12)||((AF) == GPIO_AF_13)||\
((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
/**
* @}
*/
/** @defgroup GPIO_Speed_Legacy
* @{
*/
#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */
#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */
#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the GPIO configuration to the default reset state *****/
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
/* Initialization and Configuration functions *********************************/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
/* GPIO Read and Write functions **********************************************/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
/* GPIO Alternate functions configuration functions ***************************/
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_GPIO_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_rcc.c
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lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_rcc.h
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/**
******************************************************************************
* @file stm32f30x_rcc.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the RCC
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_RCC_H
#define __STM32F30x_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup RCC
* @{
*/
/* Exported types ------------------------------------------------------------*/
typedef struct
{
uint32_t SYSCLK_Frequency;
uint32_t HCLK_Frequency;
uint32_t PCLK1_Frequency;
uint32_t PCLK2_Frequency;
uint32_t ADC12CLK_Frequency;
uint32_t ADC34CLK_Frequency;
uint32_t I2C1CLK_Frequency;
uint32_t I2C2CLK_Frequency;
uint32_t I2C3CLK_Frequency;
uint32_t TIM1CLK_Frequency;
uint32_t HRTIM1CLK_Frequency;
uint32_t TIM8CLK_Frequency;
uint32_t USART1CLK_Frequency;
uint32_t USART2CLK_Frequency;
uint32_t USART3CLK_Frequency;
uint32_t UART4CLK_Frequency;
uint32_t UART5CLK_Frequency;
uint32_t TIM15CLK_Frequency;
uint32_t TIM16CLK_Frequency;
uint32_t TIM17CLK_Frequency;
}RCC_ClocksTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_Exported_Constants
* @{
*/
/** @defgroup RCC_HSE_configuration
* @{
*/
#define RCC_HSE_OFF ((uint8_t)0x00)
#define RCC_HSE_ON ((uint8_t)0x01)
#define RCC_HSE_Bypass ((uint8_t)0x05)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_Bypass))
/**
* @}
*/
/** @defgroup RCC_PLL_Clock_Source
* @{
*/
#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
((SOURCE) == RCC_PLLSource_PREDIV1))
/**
* @}
*/
/** @defgroup RCC_PLL_Multiplication_Factor
* @{
*/
#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
((MUL) == RCC_PLLMul_16))
/**
* @}
*/
/** @defgroup RCC_PREDIV1_division_factor
* @{
*/
#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
/**
* @}
*/
/** @defgroup RCC_System_Clock_Source
* @{
*/
#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
/**
* @}
*/
/** @defgroup RCC_AHB_Clock_Source
* @{
*/
#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
((HCLK) == RCC_SYSCLK_Div512))
/**
* @}
*/
/** @defgroup RCC_APB1_APB2_clock_source
* @{
*/
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
((PCLK) == RCC_HCLK_Div16))
/**
* @}
*/
/** @defgroup RCC_ADC_clock_source
* @{
*/
/* ADC1 & ADC2 */
#define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000)
#define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100)
#define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110)
#define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120)
#define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130)
#define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140)
#define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150)
#define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160)
#define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170)
#define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180)
#define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190)
#define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0)
#define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0)
/* ADC3 & ADC4 */
#define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000)
#define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000)
#define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200)
#define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400)
#define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600)
#define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800)
#define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00)
#define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00)
#define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00)
#define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000)
#define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200)
#define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400)
#define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600)
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
/**
* @}
*/
/** @defgroup RCC_TIM_clock_source
* @{
*/
#define RCC_TIM1CLK_HCLK ((uint32_t)0x00000000)
#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW
#define RCC_TIM8CLK_HCLK ((uint32_t)0x10000000)
#define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200)
#define RCC_TIM15CLK_HCLK ((uint32_t)0x20000000)
#define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400)
#define RCC_TIM16CLK_HCLK ((uint32_t)0x30000000)
#define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800)
#define RCC_TIM17CLK_HCLK ((uint32_t)0x40000000)
#define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000)
#define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \
((TIMCLK) == RCC_TIM15CLK_HCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \
((TIMCLK) == RCC_TIM16CLK_HCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \
((TIMCLK) == RCC_TIM17CLK_HCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK))
/**
* @}
*/
/** @defgroup RCC_HRTIM_clock_source
* @{
*/
#define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000)
#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW
#define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK))
/**
* @}
*/
/** @defgroup RCC_I2C_clock_source
* @{
*/
#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
#define RCC_I2C2CLK_HSI ((uint32_t)0x10000000)
#define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020)
#define RCC_I2C3CLK_HSI ((uint32_t)0x20000000)
#define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040)
#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \
((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK))
/**
* @}
*/
/** @defgroup RCC_USART_clock_source
* @{
*/
#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
#define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
#define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000)
#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000)
#define RCC_USART2CLK_LSE ((uint32_t)0x20020000)
#define RCC_USART2CLK_HSI ((uint32_t)0x20030000)
#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000)
#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000)
#define RCC_USART3CLK_LSE ((uint32_t)0x30080000)
#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000)
#define RCC_UART4CLK_PCLK ((uint32_t)0x40000000)
#define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000)
#define RCC_UART4CLK_LSE ((uint32_t)0x40200000)
#define RCC_UART4CLK_HSI ((uint32_t)0x40300000)
#define RCC_UART5CLK_PCLK ((uint32_t)0x50000000)
#define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000)
#define RCC_UART5CLK_LSE ((uint32_t)0x50800000)
#define RCC_UART5CLK_HSI ((uint32_t)0x50C00000)
#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
/**
* @}
*/
/** @defgroup RCC_Interrupt_Source
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_CSS ((uint8_t)0x80)
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup RCC_LSE_configuration
* @{
*/
#define RCC_LSE_OFF ((uint32_t)0x00000000)
#define RCC_LSE_ON RCC_BDCR_LSEON
#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_Bypass))
/**
* @}
*/
/** @defgroup RCC_RTC_Clock_Source
* @{
*/
#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
((SOURCE) == RCC_RTCCLKSource_LSI) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
/**
* @}
*/
/** @defgroup RCC_I2S_Clock_Source
* @{
*/
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
/** @defgroup RCC_LSE_Drive_Configuration
* @{
*/
#define RCC_LSEDrive_Low ((uint32_t)0x00000000)
#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
#define RCC_LSEDrive_High RCC_BDCR_LSEDRV
#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
/**
* @}
*/
/** @defgroup RCC_AHB_Peripherals
* @{
*/
#define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
#define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_APB2_Peripherals
* @{
*/
#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
#define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN
#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
#define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFF887FE) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_APB1_Peripherals
* @{
*/
#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
#define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN
#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
#define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN
#define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN
#define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN
#define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_MCO_Clock_Source
* @{
*/
#define RCC_MCOSource_NoClock ((uint8_t)0x00)
#define RCC_MCOSource_LSI ((uint8_t)0x02)
#define RCC_MCOSource_LSE ((uint8_t)0x03)
#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
#define RCC_MCOSource_HSI ((uint8_t)0x05)
#define RCC_MCOSource_HSE ((uint8_t)0x06)
#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \
((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \
((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
/**
* @}
*/
/** @defgroup RCC_MCOPrescaler
* @{
*/
#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
((PRESCALER) == RCC_MCOPrescaler_2) || \
((PRESCALER) == RCC_MCOPrescaler_4) || \
((PRESCALER) == RCC_MCOPrescaler_8) || \
((PRESCALER) == RCC_MCOPrescaler_16) || \
((PRESCALER) == RCC_MCOPrescaler_32) || \
((PRESCALER) == RCC_MCOPrescaler_64) || \
((PRESCALER) == RCC_MCOPrescaler_128))
/**
* @}
*/
/** @defgroup RCC_USB_Device_clock_source
* @{
*/
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
/**
* @}
*/
/** @defgroup RCC_Flag
* @{
*/
#define RCC_FLAG_HSIRDY ((uint8_t)0x01)
#define RCC_FLAG_HSERDY ((uint8_t)0x11)
#define RCC_FLAG_PLLRDY ((uint8_t)0x19)
#define RCC_FLAG_MCOF ((uint8_t)0x9C)
#define RCC_FLAG_LSERDY ((uint8_t)0x21)
#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
#define RCC_FLAG_OBLRST ((uint8_t)0x59)
#define RCC_FLAG_PINRST ((uint8_t)0x5A)
#define RCC_FLAG_PORRST ((uint8_t)0x5B)
#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
((FLAG) == RCC_FLAG_MCOF))
#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the RCC clock configuration to the default reset state */
void RCC_DeInit(void);
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
void RCC_HSEConfig(uint8_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_LSEConfig(uint32_t RCC_LSE);
void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
void RCC_LSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
#ifdef STM32F303xC
void RCC_MCOConfig(uint8_t RCC_MCOSource);
#else
void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
#endif /* STM32F303xC */
/* System, AHB and APB busses clocks configuration functions ******************/
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
/* Peripheral clocks configuration functions **********************************/
void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK);
void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK);
void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK);
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_RCC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
Notes for<o:p></o:p> </span><span style="font-size: 20pt; color: rgb(51, 102, 255); font-family: Verdana;">STM32F30x Standard Peripherals Library Drivers (StdPeriph_Drivers)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span><br>
<span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
© 2014 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
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<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Update history<o:p></o:p></span></h2>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 189px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1 /04-April-2014<o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul><li><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none;">stm32f30x_hrtim.c/.h:&nbsp;</span></li><ul><li><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none;">Add "HRTIM_SINGLE_CALIBRATION" define.</span></li><li><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none;">Add HRTIM Common flags definition</span></li><li><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none;">Add new function <span style="font-style: italic;">HRTIM_SlaveSetCompare(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t CompareUnit, uint32_t Compare).</span></span></li><li><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none;">Update <span style="font-style: italic;">HRTIM_DLLCalibrationStart()</span> function.</span></li><li><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none;">Update <span style="font-style: italic;">HRTIM_DMACmd(), HRTIM_GetITStatus(), HRTIM_GetFlagStatus(), HRTIM_ClearITPendingBit(), HRTIM_ClearFlag() </span>and <span style="font-style: italic;">HRTIM_ITConfig() </span>functions to properly manage master and slave HRTIMERS.<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 189px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 /27-February-2014<o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul><li><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none;">Add support of the<span class="Apple-converted-space">&nbsp;</span></span><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13px; font-variant: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; font-weight: bold; font-style: italic;">STM32F302x8 and STM32F334x8</span><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13px; font-style: normal; font-variant: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; font-weight: bold;"><span class="Apple-converted-space"> </span></span><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none;">devices.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add High Resolution Timer(HRTIM) peripheral driver.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f30x_adc.c</span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update ADC_TempSensorCmd() and ADC_VbatCmd() functions to be inline with the devices specification.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update ADC_DMAConfig() function description.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f30x_dac.c/.h: update overall driver to add the support of the DAC2.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f30x_gpio.c:&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update
GPIO_Init() function to avoid&nbsp;unexpected transition in the GPIO
pin configuration when writing to the PUPDR register.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f30x_rcc.c/.h:&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">update for<span class="Apple-converted-space">&nbsp;</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">STM32F302x8 </span>and<span style="font-style: italic;"> STM32F334x8</span></span><span style="font-size: 10pt; font-family: Verdana;"><span class="Apple-converted-space"> </span>devices</span></li><ul style="margin-bottom: 0cm;"><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add new function<span class="Apple-converted-space">&nbsp;</span><span style="font-style: italic;">RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler).</span></span></li><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">RCC_GetClocksFreq() </span>funtion to :</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">properly return the ADC clock frequency,</span></li><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">workarround USART1 clock limitation for the STM32F302x8 and STM32F334x8 devices,</span></li><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">support TIM15, 16, 17, HRTIM and I2C3 peripherals.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update RCC_I2CCLKConfig() function to support I2C3 peripheral.</span></li><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update RCC_TIMCLKConfig() function to support TIM15, 16, and 17 peripherals.</span></li><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add RCC_HRTIM1CLKConfig() function.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">stm32f30x_syscfg.c/.h</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update SYSCFG_DMAChannelRemapConfig() function to support new DMA channels remap.</span></li><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update SYSCFG_TriggerRemapConfig() funciton to support the new remap of DAC trigger to HRTIM.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">stm32f30x_tim.c:</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update TIM_SelectOCxM() function to properly manage the output compare modes.<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 189px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 23-October-2012<o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f30x_adc.c/h<o:p></o:p></span></p></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Remove
the following functions, the configuration will be done under ADC_Init function :</span></p></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">ADC_InjectedSequencerLengthConfig;
<o:p></o:p></span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">ADC_InjectedChannelConfig;<o:p></o:p></span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">ADC_ExternalTriggerInjectedPolarityConfig;<o:p></o:p></span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-style: italic;">ADC_SelectExternalTriggerInjected</span><o:p></o:p></span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update
&nbsp;comment of <span style="font-style: italic;">uint8_t ADC_TwoSamplingDelay</span> parameter in
<span style="font-style: italic;">ADC_CommonInitTypeDef</span> structure definition.<o:p></o:p></span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p>Add
a function to configure the sampling time for injected channels&nbsp;<o:p></o:p>: <span style="font-style: italic;">void
ADC_InjectedChannelSampleTimeConfig (ADC_TypeDef* ADCx, uint8_t
ADC_InjectedChannel, uint8_t ADC_SampleTime);</span></span></p></li></ul></ul>
<p style="margin-left: 40px;" class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p>
<o:p></o:p></span></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f30x_rtc.c</span></p></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update
comments : remove all reference to RTC_AF1<o:p></o:p>, reformulate
the PC13 RTC_AF table to be in line with the description in Reference&nbsp;manual (RM00316)</span></p></li></ul></ul><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p>&nbsp;</o:p>stm32f30x_tim.c
<o:p></o:p></span></p></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update local variables declaration (must be uint32_t) to correct&nbsp;Tasking toochain warnings. &nbsp;</span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p>stm32f30x_gpio.h
<o:p></o:p></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update <span style="font-style: italic;">GPIOSpeed_TypeDef </span>parameters structure to be in line with description in Reference manual and add GPIO&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">speed</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> legacy defines.</span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Remove all references to other products (STM32F37x, STM32F0xx,...) in the comments.<br></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 189px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 04-September-2012<o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release for <span style="font-style: italic; font-weight: bold;">STM32F30x and STM32F31x devices</span></span></li></ul>
<span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0cm;" type="square"></ul>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';">Licensed
under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use
this&nbsp;</span><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';">package</span><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';">
except in compliance with the License. You may obtain a copy of the License
at:<br><br></span></p>
<div style="text-align: center;"><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
<a href="http://www.st.com/software_license_agreement_liberty_v2" target="_blank">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';"></span></div><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';"><br>Unless
required by applicable law or agreed to in writing, software distributed under
the License is distributed on an "AS IS" BASIS, <br>WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, either express or implied. See the License for the
specific language governing permissions and limitations under the
License.</span><b><span style="font-size: 10pt; color: black; font-family: Verdana;"></span></b><p class="MsoNormal" style="margin: 4.5pt 0cm;"><b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></p>
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<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';">For
complete documentation on </span><span style="font-size: 10pt; font-family: 'Verdana','sans-serif';">STM32<span style="color: black;"> Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank"><u><span style="color: blue;"></span></u></a></span><span style="color: black;"><o:p></o:p></span></p>
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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_adc.h
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/**
******************************************************************************
* @file stm32f30x_adc.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_ADC_H
#define __STM32F30x_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief ADC Init structure definition
*/
typedef struct
{
uint32_t ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_Resolution; /*!< Configures the ADC resolution.
This parameter can be a value of @ref ADC_resolution */
uint32_t ADC_ExternalTrigConvEvent; /*!< Defines the external trigger used to start the analog
to digital conversion of regular channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_ExternalTrigEventEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
This parameter can be a value of
@ref ADC_external_trigger_edge_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align */
uint32_t ADC_OverrunMode; /*!< Specifies the way data overrun are managed.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_AutoInjMode; /*!< Enable/disable automatic injected group conversion after
regular group conversion.
This parameter can be set to ENABLE or DISABLE. */
uint8_t ADC_NbrOfRegChannel; /*!< Specifies the number of ADC channels that will be converted
using the sequencer for regular channel group.
This parameter must range from 1 to 16. */
}ADC_InitTypeDef;
/**
* @}
*/
/**
* @brief ADC Init structure definition
*/
typedef struct
{
uint32_t ADC_ExternalTrigInjecConvEvent; /*!< Defines the external trigger used to start the analog
to digital conversion of injected channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_Injected_channels_conversion */
uint32_t ADC_ExternalTrigInjecEventEdge; /*!< Select the external trigger edge and enable the trigger of an injected group.
This parameter can be a value of
@ref ADC_external_trigger_edge_for_Injected_channels_conversion */
uint8_t ADC_NbrOfInjecChannel; /*!< Specifies the number of ADC channels that will be converted
using the sequencer for injected channel group.
This parameter must range from 1 to 4. */
uint32_t ADC_InjecSequence1;
uint32_t ADC_InjecSequence2;
uint32_t ADC_InjecSequence3;
uint32_t ADC_InjecSequence4;
}ADC_InjectedInitTypeDef;
/**
* @}
*/
typedef struct
{
uint32_t ADC_Mode; /*!< Configures the ADC to operate in
independent or multi mode.
This parameter can be a value of @ref ADC_mode */
uint32_t ADC_Clock; /*!< Select the clock of the ADC. The clock is common for both master
and slave ADCs.
This parameter can be a value of @ref ADC_Clock */
uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
This parameter can be a value of
@ref ADC_Direct_memory_access_mode_for_multi_mode */
uint32_t ADC_DMAMode; /*!< Configures the DMA mode for ADC.
This parameter can be a value of @ref ADC_DMA_Mode_definition */
uint8_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
This parameter can be a value between 0x0 and 0xF */
}ADC_CommonInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants
* @{
*/
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
((PERIPH) == ADC2) || \
((PERIPH) == ADC3) || \
((PERIPH) == ADC4))
#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
((PERIPH) == ADC2) || \
((PERIPH) == ADC3) || \
((PERIPH) == ADC4))
/** @defgroup ADC_ContinuousConvMode
* @{
*/
#define ADC_ContinuousConvMode_Enable ((uint32_t)0x00002000) /*!< ADC continuous conversion mode enable */
#define ADC_ContinuousConvMode_Disable ((uint32_t)0x00000000) /*!< ADC continuous conversion mode disable */
#define IS_ADC_CONVMODE(MODE) (((MODE) == ADC_ContinuousConvMode_Enable) || \
((MODE) == ADC_ContinuousConvMode_Disable))
/**
* @}
*/
/** @defgroup ADC_OverunMode
* @{
*/
#define ADC_OverrunMode_Enable ((uint32_t)0x00001000) /*!< ADC Overrun Mode enable */
#define ADC_OverrunMode_Disable ((uint32_t)0x00000000) /*!< ADC Overrun Mode disable */
#define IS_ADC_OVRUNMODE(MODE) (((MODE) == ADC_OverrunMode_Enable) || \
((MODE) == ADC_OverrunMode_Disable))
/**
* @}
*/
/** @defgroup ADC_AutoInjecMode
* @{
*/
#define ADC_AutoInjec_Enable ((uint32_t)0x02000000) /*!< ADC Auto injected Mode enable */
#define ADC_AutoInjec_Disable ((uint32_t)0x00000000) /*!< ADC Auto injected Mode disable */
#define IS_ADC_AUTOINJECMODE(MODE) (((MODE) == ADC_AutoInjec_Enable) || \
((MODE) == ADC_AutoInjec_Disable))
/**
* @}
*/
/** @defgroup ADC_resolution
* @{
*/
#define ADC_Resolution_12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
#define ADC_Resolution_10b ((uint32_t)0x00000008) /*!< ADC 10-bit resolution */
#define ADC_Resolution_8b ((uint32_t)0x00000010) /*!< ADC 8-bit resolution */
#define ADC_Resolution_6b ((uint32_t)0x00000018) /*!< ADC 6-bit resolution */
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
((RESOLUTION) == ADC_Resolution_10b) || \
((RESOLUTION) == ADC_Resolution_8b) || \
((RESOLUTION) == ADC_Resolution_6b))
/**
* @}
*/
/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
* @{
*/
#define ADC_ExternalTrigEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */
#define ADC_ExternalTrigEventEdge_RisingEdge ((uint16_t)0x0400) /*!< ADC external trigger rising edge for regular conversion */
#define ADC_ExternalTrigEventEdge_FallingEdge ((uint16_t)0x0800) /*!< ADC ADC external trigger falling edge for regular conversion */
#define ADC_ExternalTrigEventEdge_BothEdge ((uint16_t)0x0C00) /*!< ADC ADC external trigger both edges for regular conversion */
#define IS_EXTERNALTRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigEventEdge_None) || \
((EDGE) == ADC_ExternalTrigEventEdge_RisingEdge) || \
((EDGE) == ADC_ExternalTrigEventEdge_FallingEdge) || \
((EDGE) == ADC_ExternalTrigEventEdge_BothEdge))
/**
* @}
*/
/** @defgroup ADC_external_trigger_edge_for_Injected_channels_conversion
* @{
*/
#define ADC_ExternalTrigInjecEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */
#define ADC_ExternalTrigInjecEventEdge_RisingEdge ((uint16_t)0x0040) /*!< ADC external trigger rising edge for injected conversion */
#define ADC_ExternalTrigInjecEventEdge_FallingEdge ((uint16_t)0x0080) /*!< ADC external trigger falling edge for injected conversion */
#define ADC_ExternalTrigInjecEventEdge_BothEdge ((uint16_t)0x00C0) /*!< ADC external trigger both edges for injected conversion */
#define IS_EXTERNALTRIGINJ_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecEventEdge_None) || \
((EDGE) == ADC_ExternalTrigInjecEventEdge_RisingEdge) || \
((EDGE) == ADC_ExternalTrigInjecEventEdge_FallingEdge) || \
((EDGE) == ADC_ExternalTrigInjecEventEdge_BothEdge))
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
* @{
*/
#define ADC_ExternalTrigConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger event 0 */
#define ADC_ExternalTrigConvEvent_1 ((uint16_t)0x0040) /*!< ADC external trigger event 1 */
#define ADC_ExternalTrigConvEvent_2 ((uint16_t)0x0080) /*!< ADC external trigger event 2 */
#define ADC_ExternalTrigConvEvent_3 ((uint16_t)0x00C0) /*!< ADC external trigger event 3 */
#define ADC_ExternalTrigConvEvent_4 ((uint16_t)0x0100) /*!< ADC external trigger event 4 */
#define ADC_ExternalTrigConvEvent_5 ((uint16_t)0x0140) /*!< ADC external trigger event 5 */
#define ADC_ExternalTrigConvEvent_6 ((uint16_t)0x0180) /*!< ADC external trigger event 6 */
#define ADC_ExternalTrigConvEvent_7 ((uint16_t)0x01C0) /*!< ADC external trigger event 7 */
#define ADC_ExternalTrigConvEvent_8 ((uint16_t)0x0200) /*!< ADC external trigger event 8 */
#define ADC_ExternalTrigConvEvent_9 ((uint16_t)0x0240) /*!< ADC external trigger event 9 */
#define ADC_ExternalTrigConvEvent_10 ((uint16_t)0x0280) /*!< ADC external trigger event 10 */
#define ADC_ExternalTrigConvEvent_11 ((uint16_t)0x02C0) /*!< ADC external trigger event 11 */
#define ADC_ExternalTrigConvEvent_12 ((uint16_t)0x0300) /*!< ADC external trigger event 12 */
#define ADC_ExternalTrigConvEvent_13 ((uint16_t)0x0340) /*!< ADC external trigger event 13 */
#define ADC_ExternalTrigConvEvent_14 ((uint16_t)0x0380) /*!< ADC external trigger event 14 */
#define ADC_ExternalTrigConvEvent_15 ((uint16_t)0x03C0) /*!< ADC external trigger event 15 */
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConvEvent_0) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_1) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_2) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_3) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_4) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_5) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_6) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_7) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_8) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_9) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_10) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_11) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_12) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_13) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_14) || \
((REGTRIG) == ADC_ExternalTrigConvEvent_15))
/**
* @}
*/
/** @defgroup ADC_external_trigger_sources_for_Injected_channels_conversion
* @{
*/
#define ADC_ExternalTrigInjecConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger for injected conversion event 0 */
#define ADC_ExternalTrigInjecConvEvent_1 ((uint16_t)0x0004) /*!< ADC external trigger for injected conversion event 1 */
#define ADC_ExternalTrigInjecConvEvent_2 ((uint16_t)0x0008) /*!< ADC external trigger for injected conversion event 2 */
#define ADC_ExternalTrigInjecConvEvent_3 ((uint16_t)0x000C) /*!< ADC external trigger for injected conversion event 3 */
#define ADC_ExternalTrigInjecConvEvent_4 ((uint16_t)0x0010) /*!< ADC external trigger for injected conversion event 4 */
#define ADC_ExternalTrigInjecConvEvent_5 ((uint16_t)0x0014) /*!< ADC external trigger for injected conversion event 5 */
#define ADC_ExternalTrigInjecConvEvent_6 ((uint16_t)0x0018) /*!< ADC external trigger for injected conversion event 6 */
#define ADC_ExternalTrigInjecConvEvent_7 ((uint16_t)0x001C) /*!< ADC external trigger for injected conversion event 7 */
#define ADC_ExternalTrigInjecConvEvent_8 ((uint16_t)0x0020) /*!< ADC external trigger for injected conversion event 8 */
#define ADC_ExternalTrigInjecConvEvent_9 ((uint16_t)0x0024) /*!< ADC external trigger for injected conversion event 9 */
#define ADC_ExternalTrigInjecConvEvent_10 ((uint16_t)0x0028) /*!< ADC external trigger for injected conversion event 10 */
#define ADC_ExternalTrigInjecConvEvent_11 ((uint16_t)0x002C) /*!< ADC external trigger for injected conversion event 11 */
#define ADC_ExternalTrigInjecConvEvent_12 ((uint16_t)0x0030) /*!< ADC external trigger for injected conversion event 12 */
#define ADC_ExternalTrigInjecConvEvent_13 ((uint16_t)0x0034) /*!< ADC external trigger for injected conversion event 13 */
#define ADC_ExternalTrigInjecConvEvent_14 ((uint16_t)0x0038) /*!< ADC external trigger for injected conversion event 14 */
#define ADC_ExternalTrigInjecConvEvent_15 ((uint16_t)0x003C) /*!< ADC external trigger for injected conversion event 15 */
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConvEvent_0) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_1) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_2) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_3) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_4) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_5) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_6) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_7) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_8) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_9) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_10) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_11) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_12) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_13) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_14) || \
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_15))
/**
* @}
*/
/** @defgroup ADC_data_align
* @{
*/
#define ADC_DataAlign_Right ((uint32_t)0x00000000) /*!< ADC Data alignment right */
#define ADC_DataAlign_Left ((uint32_t)0x00000020) /*!< ADC Data alignment left */
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
((ALIGN) == ADC_DataAlign_Left))
/**
* @}
*/
/** @defgroup ADC_channels
* @{
*/
#define ADC_Channel_1 ((uint8_t)0x01) /*!< ADC Channel 1 */
#define ADC_Channel_2 ((uint8_t)0x02) /*!< ADC Channel 2 */
#define ADC_Channel_3 ((uint8_t)0x03) /*!< ADC Channel 3 */
#define ADC_Channel_4 ((uint8_t)0x04) /*!< ADC Channel 4 */
#define ADC_Channel_5 ((uint8_t)0x05) /*!< ADC Channel 5 */
#define ADC_Channel_6 ((uint8_t)0x06) /*!< ADC Channel 6 */
#define ADC_Channel_7 ((uint8_t)0x07) /*!< ADC Channel 7 */
#define ADC_Channel_8 ((uint8_t)0x08) /*!< ADC Channel 8 */
#define ADC_Channel_9 ((uint8_t)0x09) /*!< ADC Channel 9 */
#define ADC_Channel_10 ((uint8_t)0x0A) /*!< ADC Channel 10 */
#define ADC_Channel_11 ((uint8_t)0x0B) /*!< ADC Channel 11 */
#define ADC_Channel_12 ((uint8_t)0x0C) /*!< ADC Channel 12 */
#define ADC_Channel_13 ((uint8_t)0x0D) /*!< ADC Channel 13 */
#define ADC_Channel_14 ((uint8_t)0x0E) /*!< ADC Channel 14 */
#define ADC_Channel_15 ((uint8_t)0x0F) /*!< ADC Channel 15 */
#define ADC_Channel_16 ((uint8_t)0x10) /*!< ADC Channel 16 */
#define ADC_Channel_17 ((uint8_t)0x11) /*!< ADC Channel 17 */
#define ADC_Channel_18 ((uint8_t)0x12) /*!< ADC Channel 18 */
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_18)
#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_17)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \
((CHANNEL) == ADC_Channel_2) || \
((CHANNEL) == ADC_Channel_3) || \
((CHANNEL) == ADC_Channel_4) || \
((CHANNEL) == ADC_Channel_5) || \
((CHANNEL) == ADC_Channel_6) || \
((CHANNEL) == ADC_Channel_7) || \
((CHANNEL) == ADC_Channel_8) || \
((CHANNEL) == ADC_Channel_9) || \
((CHANNEL) == ADC_Channel_10) || \
((CHANNEL) == ADC_Channel_11) || \
((CHANNEL) == ADC_Channel_12) || \
((CHANNEL) == ADC_Channel_13) || \
((CHANNEL) == ADC_Channel_14) || \
((CHANNEL) == ADC_Channel_15) || \
((CHANNEL) == ADC_Channel_16) || \
((CHANNEL) == ADC_Channel_17) || \
((CHANNEL) == ADC_Channel_18))
#define IS_ADC_DIFFCHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \
((CHANNEL) == ADC_Channel_2) || \
((CHANNEL) == ADC_Channel_3) || \
((CHANNEL) == ADC_Channel_4) || \
((CHANNEL) == ADC_Channel_5) || \
((CHANNEL) == ADC_Channel_6) || \
((CHANNEL) == ADC_Channel_7) || \
((CHANNEL) == ADC_Channel_8) || \
((CHANNEL) == ADC_Channel_9) || \
((CHANNEL) == ADC_Channel_10) || \
((CHANNEL) == ADC_Channel_11) || \
((CHANNEL) == ADC_Channel_12) || \
((CHANNEL) == ADC_Channel_13) || \
((CHANNEL) == ADC_Channel_14))
/**
* @}
*/
/** @defgroup ADC_mode
* @{
*/
#define ADC_Mode_Independent ((uint32_t)0x00000000) /*!< ADC independent mode */
#define ADC_Mode_CombRegSimulInjSimul ((uint32_t)0x00000001) /*!< ADC multi ADC mode: Combined Regular simultaneous injected simultaneous mode */
#define ADC_Mode_CombRegSimulAltTrig ((uint32_t)0x00000002) /*!< ADC multi ADC mode: Combined Regular simultaneous Alternate trigger mode */
#define ADC_Mode_InjSimul ((uint32_t)0x00000005) /*!< ADC multi ADC mode: Injected simultaneous mode */
#define ADC_Mode_RegSimul ((uint32_t)0x00000006) /*!< ADC multi ADC mode: Regular simultaneous mode */
#define ADC_Mode_Interleave ((uint32_t)0x00000007) /*!< ADC multi ADC mode: Interleave mode */
#define ADC_Mode_AltTrig ((uint32_t)0x00000009) /*!< ADC multi ADC mode: Alternate Trigger mode */
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
((MODE) == ADC_Mode_CombRegSimulInjSimul) || \
((MODE) == ADC_Mode_CombRegSimulAltTrig) || \
((MODE) == ADC_Mode_InjSimul) || \
((MODE) == ADC_Mode_RegSimul) || \
((MODE) == ADC_Mode_Interleave) || \
((MODE) == ADC_Mode_AltTrig))
/**
* @}
*/
/** @defgroup ADC_Clock
* @{
*/
#define ADC_Clock_AsynClkMode ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */
#define ADC_Clock_SynClkModeDiv1 ((uint32_t)0x00010000) /*!< Synchronous clock mode divided by 1 */
#define ADC_Clock_SynClkModeDiv2 ((uint32_t)0x00020000) /*!< Synchronous clock mode divided by 2 */
#define ADC_Clock_SynClkModeDiv4 ((uint32_t)0x00030000) /*!< Synchronous clock mode divided by 4 */
#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_Clock_AsynClkMode) ||\
((CLOCK) == ADC_Clock_SynClkModeDiv1) ||\
((CLOCK) == ADC_Clock_SynClkModeDiv2)||\
((CLOCK) == ADC_Clock_SynClkModeDiv4))
/**
* @}
*/
/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
* @{
*/
#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /*!< DMA mode disabled */
#define ADC_DMAAccessMode_1 ((uint32_t)0x00008000) /*!< DMA mode enabled for 12 and 10-bit resolution (6 bit) */
#define ADC_DMAAccessMode_2 ((uint32_t)0x0000C000) /*!< DMA mode enabled for 8 and 6-bit resolution (8bit) */
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
((MODE) == ADC_DMAAccessMode_1) || \
((MODE) == ADC_DMAAccessMode_2))
/**
* @}
*/
/** @defgroup ADC_sampling_time
* @{
*/
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) /*!< ADC sampling time 1.5 cycle */
#define ADC_SampleTime_2Cycles5 ((uint8_t)0x01) /*!< ADC sampling time 2.5 cycles */
#define ADC_SampleTime_4Cycles5 ((uint8_t)0x02) /*!< ADC sampling time 4.5 cycles */
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x03) /*!< ADC sampling time 7.5 cycles */
#define ADC_SampleTime_19Cycles5 ((uint8_t)0x04) /*!< ADC sampling time 19.5 cycles */
#define ADC_SampleTime_61Cycles5 ((uint8_t)0x05) /*!< ADC sampling time 61.5 cycles */
#define ADC_SampleTime_181Cycles5 ((uint8_t)0x06) /*!< ADC sampling time 181.5 cycles */
#define ADC_SampleTime_601Cycles5 ((uint8_t)0x07) /*!< ADC sampling time 601.5 cycles */
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
((TIME) == ADC_SampleTime_2Cycles5) || \
((TIME) == ADC_SampleTime_4Cycles5) || \
((TIME) == ADC_SampleTime_7Cycles5) || \
((TIME) == ADC_SampleTime_19Cycles5) || \
((TIME) == ADC_SampleTime_61Cycles5) || \
((TIME) == ADC_SampleTime_181Cycles5) || \
((TIME) == ADC_SampleTime_601Cycles5))
/**
* @}
*/
/** @defgroup ADC_injected_Channel_selection
* @{
*/
#define ADC_InjectedChannel_1 ADC_Channel_1 /*!< ADC Injected channel 1 */
#define ADC_InjectedChannel_2 ADC_Channel_2 /*!< ADC Injected channel 2 */
#define ADC_InjectedChannel_3 ADC_Channel_3 /*!< ADC Injected channel 3 */
#define ADC_InjectedChannel_4 ADC_Channel_4 /*!< ADC Injected channel 4 */
#define ADC_InjectedChannel_5 ADC_Channel_5 /*!< ADC Injected channel 5 */
#define ADC_InjectedChannel_6 ADC_Channel_6 /*!< ADC Injected channel 6 */
#define ADC_InjectedChannel_7 ADC_Channel_7 /*!< ADC Injected channel 7 */
#define ADC_InjectedChannel_8 ADC_Channel_8 /*!< ADC Injected channel 8 */
#define ADC_InjectedChannel_9 ADC_Channel_9 /*!< ADC Injected channel 9 */
#define ADC_InjectedChannel_10 ADC_Channel_10 /*!< ADC Injected channel 10 */
#define ADC_InjectedChannel_11 ADC_Channel_11 /*!< ADC Injected channel 11 */
#define ADC_InjectedChannel_12 ADC_Channel_12 /*!< ADC Injected channel 12 */
#define ADC_InjectedChannel_13 ADC_Channel_13 /*!< ADC Injected channel 13 */
#define ADC_InjectedChannel_14 ADC_Channel_14 /*!< ADC Injected channel 14 */
#define ADC_InjectedChannel_15 ADC_Channel_15 /*!< ADC Injected channel 15 */
#define ADC_InjectedChannel_16 ADC_Channel_16 /*!< ADC Injected channel 16 */
#define ADC_InjectedChannel_17 ADC_Channel_17 /*!< ADC Injected channel 17 */
#define ADC_InjectedChannel_18 ADC_Channel_18 /*!< ADC Injected channel 18 */
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
((CHANNEL) == ADC_InjectedChannel_2) || \
((CHANNEL) == ADC_InjectedChannel_3) || \
((CHANNEL) == ADC_InjectedChannel_4) ||\
((CHANNEL) == ADC_InjectedChannel_5) ||\
((CHANNEL) == ADC_InjectedChannel_6) ||\
((CHANNEL) == ADC_InjectedChannel_7) ||\
((CHANNEL) == ADC_InjectedChannel_8) ||\
((CHANNEL) == ADC_InjectedChannel_9) ||\
((CHANNEL) == ADC_InjectedChannel_10) ||\
((CHANNEL) == ADC_InjectedChannel_11) ||\
((CHANNEL) == ADC_InjectedChannel_12) ||\
((CHANNEL) == ADC_InjectedChannel_13) ||\
((CHANNEL) == ADC_InjectedChannel_14) ||\
((CHANNEL) == ADC_InjectedChannel_15) ||\
((CHANNEL) == ADC_InjectedChannel_16) ||\
((CHANNEL) == ADC_InjectedChannel_17) ||\
((CHANNEL) == ADC_InjectedChannel_18))
/**
* @}
*/
/** @defgroup ADC_injected_Sequence_selection
* @{
*/
#define ADC_InjectedSequence_1 ADC_Channel_1 /*!< ADC Injected sequence 1 */
#define ADC_InjectedSequence_2 ADC_Channel_2 /*!< ADC Injected sequence 2 */
#define ADC_InjectedSequence_3 ADC_Channel_3 /*!< ADC Injected sequence 3 */
#define ADC_InjectedSequence_4 ADC_Channel_4 /*!< ADC Injected sequence 4 */
#define IS_ADC_INJECTED_SEQUENCE(SEQUENCE) (((SEQUENCE) == ADC_InjectedSequence_1) || \
((SEQUENCE) == ADC_InjectedSequence_2) || \
((SEQUENCE) == ADC_InjectedSequence_3) || \
((SEQUENCE) == ADC_InjectedSequence_4))
/**
* @}
*/
/** @defgroup ADC_analog_watchdog_selection
* @{
*/
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00C00000) /*!< ADC Analog watchdog single regular mode */
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x01400000) /*!< ADC Analog watchdog single injected mode */
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x01C00000) /*!< ADC Analog watchdog single regular or injected mode */
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) /*!< ADC Analog watchdog all regular mode */
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x01000000) /*!< ADC Analog watchdog all injected mode */
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x01800000) /*!< ADC Analog watchdog all regular and all injected mode */
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) /*!< ADC Analog watchdog off */
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_None))
/**
* @}
*/
/** @defgroup ADC_Calibration_Mode_definition
* @{
*/
#define ADC_CalibrationMode_Single ((uint32_t)0x00000000) /*!< ADC Calibration for single ended channel */
#define ADC_CalibrationMode_Differential ((uint32_t)0x40000000) /*!< ADC Calibration for differential channel */
#define IS_ADC_CALIBRATION_MODE(MODE) (((MODE) == ADC_CalibrationMode_Single) ||((MODE) == ADC_CalibrationMode_Differential))
/**
* @}
*/
/** @defgroup ADC_DMA_Mode_definition
* @{
*/
#define ADC_DMAMode_OneShot ((uint32_t)0x00000000) /*!< ADC DMA Oneshot mode */
#define ADC_DMAMode_Circular ((uint32_t)0x00000002) /*!< ADC DMA circular mode */
#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || ((MODE) == ADC_DMAMode_Circular))
/**
* @}
*/
/** @defgroup ADC_interrupts_definition
* @{
*/
#define ADC_IT_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) interrupt source */
#define ADC_IT_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling interrupt source */
#define ADC_IT_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion interrupt source */
#define ADC_IT_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions interrupt source */
#define ADC_IT_OVR ((uint16_t)0x0010) /*!< ADC overrun interrupt source */
#define ADC_IT_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion interrupt source */
#define ADC_IT_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions interrupt source */
#define ADC_IT_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 interrupt source */
#define ADC_IT_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 interrupt source */
#define ADC_IT_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 interrupt source */
#define ADC_IT_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow interrupt source */
#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF800) == 0x0000) && ((IT) != 0x0000))
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_RDY) || ((IT) == ADC_IT_EOSMP) || \
((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOS) || \
((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_EOS) || \
((IT) == ADC_IT_JEOS) || ((IT) == ADC_IT_AWD1) || \
((IT) == ADC_IT_AWD2) || ((IT) == ADC_IT_AWD3) || \
((IT) == ADC_IT_JQOVF))
/**
* @}
*/
/** @defgroup ADC_flags_definition
* @{
*/
#define ADC_FLAG_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) flag */
#define ADC_FLAG_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling flag */
#define ADC_FLAG_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion flag */
#define ADC_FLAG_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions flag */
#define ADC_FLAG_OVR ((uint16_t)0x0010) /*!< ADC overrun flag */
#define ADC_FLAG_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion flag */
#define ADC_FLAG_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions flag */
#define ADC_FLAG_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 flag */
#define ADC_FLAG_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 flag */
#define ADC_FLAG_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 flag */
#define ADC_FLAG_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow flag */
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF800) == 0x0000) && ((FLAG) != 0x0000))
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \
((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_JEOC) || \
((FLAG) == ADC_FLAG_JEOS) || ((FLAG) == ADC_FLAG_AWD1) || \
((FLAG) == ADC_FLAG_AWD2) || ((FLAG) == ADC_FLAG_AWD3) || \
((FLAG) == ADC_FLAG_JQOVF))
/**
* @}
*/
/** @defgroup ADC_Common_flags_definition
* @{
*/
#define ADC_FLAG_MSTRDY ((uint32_t)0x00000001) /*!< ADC Master Ready (ADRDY) flag */
#define ADC_FLAG_MSTEOSMP ((uint32_t)0x00000002) /*!< ADC Master End of Sampling flag */
#define ADC_FLAG_MSTEOC ((uint32_t)0x00000004) /*!< ADC Master End of Regular Conversion flag */
#define ADC_FLAG_MSTEOS ((uint32_t)0x00000008) /*!< ADC Master End of Regular sequence of Conversions flag */
#define ADC_FLAG_MSTOVR ((uint32_t)0x00000010) /*!< ADC Master overrun flag */
#define ADC_FLAG_MSTJEOC ((uint32_t)0x00000020) /*!< ADC Master End of Injected Conversion flag */
#define ADC_FLAG_MSTJEOS ((uint32_t)0x00000040) /*!< ADC Master End of Injected sequence of Conversions flag */
#define ADC_FLAG_MSTAWD1 ((uint32_t)0x00000080) /*!< ADC Master Analog watchdog 1 flag */
#define ADC_FLAG_MSTAWD2 ((uint32_t)0x00000100) /*!< ADC Master Analog watchdog 2 flag */
#define ADC_FLAG_MSTAWD3 ((uint32_t)0x00000200) /*!< ADC Master Analog watchdog 3 flag */
#define ADC_FLAG_MSTJQOVF ((uint32_t)0x00000400) /*!< ADC Master Injected Context Queue Overflow flag */
#define ADC_FLAG_SLVRDY ((uint32_t)0x00010000) /*!< ADC Slave Ready (ADRDY) flag */
#define ADC_FLAG_SLVEOSMP ((uint32_t)0x00020000) /*!< ADC Slave End of Sampling flag */
#define ADC_FLAG_SLVEOC ((uint32_t)0x00040000) /*!< ADC Slave End of Regular Conversion flag */
#define ADC_FLAG_SLVEOS ((uint32_t)0x00080000) /*!< ADC Slave End of Regular sequence of Conversions flag */
#define ADC_FLAG_SLVOVR ((uint32_t)0x00100000) /*!< ADC Slave overrun flag */
#define ADC_FLAG_SLVJEOC ((uint32_t)0x00200000) /*!< ADC Slave End of Injected Conversion flag */
#define ADC_FLAG_SLVJEOS ((uint32_t)0x00400000) /*!< ADC Slave End of Injected sequence of Conversions flag */
#define ADC_FLAG_SLVAWD1 ((uint32_t)0x00800000) /*!< ADC Slave Analog watchdog 1 flag */
#define ADC_FLAG_SLVAWD2 ((uint32_t)0x01000000) /*!< ADC Slave Analog watchdog 2 flag */
#define ADC_FLAG_SLVAWD3 ((uint32_t)0x02000000) /*!< ADC Slave Analog watchdog 3 flag */
#define ADC_FLAG_SLVJQOVF ((uint32_t)0x04000000) /*!< ADC Slave Injected Context Queue Overflow flag */
#define IS_ADC_CLEAR_COMMONFLAG(FLAG) ((((FLAG) & (uint32_t)0xF800F800) == 0x0000) && ((FLAG) != 0x00000000))
#define IS_ADC_GET_COMMONFLAG(FLAG) (((FLAG) == ADC_FLAG_MSTRDY) || ((FLAG) == ADC_FLAG_MSTEOSMP) || \
((FLAG) == ADC_FLAG_MSTEOC) || ((FLAG) == ADC_FLAG_MSTEOS) || \
((FLAG) == ADC_FLAG_MSTOVR) || ((FLAG) == ADC_FLAG_MSTEOS) || \
((FLAG) == ADC_FLAG_MSTJEOS) || ((FLAG) == ADC_FLAG_MSTAWD1) || \
((FLAG) == ADC_FLAG_MSTAWD2) || ((FLAG) == ADC_FLAG_MSTAWD3) || \
((FLAG) == ADC_FLAG_MSTJQOVF) || \
((FLAG) == ADC_FLAG_SLVRDY) || ((FLAG) == ADC_FLAG_SLVEOSMP) || \
((FLAG) == ADC_FLAG_SLVEOC) || ((FLAG) == ADC_FLAG_SLVEOS) || \
((FLAG) == ADC_FLAG_SLVOVR) || ((FLAG) == ADC_FLAG_SLVEOS) || \
((FLAG) == ADC_FLAG_SLVJEOS) || ((FLAG) == ADC_FLAG_SLVAWD1) || \
((FLAG) == ADC_FLAG_SLVAWD2) || ((FLAG) == ADC_FLAG_SLVAWD3) || \
((FLAG) == ADC_FLAG_SLVJQOVF))
/**
* @}
*/
/** @defgroup ADC_thresholds
* @{
*/
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_offset
* @{
*/
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_length
* @{
*/
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_regular_length
* @{
*/
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_discontinuous_mode_number
* @{
*/
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
/**
* @}
*/
/** @defgroup ADC_two_sampling_delay_number
* @{
*/
#define IS_ADC_TWOSAMPLING_DELAY(DELAY) (((DELAY) <= 0xF))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the ADC configuration to the default reset state *****/
void ADC_DeInit(ADC_TypeDef* ADCx);
/* Initialization and Configuration functions *********************************/
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct);
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_StartCalibration(ADC_TypeDef* ADCx);
uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx);
void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration);
void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode);
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_DisableCmd(ADC_TypeDef* ADCx);
FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx);
void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState);
void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
/* Analog Watchdog configuration functions ************************************/
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
/* Temperature Sensor, Vrefint and Vbat management function */
void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
/* Channels Configuration functions ***********************************/
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength);
void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge);
void ADC_StartConversion(ADC_TypeDef* ADCx);
FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx);
void ADC_StopConversion(ADC_TypeDef* ADCx);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx);
void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
/* Regular Channels DMA Configuration functions *******************************/
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode);
/* Injected channels Configuration functions **********************************/
void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime);
void ADC_StartInjectedConversion(ADC_TypeDef* ADCx);
FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx);
void ADC_StopInjectedConversion(ADC_TypeDef* ADCx);
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
/* ADC Dual Modes Configuration functions *************************************/
FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
/* Interrupts and flags management functions **********************************/
void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F30x_ADC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

643
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_can.h
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@ -1,643 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_can.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the CAN firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_CAN_H
#define __STM32F30x_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup CAN
* @{
*/
/* Exported types ------------------------------------------------------------*/
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1))
/**
* @brief CAN init structure definition
*/
typedef struct
{
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
It ranges from 1 to 1024. */
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of @ref CAN_operating_mode */
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
the CAN hardware is allowed to lengthen or
shorten a bit to perform resynchronization.
This parameter can be a value of @ref CAN_synchronisation_jump_width */
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
Segment 1. This parameter can be a value of
@ref CAN_time_quantum_in_bit_segment_1 */
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
This parameter can be set either to ENABLE or DISABLE. */
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
This parameter can be set either to ENABLE or DISABLE. */
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
This parameter can be set either to ENABLE or DISABLE. */
FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.
This parameter can be set either to ENABLE or DISABLE. */
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
This parameter can be set either to ENABLE or DISABLE. */
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
This parameter can be set either to ENABLE or DISABLE. */
} CAN_InitTypeDef;
/**
* @brief CAN filter init structure definition
*/
typedef struct
{
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
This parameter can be set either to ENABLE or DISABLE. */
} CAN_FilterInitTypeDef;
/**
* @brief CAN Tx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t IDE; /*!< Specifies the type of identifier for the message that
will be transmitted. This parameter can be a value
of @ref CAN_identifier_type */
uint8_t RTR; /*!< Specifies the type of frame for the message that will
be transmitted. This parameter can be a value of
@ref CAN_remote_transmission_request */
uint8_t DLC; /*!< Specifies the length of the frame that will be
transmitted. This parameter can be a value between
0 to 8 */
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
to 0xFF. */
} CanTxMsg;
/**
* @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t IDE; /*!< Specifies the type of identifier for the message that
will be received. This parameter can be a value of
@ref CAN_identifier_type */
uint8_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of
@ref CAN_remote_transmission_request */
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter can be a value between 0 to 8 */
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
0xFF. */
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
the mailbox passes through. This parameter can be a
value between 0 to 0xFF */
} CanRxMsg;
/* Exported constants --------------------------------------------------------*/
/** @defgroup CAN_Exported_Constants
* @{
*/
/** @defgroup CAN_InitStatus
* @{
*/
#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
/* Legacy defines */
#define CANINITFAILED CAN_InitStatus_Failed
#define CANINITOK CAN_InitStatus_Success
/**
* @}
*/
/** @defgroup CAN_operating_mode
* @{
*/
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
((MODE) == CAN_Mode_LoopBack)|| \
((MODE) == CAN_Mode_Silent) || \
((MODE) == CAN_Mode_Silent_LoopBack))
/**
* @}
*/
/**
* @defgroup CAN_operating_mode
* @{
*/
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
((MODE) == CAN_OperatingMode_Normal)|| \
((MODE) == CAN_OperatingMode_Sleep))
/**
* @}
*/
/**
* @defgroup CAN_operating_mode_status
* @{
*/
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
/**
* @}
*/
/** @defgroup CAN_synchronisation_jump_width
* @{
*/
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_1
* @{
*/
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_2
* @{
*/
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
/**
* @}
*/
/** @defgroup CAN_clock_prescaler
* @{
*/
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
/**
* @}
*/
/** @defgroup CAN_filter_number
* @{
*/
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
/**
* @}
*/
/** @defgroup CAN_filter_mode
* @{
*/
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
((MODE) == CAN_FilterMode_IdList))
/**
* @}
*/
/** @defgroup CAN_filter_scale
* @{
*/
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
((SCALE) == CAN_FilterScale_32bit))
/**
* @}
*/
/** @defgroup CAN_filter_FIFO
* @{
*/
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
((FIFO) == CAN_FilterFIFO1))
/* Legacy defines */
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
/**
* @}
*/
/** @defgroup CAN_Start_bank_filter_for_slave_CAN
* @{
*/
#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
/**
* @}
*/
/** @defgroup CAN_Tx
* @{
*/
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
/**
* @}
*/
/** @defgroup CAN_identifier_type
* @{
*/
#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
((IDTYPE) == CAN_Id_Extended))
/* Legacy defines */
#define CAN_ID_STD CAN_Id_Standard
#define CAN_ID_EXT CAN_Id_Extended
/**
* @}
*/
/** @defgroup CAN_remote_transmission_request
* @{
*/
#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
/* Legacy defines */
#define CAN_RTR_DATA CAN_RTR_Data
#define CAN_RTR_REMOTE CAN_RTR_Remote
/**
* @}
*/
/** @defgroup CAN_transmit_constants
* @{
*/
#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide
an empty mailbox */
/* Legacy defines */
#define CANTXFAILED CAN_TxStatus_Failed
#define CANTXOK CAN_TxStatus_Ok
#define CANTXPENDING CAN_TxStatus_Pending
#define CAN_NO_MB CAN_TxStatus_NoMailBox
/**
* @}
*/
/** @defgroup CAN_receive_FIFO_number_constants
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
/**
* @}
*/
/** @defgroup CAN_sleep_constants
* @{
*/
#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
/* Legacy defines */
#define CANSLEEPFAILED CAN_Sleep_Failed
#define CANSLEEPOK CAN_Sleep_Ok
/**
* @}
*/
/** @defgroup CAN_wake_up_constants
* @{
*/
#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
/* Legacy defines */
#define CANWAKEUPFAILED CAN_WakeUp_Failed
#define CANWAKEUPOK CAN_WakeUp_Ok
/**
* @}
*/
/**
* @defgroup CAN_Error_Code_constants
* @{
*/
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
/**
* @}
*/
/** @defgroup CAN_flags
* @{
*/
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
and CAN_ClearFlag() functions. */
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
CAN_GetFlagStatus() function. */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
/* Receive Flags */
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
/* Operating Mode Flags */
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
((FLAG) == CAN_FLAG_SLAK ))
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
/**
* @}
*/
/** @defgroup CAN_interrupts
* @{
*/
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
/* Receive Interrupts */
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
/* Operating Mode Interrupts */
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
/* Error Interrupts */
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
/* Flags named as Interrupts : kept only for FW compatibility */
#define CAN_IT_RQCP0 CAN_IT_TME
#define CAN_IT_RQCP1 CAN_IT_TME
#define CAN_IT_RQCP2 CAN_IT_TME
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the CAN configuration to the default reset state *****/
void CAN_DeInit(CAN_TypeDef* CANx);
/* Initialization and Configuration functions *********************************/
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
/* CAN Frames Transmission functions ******************************************/
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
/* CAN Frames Reception functions *********************************************/
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
/* Operation modes functions **************************************************/
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
/* CAN Bus Error management functions *****************************************/
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
/* Interrupts and flags management functions **********************************/
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_CAN_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

426
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_comp.h
View file

@ -1,426 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_comp.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the COMP firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_COMP_H
#define __STM32F30x_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup COMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief COMP Init structure definition
*/
typedef struct
{
uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator.
This parameter can be a value of @ref COMP_InvertingInput */
uint32_t COMP_NonInvertingInput; /*!< Selects the non inverting input of the comparator.
This parameter can be a value of @ref COMP_NonInvertingInput */
uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.
This parameter can be a value of @ref COMP_Output */
uint32_t COMP_BlankingSrce; /*!< Selects the output blanking source of the comparator.
This parameter can be a value of @ref COMP_BlankingSrce */
uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator.
This parameter can be a value of @ref COMP_OutputPoloarity */
uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
This parameter can be a value of @ref COMP_Hysteresis */
uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator
and allows to adjust the speed/consumption.
This parameter can be a value of @ref COMP_Mode */
}COMP_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup COMP_Exported_Constants
* @{
*/
/** @defgroup COMP_Selection
* @{
*/
#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */
#define COMP_Selection_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Selection */
#define COMP_Selection_COMP3 ((uint32_t)0x00000008) /*!< COMP3 Selection */
#define COMP_Selection_COMP4 ((uint32_t)0x0000000C) /*!< COMP4 Selection */
#define COMP_Selection_COMP5 ((uint32_t)0x00000010) /*!< COMP5 Selection */
#define COMP_Selection_COMP6 ((uint32_t)0x00000014) /*!< COMP6 Selection */
#define COMP_Selection_COMP7 ((uint32_t)0x00000018) /*!< COMP7 Selection */
#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
((PERIPH) == COMP_Selection_COMP2) || \
((PERIPH) == COMP_Selection_COMP3) || \
((PERIPH) == COMP_Selection_COMP4) || \
((PERIPH) == COMP_Selection_COMP5) || \
((PERIPH) == COMP_Selection_COMP6) || \
((PERIPH) == COMP_Selection_COMP7))
/**
* @}
*/
/** @defgroup COMP_InvertingInput
* @{
*/
#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
#define COMP_InvertingInput_DAC1OUT1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_OUT1 (PA4) connected to comparator inverting input */
#define COMP_InvertingInput_DAC1OUT2 ((uint32_t)0x00000050) /*!< DAC1_OUT2 (PA5) connected to comparator inverting input */
#define COMP_InvertingInput_IO1 ((uint32_t)0x00000060) /*!< I/O1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
PC0 for COMP7) connected to comparator inverting input */
#define COMP_InvertingInput_IO2 COMP_CSR_COMPxINSEL /*!< I/O2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
PB15 for COMP6) connected to comparator inverting input */
#define COMP_InvertingInput_DAC2OUT1 COMP_CSR_COMPxINSEL_3 /*!< DAC2_OUT1 (PA6) connected to comparator inverting input */
#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
((INPUT) == COMP_InvertingInput_VREFINT) || \
((INPUT) == COMP_InvertingInput_DAC1OUT1) || \
((INPUT) == COMP_InvertingInput_DAC1OUT2) || \
((INPUT) == COMP_InvertingInput_IO1) || \
((INPUT) == COMP_InvertingInput_IO2) || \
((INPUT) == COMP_InvertingInput_DAC2OUT1))
/**
* @}
*/
/** @defgroup COMP_NonInvertingInput
* @{
*/
#define COMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
PA0 for COMP7) connected to comparator non inverting input */
#define COMP_NonInvertingInput_IO2 COMP_CSR_COMPxNONINSEL /*!< I/O2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
#define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_NonInvertingInput_IO1) || \
((INPUT) == COMP_NonInvertingInput_IO2))
/**
* @}
*/
/** @defgroup COMP_Output
* @{
*/
#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
/* Output Redirection common for all comparators COMP1...COMP7 */
#define COMP_Output_TIM1BKIN COMP_CSR_COMPxOUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
#define COMP_Output_TIM1BKIN2 ((uint32_t)0x00000800) /*!< COMP output connected to TIM1 Break Input 2 (BKIN2) */
#define COMP_Output_TIM8BKIN ((uint32_t)0x00000C00) /*!< COMP output connected to TIM8 Break Input (BKIN) */
#define COMP_Output_TIM8BKIN2 ((uint32_t)0x00001000) /*!< COMP output connected to TIM8 Break Input 2 (BKIN2) */
#define COMP_Output_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x00001400) /*!< COMP output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
/* Output Redirection common for COMP1 and COMP2 */
#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00001800) /*!< COMP output connected to TIM1 OCREF Clear */
#define COMP_Output_TIM1IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM1 Input Capture 1 */
#define COMP_Output_TIM2IC4 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 4 */
#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM2 OCREF Clear */
#define COMP_Output_TIM3IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM3 Input Capture 1 */
#define COMP_Output_TIM3OCREFCLR ((uint32_t)0x00002C00) /*!< COMP output connected to TIM3 OCREF Clear */
/* Output Redirection specific to COMP2 */
#define COMP_Output_HRTIM1_FLT6 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT6 */
#define COMP_Output_HRTIM1_EE1_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE1_2*/
#define COMP_Output_HRTIM1_EE6_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE6_2 */
/* Output Redirection specific to COMP3 */
#define COMP_Output_TIM4IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM4 Input Capture 1 */
#define COMP_Output_TIM3IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM3 Input Capture 2 */
#define COMP_Output_TIM15IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 Input Capture 1 */
#define COMP_Output_TIM15BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM15 Break Input (BKIN) */
/* Output Redirection specific to COMP4 */
#define COMP_Output_TIM3IC3 ((uint32_t)0x00001800) /*!< COMP output connected to TIM3 Input Capture 3 */
#define COMP_Output_TIM8OCREFCLR ((uint32_t)0x00001C00) /*!< COMP output connected to TIM8 OCREF Clear */
#define COMP_Output_TIM15IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM15 Input Capture 2 */
#define COMP_Output_TIM4IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 2 */
#define COMP_Output_TIM15OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 OCREF Clear */
#define COMP_Output_HRTIM1_FLT7 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT7 */
#define COMP_Output_HRTIM1_EE2_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE2_2*/
#define COMP_Output_HRTIM1_EE7_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE7_2 */
/* Output Redirection specific to COMP5 */
#define COMP_Output_TIM2IC1 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 1 */
#define COMP_Output_TIM17IC1 ((uint32_t)0x00002000) /*!< COMP output connected to TIM17 Input Capture 1 */
#define COMP_Output_TIM4IC3 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 3 */
#define COMP_Output_TIM16BKIN ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Break Input (BKIN) */
/* Output Redirection specific to COMP6 */
#define COMP_Output_TIM2IC2 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 2 */
#define COMP_Output_COMP6TIM2OCREFCLR ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 OCREF Clear */
#define COMP_Output_TIM16OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM16 OCREF Clear */
#define COMP_Output_TIM16IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Input Capture 1 */
#define COMP_Output_TIM4IC4 ((uint32_t)0x00002C00) /*!< COMP output connected to TIM4 Input Capture 4 */
#define COMP_Output_HRTIM1_FLT8 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT8 */
#define COMP_Output_HRTIM1_EE3_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE3_2*/
#define COMP_Output_HRTIM1_EE8_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE8_2 */
/* Output Redirection specific to COMP7 */
#define COMP_Output_TIM2IC3 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 3 */
#define COMP_Output_TIM1IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM1 Input Capture 2 */
#define COMP_Output_TIM17OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 OCREF Clear */
#define COMP_Output_TIM17BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM16 Break Input (BKIN) */
#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \
((OUTPUT) == COMP_Output_TIM1BKIN) || \
((OUTPUT) == COMP_Output_TIM1IC1) || \
((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
((OUTPUT) == COMP_Output_TIM2IC4) || \
((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
((OUTPUT) == COMP_Output_COMP6TIM2OCREFCLR) || \
((OUTPUT) == COMP_Output_TIM3IC1) || \
((OUTPUT) == COMP_Output_TIM3OCREFCLR) || \
((OUTPUT) == COMP_Output_TIM8BKIN) || \
((OUTPUT) == COMP_Output_TIM1BKIN2) || \
((OUTPUT) == COMP_Output_TIM8BKIN2) || \
((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
((OUTPUT) == COMP_Output_TIM1BKIN2_TIM8BKIN2) || \
((OUTPUT) == COMP_Output_TIM3IC2) || \
((OUTPUT) == COMP_Output_TIM4IC1) || \
((OUTPUT) == COMP_Output_TIM15IC1) || \
((OUTPUT) == COMP_Output_TIM15BKIN) || \
((OUTPUT) == COMP_Output_TIM8OCREFCLR) || \
((OUTPUT) == COMP_Output_TIM3IC3) || \
((OUTPUT) == COMP_Output_TIM4IC1) || \
((OUTPUT) == COMP_Output_TIM15IC1) || \
((OUTPUT) == COMP_Output_TIM2IC1) || \
((OUTPUT) == COMP_Output_TIM4IC3) || \
((OUTPUT) == COMP_Output_TIM16BKIN) || \
((OUTPUT) == COMP_Output_TIM17IC1) || \
((OUTPUT) == COMP_Output_TIM2IC2) || \
((OUTPUT) == COMP_Output_TIM16IC1) || \
((OUTPUT) == COMP_Output_TIM4IC4) || \
((OUTPUT) == COMP_Output_TIM16OCREFCLR) || \
((OUTPUT) == COMP_Output_TIM2IC3) || \
((OUTPUT) == COMP_Output_TIM1IC2) || \
((OUTPUT) == COMP_Output_TIM17BKIN) || \
((OUTPUT) == COMP_Output_TIM17OCREFCLR) || \
((OUTPUT) == COMP_Output_HRTIM1_FLT6) || \
((OUTPUT) == COMP_Output_HRTIM1_EE1_2) || \
((OUTPUT) == COMP_Output_HRTIM1_EE6_2) || \
((OUTPUT) == COMP_Output_HRTIM1_FLT7) || \
((OUTPUT) == COMP_Output_HRTIM1_EE2_2) || \
((OUTPUT) == COMP_Output_HRTIM1_EE7_2) || \
((OUTPUT) == COMP_Output_HRTIM1_FLT8) || \
((OUTPUT) == COMP_Output_HRTIM1_EE3_2) || \
((OUTPUT) == COMP_Output_HRTIM1_EE8_2))
/**
* @}
*/
/** @defgroup COMP_BlankingSrce
* @{
*/
/* No blanking source can be selected for all comparators */
#define COMP_BlankingSrce_None ((uint32_t)0x00000000) /*!< No blanking source */
/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
#define COMP_BlankingSrce_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for compartor */
/* Blanking source common for COMP1 and COMP2 */
#define COMP_BlankingSrce_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC5 selected as blanking source for compartor */
/* Blanking source common for COMP1, COMP2 and COMP5 */
#define COMP_BlankingSrce_TIM3OC3 ((uint32_t)0x000C0000) /*!< TIM2 OC3 selected as blanking source for compartor */
/* Blanking source common for COMP3 and COMP6 */
#define COMP_BlankingSrce_TIM2OC4 ((uint32_t)0x000C0000) /*!< TIM2 OC4 selected as blanking source for compartor */
/* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
#define COMP_BlankingSrce_TIM8OC5 COMP_CSR_COMPxBLANKING_1 /*!< TIM8 OC5 selected as blanking source for compartor */
/* Blanking source for COMP4 */
#define COMP_BlankingSrce_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for compartor */
#define COMP_BlankingSrce_TIM15OC1 ((uint32_t)0x000C0000) /*!< TIM15 OC1 selected as blanking source for compartor */
/* Blanking source common for COMP6 and COMP7 */
#define COMP_BlankingSrce_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for compartor */
#define IS_COMP_BLANKING_SOURCE(SOURCE) (((SOURCE) == COMP_BlankingSrce_None) || \
((SOURCE) == COMP_BlankingSrce_TIM1OC5) || \
((SOURCE) == COMP_BlankingSrce_TIM2OC3) || \
((SOURCE) == COMP_BlankingSrce_TIM3OC3) || \
((SOURCE) == COMP_BlankingSrce_TIM2OC4) || \
((SOURCE) == COMP_BlankingSrce_TIM8OC5) || \
((SOURCE) == COMP_BlankingSrce_TIM3OC4) || \
((SOURCE) == COMP_BlankingSrce_TIM15OC1) || \
((SOURCE) == COMP_BlankingSrce_TIM15OC2))
/**
* @}
*/
/** @defgroup COMP_OutputPoloarity
* @{
*/
#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
#define COMP_OutputPol_Inverted COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \
((POL) == COMP_OutputPol_Inverted))
/**
* @}
*/
/** @defgroup COMP_Hysteresis
* @{
*/
/* Please refer to the electrical characteristics in the device datasheet for
the hysteresis level */
#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */
#define COMP_Hysteresis_Low COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
#define COMP_Hysteresis_Medium COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
#define COMP_Hysteresis_High COMP_CSR_COMPxHYST /*!< Hysteresis level high */
#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \
((HYSTERESIS) == COMP_Hysteresis_Low) || \
((HYSTERESIS) == COMP_Hysteresis_Medium) || \
((HYSTERESIS) == COMP_Hysteresis_High))
/**
* @}
*/
/** @defgroup COMP_Mode
* @{
*/
/* Please refer to the electrical characteristics in the device datasheet for
the power consumption values */
#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */
#define COMP_Mode_MediumSpeed COMP_CSR_COMPxMODE_0 /*!< Medium Speed */
#define COMP_Mode_LowPower COMP_CSR_COMPxMODE_1 /*!< Low power mode */
#define COMP_Mode_UltraLowPower COMP_CSR_COMPxMODE /*!< Ultra-low power mode */
#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \
((MODE) == COMP_Mode_LowPower) || \
((MODE) == COMP_Mode_MediumSpeed) || \
((MODE) == COMP_Mode_HighSpeed))
/**
* @}
*/
/** @defgroup COMP_OutputLevel
* @{
*/
/* When output polarity is not inverted, comparator output is high when
the non-inverting input is at a higher voltage than the inverting input */
#define COMP_OutputLevel_High COMP_CSR_COMPxOUT
/* When output polarity is not inverted, comparator output is low when
the non-inverting input is at a lower voltage than the inverting input*/
#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup COMP_WindowMode
* @{
*/
#define IS_COMP_WINDOW(WINDOW) (((WINDOW) == COMP_Selection_COMP2) || \
((WINDOW) == COMP_Selection_COMP4) || \
((WINDOW) == COMP_Selection_COMP6))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the COMP configuration to the default reset state ****/
void COMP_DeInit(uint32_t COMP_Selection);
/* Initialization and Configuration functions *********************************/
void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState);
uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
/* Window mode control function ***********************************************/
void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState);
/* COMP configuration locking function ****************************************/
void COMP_LockConfig(uint32_t COMP_Selection);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F30x_COMP_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

121
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_crc.h
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@ -1,121 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_crc.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the CRC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_CRC_H
#define __STM32F30x_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/*!< Includes ----------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_ReverseInputData
* @{
*/
#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
((DATA) == CRC_ReverseInputData_8bits) || \
((DATA) == CRC_ReverseInputData_16bits) || \
((DATA) == CRC_ReverseInputData_32bits))
/**
* @}
*/
/** @defgroup CRC_PolynomialSize
* @{
*/
#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */
#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */
#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */
#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \
((SIZE) == CRC_PolSize_8) || \
((SIZE) == CRC_PolSize_16) || \
((SIZE) == CRC_PolSize_32))
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Configuration of the CRC computation unit **********************************/
void CRC_DeInit(void);
void CRC_ResetDR(void);
void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize);
void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
void CRC_ReverseOutputDataCmd(FunctionalState NewState);
void CRC_SetInitRegister(uint32_t CRC_InitValue);
void CRC_SetPolynomial(uint32_t CRC_Pol);
/* CRC computation ************************************************************/
uint32_t CRC_CalcCRC(uint32_t CRC_Data);
uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data);
uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data);
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
uint32_t CRC_GetCRC(void);
/* Independent register (IDR) access (write/read) *****************************/
void CRC_SetIDRegister(uint8_t CRC_IDValue);
uint8_t CRC_GetIDRegister(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_CRC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

322
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dac.h
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/**
******************************************************************************
* @file stm32f30x_dac.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_DAC_H
#define __STM32F30x_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
#define DAC_CR_DMAUDRIE ((uint32_t)0x00002000) /*!< DAC channel DMA underrun interrupt enable */
/**
* @brief DAC Init structure definition
*/
typedef struct
{
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
are generated, or whether no wave is generated.
This parameter can be a value of @ref DAC_wave_generation */
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
the maximum amplitude triangle generation for the DAC channel.
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
uint32_t DAC_Buffer_Switch; /*!< Specifies whether the DAC channel output buffer is enabled or disabled or
the DAC channel output switch is enabled or disabled.
This parameter can be a value of @ref DAC_buffer_switch */
}DAC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_Exported_Constants
* @{
*/
#define IS_DAC_ALL_PERIPH(PERIPH) (((PERIPH) == DAC1) || \
((PERIPH) == DAC2))
#define IS_DAC_LIST1_PERIPH(PERIPH) (((PERIPH) == DAC1))
/** @defgroup DAC_trigger_selection
* @{
*/
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC1 channel1/2 */
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
#define DAC_Trigger_HRTIM1_DACTRG1 ((uint32_t)0x0000001C) /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC1 channel1/2 */
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_HRTIM1_DACTRG2 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC1 channel1/2 */
#define DAC_Trigger_HRTIM1_DACTRG3 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC2 channel1 */
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC1/2 channel1/2 */
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC1/2 channel1/2 */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
((TRIGGER) == DAC_Trigger_T3_TRGO) || \
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
((TRIGGER) == DAC_Trigger_T15_TRGO) || \
((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG1)|| \
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG2)|| \
((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG3)|| \
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
((TRIGGER) == DAC_Trigger_Software))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
((WAVE) == DAC_WaveGeneration_Noise) || \
((WAVE) == DAC_WaveGeneration_Triangle))
/**
* @}
*/
/** @defgroup DAC_lfsrunmask_triangleamplitude
* @{
*/
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
((VALUE) == DAC_TriangleAmplitude_1) || \
((VALUE) == DAC_TriangleAmplitude_3) || \
((VALUE) == DAC_TriangleAmplitude_7) || \
((VALUE) == DAC_TriangleAmplitude_15) || \
((VALUE) == DAC_TriangleAmplitude_31) || \
((VALUE) == DAC_TriangleAmplitude_63) || \
((VALUE) == DAC_TriangleAmplitude_127) || \
((VALUE) == DAC_TriangleAmplitude_255) || \
((VALUE) == DAC_TriangleAmplitude_511) || \
((VALUE) == DAC_TriangleAmplitude_1023) || \
((VALUE) == DAC_TriangleAmplitude_2047) || \
((VALUE) == DAC_TriangleAmplitude_4095))
/**
* @}
*/
/** @defgroup DAC_buffer_switch
* @{
*/
#define DAC_BufferSwitch_Disable ((uint32_t)0x00000000)
#define DAC_BufferSwitch_Enable ((uint32_t)0x00000002)
#define IS_DAC_BUFFER_SWITCH_STATE(STATE) (((STATE) == DAC_BufferSwitch_Enable) || \
((STATE) == DAC_BufferSwitch_Disable))
/**
* @}
*/
/** @defgroup DAC_Channel_selection
* @{
*/
#define DAC_Channel_1 ((uint32_t)0x00000000)
#define DAC_Channel_2 ((uint32_t)0x00000010)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
((CHANNEL) == DAC_Channel_2))
/**
* @}
*/
/** @defgroup DAC_data_alignement
* @{
*/
#define DAC_Align_12b_R ((uint32_t)0x00000000)
#define DAC_Align_12b_L ((uint32_t)0x00000004)
#define DAC_Align_8b_R ((uint32_t)0x00000008)
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
((ALIGN) == DAC_Align_12b_L) || \
((ALIGN) == DAC_Align_8b_R))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_Wave_Noise ((uint32_t)0x00000040)
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
((WAVE) == DAC_Wave_Triangle))
/**
* @}
*/
/** @defgroup DAC_data
* @{
*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
/** @defgroup DAC_interrupts_definition
* @{
*/
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
/**
* @}
*/
/** @defgroup DAC_flags_definition
* @{
*/
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the DAC configuration to the default reset state *****/
void DAC_DeInit(DAC_TypeDef* DACx);
/* DAC channels configuration: trigger, output buffer, data format functions */
void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState);
void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel);
/* DMA management functions ***************************************************/
void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F30x_DAC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dbgmcu.h
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@ -1,108 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_dbgmcu.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the DBGMCU firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_DBGMCU_H
#define __STM32F30x_DBGMCU_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup DBGMCU
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DBGMCU_Exported_Constants
* @{
*/
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
#define DBGMCU_STOP ((uint32_t)0x00000002)
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFD9FE3C8) == 0x00) && ((PERIPH) != 0x00))
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
#define DBGMCU_TIM15_STOP ((uint32_t)0x00000004)
#define DBGMCU_TIM16_STOP ((uint32_t)0x00000008)
#define DBGMCU_TIM17_STOP ((uint32_t)0x00000010)
#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE0) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Device and Revision ID management functions ********************************/
uint32_t DBGMCU_GetREVID(void);
uint32_t DBGMCU_GetDEVID(void);
/* Peripherals Configuration functions ****************************************/
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_DBGMCU_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

436
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dma.h
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@ -1,436 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_dma.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_DMA_H
#define __STM32F30x_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief DMA Init structures definition
*/
typedef struct
{
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
This parameter can be a value of @ref DMA_data_transfer_direction */
uint16_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
The data unit is equal to the configuration set in DMA_PeripheralDataSize
or DMA_MemoryDataSize members depending in the transfer direction. */
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
This parameter can be a value of @ref DMA_memory_incremented_mode */
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_peripheral_data_size */
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_memory_data_size */
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_circular_normal_mode
@note: The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_priority_level */
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
This parameter can be a value of @ref DMA_memory_to_memory */
}DMA_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants
* @{
*/
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
((PERIPH) == DMA1_Channel2) || \
((PERIPH) == DMA1_Channel3) || \
((PERIPH) == DMA1_Channel4) || \
((PERIPH) == DMA1_Channel5) || \
((PERIPH) == DMA1_Channel6) || \
((PERIPH) == DMA1_Channel7) || \
((PERIPH) == DMA2_Channel1) || \
((PERIPH) == DMA2_Channel2) || \
((PERIPH) == DMA2_Channel3) || \
((PERIPH) == DMA2_Channel4) || \
((PERIPH) == DMA2_Channel5))
/** @defgroup DMA_data_transfer_direction
* @{
*/
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
#define DMA_DIR_PeripheralDST DMA_CCR_DIR
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
((DIR) == DMA_DIR_PeripheralDST))
/**
* @}
*/
/** @defgroup DMA_peripheral_incremented_mode
* @{
*/
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
#define DMA_PeripheralInc_Enable DMA_CCR_PINC
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
((STATE) == DMA_PeripheralInc_Enable))
/**
* @}
*/
/** @defgroup DMA_memory_incremented_mode
* @{
*/
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
#define DMA_MemoryInc_Enable DMA_CCR_MINC
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
((STATE) == DMA_MemoryInc_Enable))
/**
* @}
*/
/** @defgroup DMA_peripheral_data_size
* @{
*/
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
((SIZE) == DMA_PeripheralDataSize_Word))
/**
* @}
*/
/** @defgroup DMA_memory_data_size
* @{
*/
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
((SIZE) == DMA_MemoryDataSize_Word))
/**
* @}
*/
/** @defgroup DMA_circular_normal_mode
* @{
*/
#define DMA_Mode_Normal ((uint32_t)0x00000000)
#define DMA_Mode_Circular DMA_CCR_CIRC
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
/**
* @}
*/
/** @defgroup DMA_priority_level
* @{
*/
#define DMA_Priority_VeryHigh DMA_CCR_PL
#define DMA_Priority_High DMA_CCR_PL_1
#define DMA_Priority_Medium DMA_CCR_PL_0
#define DMA_Priority_Low ((uint32_t)0x00000000)
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
((PRIORITY) == DMA_Priority_High) || \
((PRIORITY) == DMA_Priority_Medium) || \
((PRIORITY) == DMA_Priority_Low))
/**
* @}
*/
/** @defgroup DMA_memory_to_memory
* @{
*/
#define DMA_M2M_Disable ((uint32_t)0x00000000)
#define DMA_M2M_Enable DMA_CCR_MEM2MEM
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
/**
* @}
*/
/** @defgroup DMA_interrupts_definition
* @{
*/
#define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004)
#define DMA_IT_TE ((uint32_t)0x00000008)
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
/**
* @}
*/
/** @defgroup DMA_flags_definition
* @{
*/
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the DMA configuration to the default reset state ******/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
/* Initialization and Configuration functions *********************************/
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
/* Data Counter functions******************************************************/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
/* Interrupts and flags management functions **********************************/
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
void DMA_ClearFlag(uint32_t DMAy_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F30x_DMA_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_exti.h
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@ -1,234 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_exti.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the EXTI
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_EXTI_H
#define __STM32F30x_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief EXTI mode enumeration
*/
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
}EXTIMode_TypeDef;
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
}EXTITrigger_TypeDef;
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
((TRIGGER) == EXTI_Trigger_Falling) || \
((TRIGGER) == EXTI_Trigger_Rising_Falling))
/**
* @brief EXTI Init Structure definition
*/
typedef struct
{
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTITrigger_TypeDef */
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
}EXTI_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants
* @{
*/
/** @defgroup EXTI_Lines
* @{
*/
#define EXTI_Line0 ((uint32_t)0x00) /*!< External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x01) /*!< External interrupt line 1 */
#define EXTI_Line2 ((uint32_t)0x02) /*!< External interrupt line 2 */
#define EXTI_Line3 ((uint32_t)0x03) /*!< External interrupt line 3 */
#define EXTI_Line4 ((uint32_t)0x04) /*!< External interrupt line 4 */
#define EXTI_Line5 ((uint32_t)0x05) /*!< External interrupt line 5 */
#define EXTI_Line6 ((uint32_t)0x06) /*!< External interrupt line 6 */
#define EXTI_Line7 ((uint32_t)0x07) /*!< External interrupt line 7 */
#define EXTI_Line8 ((uint32_t)0x08) /*!< External interrupt line 8 */
#define EXTI_Line9 ((uint32_t)0x09) /*!< External interrupt line 9 */
#define EXTI_Line10 ((uint32_t)0x0A) /*!< External interrupt line 10 */
#define EXTI_Line11 ((uint32_t)0x0B) /*!< External interrupt line 11 */
#define EXTI_Line12 ((uint32_t)0x0C) /*!< External interrupt line 12 */
#define EXTI_Line13 ((uint32_t)0x0D) /*!< External interrupt line 13 */
#define EXTI_Line14 ((uint32_t)0x0E) /*!< External interrupt line 14 */
#define EXTI_Line15 ((uint32_t)0x0F) /*!< External interrupt line 15 */
#define EXTI_Line16 ((uint32_t)0x10) /*!< External interrupt line 16
Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x11) /*!< Internal interrupt line 17
Connected to the RTC Alarm
event */
#define EXTI_Line18 ((uint32_t)0x12) /*!< Internal interrupt line 18
Connected to the USB Device
Wakeup from suspend event */
#define EXTI_Line19 ((uint32_t)0x13) /*!< Internal interrupt line 19
Connected to the RTC Tamper
and Time Stamp events */
#define EXTI_Line20 ((uint32_t)0x14) /*!< Internal interrupt line 20
Connected to the RTC wakeup
event */
#define EXTI_Line21 ((uint32_t)0x15) /*!< Internal interrupt line 21
Connected to the Comparator 1
event */
#define EXTI_Line22 ((uint32_t)0x16) /*!< Internal interrupt line 22
Connected to the Comparator 2
event */
#define EXTI_Line23 ((uint32_t)0x17) /*!< Internal interrupt line 23
Connected to the I2C1 wakeup
event */
#define EXTI_Line24 ((uint32_t)0x18) /*!< Internal interrupt line 24
Connected to the I2C2 wakeup
event */
#define EXTI_Line25 ((uint32_t)0x19) /*!< Internal interrupt line 25
Connected to the USART1 wakeup
event */
#define EXTI_Line26 ((uint32_t)0x1A) /*!< Internal interrupt line 26
Connected to the USART2 wakeup
event */
#define EXTI_Line27 ((uint32_t)0x1B) /*!< Internal interrupt line 27
reserved */
#define EXTI_Line28 ((uint32_t)0x1C) /*!< Internal interrupt line 28
Connected to the USART3 wakeup
event */
#define EXTI_Line29 ((uint32_t)0x1D) /*!< Internal interrupt line 29
Connected to the Comparator 3
event */
#define EXTI_Line30 ((uint32_t)0x1E) /*!< Internal interrupt line 30
Connected to the Comparator 4
event */
#define EXTI_Line31 ((uint32_t)0x1F) /*!< Internal interrupt line 31
Connected to the Comparator 5
event */
#define EXTI_Line32 ((uint32_t)0x20) /*!< Internal interrupt line 32
Connected to the Comparator 6
event */
#define EXTI_Line33 ((uint32_t)0x21) /*!< Internal interrupt line 33
Connected to the Comparator 7
event */
#define EXTI_Line34 ((uint32_t)0x22) /*!< Internal interrupt line 34
Connected to the USART4 wakeup
event */
#define EXTI_Line35 ((uint32_t)0x23) /*!< Internal interrupt line 35
Connected to the USART5 wakeup
event */
#define IS_EXTI_LINE_ALL(LINE) ((LINE) <= 0x23)
#define IS_EXTI_LINE_EXT(LINE) (((LINE) <= 0x16) || (((LINE) == EXTI_Line29) || ((LINE) == EXTI_Line30) || \
((LINE) == EXTI_Line31) || ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33)))
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line29) || \
((LINE) == EXTI_Line30) || ((LINE) == EXTI_Line31) || \
((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the EXTI configuration to the default reset state *****/
void EXTI_DeInit(void);
/* Initialization and Configuration functions *********************************/
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
/* Interrupts and flags management functions **********************************/
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
void EXTI_ClearFlag(uint32_t EXTI_Line);
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_EXTI_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

329
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_flash.h
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@ -1,329 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_flash.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_FLASH_H
#define __STM32F30x_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief FLASH Status
*/
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_WRP,
FLASH_ERROR_PROGRAM,
FLASH_COMPLETE,
FLASH_TIMEOUT
}FLASH_Status;
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants
* @{
*/
/** @defgroup Flash_Latency
* @{
*/
#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
#define FLASH_Latency_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
#define FLASH_Latency_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \
((LATENCY) == FLASH_Latency_2))
/**
* @}
*/
/** @defgroup FLASH_Interrupts
* @{
*/
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
/**
* @}
*/
/** @defgroup FLASH_Address
* @{
*/
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
/**
* @}
*/
/** @defgroup FLASH_OB_DATA_ADDRESS
* @{
*/
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
/**
* @}
*/
/** @defgroup Option_Bytes_Write_Protection
* @{
*/
#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
#define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
/**
* @}
*/
/** @defgroup Option_Bytes_Read_Protection
* @{
*/
/**
* @brief Read Protection Level
*/
#define OB_RDP_Level_0 ((uint8_t)0xAA)
#define OB_RDP_Level_1 ((uint8_t)0xBB)
/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
it's no more possible to go back to level 1 or 0 */
#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
((LEVEL) == OB_RDP_Level_1))/*||\
((LEVEL) == OB_RDP_Level_2))*/
/**
* @}
*/
/** @defgroup Option_Bytes_IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STOP
* @{
*/
#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STDBY
* @{
*/
#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
/**
* @}
*/
/** @defgroup Option_Bytes_BOOT1
* @{
*/
#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
/**
* @}
*/
/** @defgroup Option_Bytes_VDDA_Analog_Monitoring
* @{
*/
#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
/**
* @}
*/
/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
* @{
*/
#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
/**
* @}
*/
/** @defgroup FLASH_Flags
* @{
*/
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
/**
* @}
*/
/** @defgroup Timeout_definition
* @{
*/
#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* FLASH Interface configuration functions ************************************/
void FLASH_SetLatency(uint32_t FLASH_Latency);
void FLASH_HalfCycleAccessCmd(FunctionalState NewState);
void FLASH_PrefetchBufferCmd(FunctionalState NewState);
/* FLASH Memory Programming functions *****************************************/
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
/* Option Bytes Programming functions *****************************************/
void FLASH_OB_Unlock(void);
void FLASH_OB_Lock(void);
void FLASH_OB_Launch(void);
FLASH_Status FLASH_OB_Erase(void);
FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
uint8_t FLASH_OB_GetUser(void);
uint32_t FLASH_OB_GetWRP(void);
FlagStatus FLASH_OB_GetRDP(void);
/* Interrupts and flags management functions **********************************/
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_FLASH_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

400
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_gpio.h
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@ -1,400 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_gpio.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_GPIO_H
#define __STM32F30x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
((PERIPH) == GPIOB) || \
((PERIPH) == GPIOC) || \
((PERIPH) == GPIOD) || \
((PERIPH) == GPIOE) || \
((PERIPH) == GPIOF))
#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
((PERIPH) == GPIOB) || \
((PERIPH) == GPIOD))
/** @defgroup Configuration_Mode_enumeration
* @{
*/
typedef enum
{
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
}GPIOMode_TypeDef;
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
/**
* @}
*/
/** @defgroup Output_type_enumeration
* @{
*/
typedef enum
{
GPIO_OType_PP = 0x00,
GPIO_OType_OD = 0x01
}GPIOOType_TypeDef;
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
/**
* @}
*/
/** @defgroup Output_Maximum_frequency_enumeration
* @{
*/
typedef enum
{
GPIO_Speed_Level_1 = 0x01, /*!< Fast Speed */
GPIO_Speed_Level_2 = 0x02, /*!< Meduim Speed */
GPIO_Speed_Level_3 = 0x03 /*!< High Speed */
}GPIOSpeed_TypeDef;
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
((SPEED) == GPIO_Speed_Level_3))
/**
* @}
*/
/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
* @{
*/
typedef enum
{
GPIO_PuPd_NOPULL = 0x00,
GPIO_PuPd_UP = 0x01,
GPIO_PuPd_DOWN = 0x02
}GPIOPuPd_TypeDef;
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
((PUPD) == GPIO_PuPd_DOWN))
/**
* @}
*/
/** @defgroup Bit_SET_and_Bit_RESET_enumeration
* @{
*/
typedef enum
{
Bit_RESET = 0,
Bit_SET
}BitAction;
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
/**
* @}
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
This parameter can be a value of @ref GPIOOType_TypeDef */
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
This parameter can be a value of @ref GPIOPuPd_TypeDef */
}GPIO_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants
* @{
*/
/** @defgroup GPIO_pins_define
* @{
*/
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \
((PIN) == GPIO_Pin_2) || \
((PIN) == GPIO_Pin_3) || \
((PIN) == GPIO_Pin_4) || \
((PIN) == GPIO_Pin_5) || \
((PIN) == GPIO_Pin_6) || \
((PIN) == GPIO_Pin_7) || \
((PIN) == GPIO_Pin_8) || \
((PIN) == GPIO_Pin_9) || \
((PIN) == GPIO_Pin_10) || \
((PIN) == GPIO_Pin_11) || \
((PIN) == GPIO_Pin_12) || \
((PIN) == GPIO_Pin_13) || \
((PIN) == GPIO_Pin_14) || \
((PIN) == GPIO_Pin_15))
/**
* @}
*/
/** @defgroup GPIO_Pin_sources
* @{
*/
#define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07)
#define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A)
#define GPIO_PinSource11 ((uint8_t)0x0B)
#define GPIO_PinSource12 ((uint8_t)0x0C)
#define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F)
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
((PINSOURCE) == GPIO_PinSource1) || \
((PINSOURCE) == GPIO_PinSource2) || \
((PINSOURCE) == GPIO_PinSource3) || \
((PINSOURCE) == GPIO_PinSource4) || \
((PINSOURCE) == GPIO_PinSource5) || \
((PINSOURCE) == GPIO_PinSource6) || \
((PINSOURCE) == GPIO_PinSource7) || \
((PINSOURCE) == GPIO_PinSource8) || \
((PINSOURCE) == GPIO_PinSource9) || \
((PINSOURCE) == GPIO_PinSource10) || \
((PINSOURCE) == GPIO_PinSource11) || \
((PINSOURCE) == GPIO_PinSource12) || \
((PINSOURCE) == GPIO_PinSource13) || \
((PINSOURCE) == GPIO_PinSource14) || \
((PINSOURCE) == GPIO_PinSource15))
/**
* @}
*/
/** @defgroup GPIO_Alternate_function_selection_define
* @{
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF_0 ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT,
MCO, NJTRST, TRACED, TRACECK */
/**
* @brief AF 1 selection
*/
#define GPIO_AF_1 ((uint8_t)0x01) /* OUT, TIM2, TIM15, TIM16, TIM17 */
/**
* @brief AF 2 selection
*/
#define GPIO_AF_2 ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 */
/**
* @brief AF 3 selection
*/
#define GPIO_AF_3 ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch, HRTIM1 */
/**
* @brief AF 4 selection
*/
#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */
/**
* @brief AF 5 selection
*/
#define GPIO_AF_5 ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */
/**
* @brief AF 6 selection
*/
#define GPIO_AF_6 ((uint8_t)0x06) /* IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */
/**
* @brief AF 7 selection
*/
#define GPIO_AF_7 ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT,
USART1, USART2, USART3 */
/**
* @brief AF 8 selection
*/
#define GPIO_AF_8 ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT,
COMP5_OUT, COMP6_OUT */
/**
* @brief AF 9 selection
*/
#define GPIO_AF_9 ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */
/**
* @brief AF 10 selection
*/
#define GPIO_AF_10 ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */
/**
* @brief AF 11 selection
*/
#define GPIO_AF_11 ((uint8_t)0x0B) /* TIM1, TIM8 */
/**
* @brief AF 12 selection
*/
#define GPIO_AF_12 ((uint8_t)0x0C) /* TIM1, HRTIM1 */
/**
* @brief AF 13 selection
*/
#define GPIO_AF_13 ((uint8_t)0x0D) /* HRTIM1, AOP2_OUT */
/**
* @brief AF 14 selection
*/
#define GPIO_AF_14 ((uint8_t)0x0E) /* USBDM, USBDP */
/**
* @brief AF 15 selection
*/
#define GPIO_AF_15 ((uint8_t)0x0F) /* OUT */
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
((AF) == GPIO_AF_12)||((AF) == GPIO_AF_13)||\
((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
/**
* @}
*/
/** @defgroup GPIO_Speed_Legacy
* @{
*/
#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */
#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */
#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the GPIO configuration to the default reset state *****/
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
/* Initialization and Configuration functions *********************************/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
/* GPIO Read and Write functions **********************************************/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
/* GPIO Alternate functions configuration functions ***************************/
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_GPIO_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_hrtim.h
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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_i2c.h
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/**
******************************************************************************
* @file stm32f30x_i2c.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_I2C_H
#define __STM32F30x_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief I2C Init structure definition
*/
typedef struct
{
uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization
section in Reference manual*/
uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.
This parameter can be a value of @ref I2C_Analog_Filter */
uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.
This parameter can be a number between 0x00 and 0x0F */
uint32_t I2C_Mode; /*!< Specifies the I2C mode.
This parameter can be a value of @ref I2C_mode */
uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.
This parameter can be a 7-bit or 10-bit address */
uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.
This parameter can be a value of @ref I2C_acknowledgement */
uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */
}I2C_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants
* @{
*/
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
((PERIPH) == I2C2))
/** @defgroup I2C_Analog_Filter
* @{
*/
#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)
#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \
((FILTER) == I2C_AnalogFilter_Disable))
/**
* @}
*/
/** @defgroup I2C_Digital_Filter
* @{
*/
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
/**
* @}
*/
/** @defgroup I2C_mode
* @{
*/
#define I2C_Mode_I2C ((uint32_t)0x00000000)
#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN
#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
((MODE) == I2C_Mode_SMBusDevice) || \
((MODE) == I2C_Mode_SMBusHost))
/**
* @}
*/
/** @defgroup I2C_acknowledgement
* @{
*/
#define I2C_Ack_Enable ((uint32_t)0x00000000)
#define I2C_Ack_Disable I2C_CR2_NACK
#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \
((ACK) == I2C_Ack_Disable))
/**
* @}
*/
/** @defgroup I2C_acknowledged_address
* @{
*/
#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
/**
* @}
*/
/** @defgroup I2C_own_address1
* @{
*/
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
/**
* @}
*/
/** @defgroup I2C_transfer_direction
* @{
*/
#define I2C_Direction_Transmitter ((uint16_t)0x0000)
#define I2C_Direction_Receiver ((uint16_t)0x0400)
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
((DIRECTION) == I2C_Direction_Receiver))
/**
* @}
*/
/** @defgroup I2C_DMA_transfer_requests
* @{
*/
#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN
#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN
#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
/**
* @}
*/
/** @defgroup I2C_slave_address
* @{
*/
#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
/**
* @}
*/
/** @defgroup I2C_own_address2
* @{
*/
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
/**
* @}
*/
/** @defgroup I2C_own_address2_mask
* @{
*/
#define I2C_OA2_NoMask ((uint8_t)0x00)
#define I2C_OA2_Mask01 ((uint8_t)0x01)
#define I2C_OA2_Mask02 ((uint8_t)0x02)
#define I2C_OA2_Mask03 ((uint8_t)0x03)
#define I2C_OA2_Mask04 ((uint8_t)0x04)
#define I2C_OA2_Mask05 ((uint8_t)0x05)
#define I2C_OA2_Mask06 ((uint8_t)0x06)
#define I2C_OA2_Mask07 ((uint8_t)0x07)
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \
((MASK) == I2C_OA2_Mask01) || \
((MASK) == I2C_OA2_Mask02) || \
((MASK) == I2C_OA2_Mask03) || \
((MASK) == I2C_OA2_Mask04) || \
((MASK) == I2C_OA2_Mask05) || \
((MASK) == I2C_OA2_Mask06) || \
((MASK) == I2C_OA2_Mask07))
/**
* @}
*/
/** @defgroup I2C_timeout
* @{
*/
#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
/**
* @}
*/
/** @defgroup I2C_registers
* @{
*/
#define I2C_Register_CR1 ((uint8_t)0x00)
#define I2C_Register_CR2 ((uint8_t)0x04)
#define I2C_Register_OAR1 ((uint8_t)0x08)
#define I2C_Register_OAR2 ((uint8_t)0x0C)
#define I2C_Register_TIMINGR ((uint8_t)0x10)
#define I2C_Register_TIMEOUTR ((uint8_t)0x14)
#define I2C_Register_ISR ((uint8_t)0x18)
#define I2C_Register_ICR ((uint8_t)0x1C)
#define I2C_Register_PECR ((uint8_t)0x20)
#define I2C_Register_RXDR ((uint8_t)0x24)
#define I2C_Register_TXDR ((uint8_t)0x28)
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
((REGISTER) == I2C_Register_CR2) || \
((REGISTER) == I2C_Register_OAR1) || \
((REGISTER) == I2C_Register_OAR2) || \
((REGISTER) == I2C_Register_TIMINGR) || \
((REGISTER) == I2C_Register_TIMEOUTR) || \
((REGISTER) == I2C_Register_ISR) || \
((REGISTER) == I2C_Register_ICR) || \
((REGISTER) == I2C_Register_PECR) || \
((REGISTER) == I2C_Register_RXDR) || \
((REGISTER) == I2C_Register_TXDR))
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup I2C_flags_definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_NACKF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
((FLAG) == I2C_FLAG_BUSY))
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @{
*/
#define I2C_IT_TXIS I2C_ISR_TXIS
#define I2C_IT_RXNE I2C_ISR_RXNE
#define I2C_IT_ADDR I2C_ISR_ADDR
#define I2C_IT_NACKF I2C_ISR_NACKF
#define I2C_IT_STOPF I2C_ISR_STOPF
#define I2C_IT_TC I2C_ISR_TC
#define I2C_IT_TCR I2C_ISR_TCR
#define I2C_IT_BERR I2C_ISR_BERR
#define I2C_IT_ARLO I2C_ISR_ARLO
#define I2C_IT_OVR I2C_ISR_OVR
#define I2C_IT_PECERR I2C_ISR_PECERR
#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_IT_ALERT I2C_ISR_ALERT
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
((IT) == I2C_IT_ALERT))
/**
* @}
*/
/** @defgroup I2C_ReloadEndMode_definition
* @{
*/
#define I2C_Reload_Mode I2C_CR2_RELOAD
#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND
#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)
#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \
((MODE) == I2C_AutoEnd_Mode) || \
((MODE) == I2C_SoftEnd_Mode))
/**
* @}
*/
/** @defgroup I2C_StartStopMode_definition
* @{
*/
#define I2C_No_StartStop ((uint32_t)0x00000000)
#define I2C_Generate_Stop I2C_CR2_STOP
#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_Generate_Start_Write I2C_CR2_START
#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \
((MODE) == I2C_Generate_Start_Read) || \
((MODE) == I2C_Generate_Start_Write) || \
((MODE) == I2C_No_StartStop))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Initialization and Configuration functions *********************************/
void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
/* Communications handling functions ******************************************/
void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
/* SMBUS management functions ************************************************/
void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
/* I2C registers management functions *****************************************/
uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
/* Data transfers management functions ****************************************/
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
/* DMA transfers management functions *****************************************/
void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F30x_I2C_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f30x_iwdg.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_IWDG_H
#define __STM32F30x_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup IWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Constants
* @{
*/
/** @defgroup IWDG_WriteAccess
* @{
*/
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
((ACCESS) == IWDG_WriteAccess_Disable))
/**
* @}
*/
/** @defgroup IWDG_prescaler
* @{
*/
#define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_8 ((uint8_t)0x01)
#define IWDG_Prescaler_16 ((uint8_t)0x02)
#define IWDG_Prescaler_32 ((uint8_t)0x03)
#define IWDG_Prescaler_64 ((uint8_t)0x04)
#define IWDG_Prescaler_128 ((uint8_t)0x05)
#define IWDG_Prescaler_256 ((uint8_t)0x06)
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
((PRESCALER) == IWDG_Prescaler_8) || \
((PRESCALER) == IWDG_Prescaler_16) || \
((PRESCALER) == IWDG_Prescaler_32) || \
((PRESCALER) == IWDG_Prescaler_64) || \
((PRESCALER) == IWDG_Prescaler_128)|| \
((PRESCALER) == IWDG_Prescaler_256))
/**
* @}
*/
/** @defgroup IWDG_Flag
* @{
*/
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
#define IWDG_FLAG_WVU ((uint16_t)0x0002)
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
((FLAG) == IWDG_FLAG_WVU))
/**
* @}
*/
/** @defgroup IWDG_Reload_Value
* @{
*/
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
/**
* @}
*/
/** @defgroup IWDG_CounterWindow_Value
* @{
*/
#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Prescaler and Counter configuration functions ******************************/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void);
void IWDG_SetWindowValue(uint16_t WindowValue);
/* IWDG activation function ***************************************************/
void IWDG_Enable(void);
/* Flag management function ***************************************************/
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_IWDG_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_misc.h
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/**
******************************************************************************
* @file stm32f30x_misc.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_MISC_H
#define __STM32F30x_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief NVIC Init Structure definition
*/
typedef struct
{
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type (For
the complete STM32 Devices IRQ Channels list, please
refer to stm32f30x.h file) */
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15.
A lower priority value indicates a higher priority */
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value
between 0 and 15.
A lower priority value indicates a higher priority */
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitTypeDef;
/**
*
@verbatim
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
============================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
============================================================================================================================
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
| | | 4 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
| | | 3 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bits for subpriority
============================================================================================================================
@endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup MISC_Exported_Constants
* @{
*/
/** @defgroup MISC_Vector_Table_Base
* @{
*/
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
*/
/** @defgroup MISC_System_Low_Power
* @{
*/
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/**
* @}
*/
/** @defgroup MISC_Preemption_Priority_Group
* @{
*/
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/**
* @}
*/
/** @defgroup MISC_SysTick_clock_source
*/
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_MISC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_opamp.h
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/**
******************************************************************************
* @file stm32f30x_opamp.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the operational
* amplifiers (OPAMP) firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_OPAMP_H
#define __STM32F30x_OPAMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup OPAMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief OPAMP Init structure definition
*/
typedef struct
{
uint32_t OPAMP_InvertingInput; /*!< Selects the inverting input of the operational amplifier.
This parameter can be a value of @ref OPAMP_InvertingInput */
uint32_t OPAMP_NonInvertingInput; /*!< Selects the non inverting input of the operational amplifier.
This parameter can be a value of @ref OPAMP_NonInvertingInput */
}OPAMP_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Constants
* @{
*/
/** @defgroup OPAMP_Selection
* @{
*/
#define OPAMP_Selection_OPAMP1 ((uint32_t)0x00000000) /*!< OPAMP1 Selection */
#define OPAMP_Selection_OPAMP2 ((uint32_t)0x00000004) /*!< OPAMP2 Selection */
#define OPAMP_Selection_OPAMP3 ((uint32_t)0x00000008) /*!< OPAMP3 Selection */
#define OPAMP_Selection_OPAMP4 ((uint32_t)0x0000000C) /*!< OPAMP4 Selection */
#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
((PERIPH) == OPAMP_Selection_OPAMP2) || \
((PERIPH) == OPAMP_Selection_OPAMP3) || \
((PERIPH) == OPAMP_Selection_OPAMP4))
/**
* @}
*/
/** @defgroup OPAMP_InvertingInput
* @{
*/
#define OPAMP_InvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
connected to OPAMPx inverting input */
#define OPAMP_InvertingInput_IO2 OPAMP_CSR_VMSEL_0 /*!< IO2 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
connected to OPAMPx inverting input */
#define OPAMP_InvertingInput_PGA OPAMP_CSR_VMSEL_1 /*!< Resistor feedback output connected to OPAMPx inverting input (PGA mode) */
#define OPAMP_InvertingInput_Vout OPAMP_CSR_VMSEL /*!< Vout connected to OPAMPx inverting input (follower mode) */
#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_InvertingInput_IO1) || \
((INPUT) == OPAMP_InvertingInput_IO2) || \
((INPUT) == OPAMP_InvertingInput_PGA) || \
((INPUT) == OPAMP_InvertingInput_Vout))
/**
* @}
*/
/** @defgroup OPAMP_NonInvertingInput
* @{
*/
#define OPAMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
connected to OPAMPx non inverting input */
#define OPAMP_NonInvertingInput_IO2 OPAMP_CSR_VPSEL_0 /*!< IO2 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
connected to OPAMPx non inverting input */
#define OPAMP_NonInvertingInput_IO3 OPAMP_CSR_VPSEL_1 /*!< IO3 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
connected to OPAMPx non inverting input */
#define OPAMP_NonInvertingInput_IO4 OPAMP_CSR_VPSEL /*!< IO4 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
connected to OPAMPx non inverting input */
#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NonInvertingInput_IO1) || \
((INPUT) == OPAMP_NonInvertingInput_IO2) || \
((INPUT) == OPAMP_NonInvertingInput_IO3) || \
((INPUT) == OPAMP_NonInvertingInput_IO4))
/**
* @}
*/
/** @defgroup OPAMP_PGAGain_Config
* @{
*/
#define OPAMP_OPAMP_PGAGain_2 ((uint32_t)0x00000000)
#define OPAMP_OPAMP_PGAGain_4 OPAMP_CSR_PGGAIN_0
#define OPAMP_OPAMP_PGAGain_8 OPAMP_CSR_PGGAIN_1
#define OPAMP_OPAMP_PGAGain_16 ((uint32_t)0x0000C000)
#define IS_OPAMP_PGAGAIN(GAIN) (((GAIN) == OPAMP_OPAMP_PGAGain_2) || \
((GAIN) == OPAMP_OPAMP_PGAGain_4) || \
((GAIN) == OPAMP_OPAMP_PGAGain_8) || \
((GAIN) == OPAMP_OPAMP_PGAGain_16))
/**
* @}
*/
/** @defgroup OPAMP_PGAConnect_Config
* @{
*/
#define OPAMP_PGAConnect_No ((uint32_t)0x00000000)
#define OPAMP_PGAConnect_IO1 OPAMP_CSR_PGGAIN_3
#define OPAMP_PGAConnect_IO2 ((uint32_t)0x00030000)
#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGAConnect_No) || \
((CONNECT) == OPAMP_PGAConnect_IO1) || \
((CONNECT) == OPAMP_PGAConnect_IO2))
/**
* @}
*/
/** @defgroup OPAMP_SecondaryInvertingInput
* @{
*/
#define IS_OPAMP_SECONDARY_INVINPUT(INVINPUT) (((INVINPUT) == OPAMP_InvertingInput_IO1) || \
((INVINPUT) == OPAMP_InvertingInput_IO2))
/**
* @}
*/
/** @defgroup OPAMP_Input
* @{
*/
#define OPAMP_Input_Inverting ((uint32_t)0x00000018) /*!< Inverting input */
#define OPAMP_Input_NonInverting ((uint32_t)0x00000013) /*!< Non inverting input */
#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_Inverting) || \
((INPUT) == OPAMP_Input_NonInverting))
/**
* @}
*/
/** @defgroup OPAMP_Vref
* @{
*/
#define OPAMP_Vref_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */
#define OPAMP_Vref_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */
#define OPAMP_Vref_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */
#define OPAMP_Vref_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */
#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_Vref_3VDDA) || \
((VREF) == OPAMP_Vref_10VDDA) || \
((VREF) == OPAMP_Vref_50VDDA) || \
((VREF) == OPAMP_Vref_90VDDA))
/**
* @}
*/
/** @defgroup OPAMP_Trimming
*/
#define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */
#define OPAMP_Trimming_User OPAMP_CSR_USERTRIM /*!< User trimming */
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
((TRIMMING) == OPAMP_Trimming_User))
/**
* @}
*/
/** @defgroup OPAMP_TrimValue
* @{
*/
#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
/**
* @}
*/
/** @defgroup OPAMP_OutputLevel
* @{
*/
#define OPAMP_OutputLevel_High OPAMP_CSR_OUTCAL
#define OPAMP_OutputLevel_Low ((uint32_t)0x00000000)
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the OPAMP configuration to the default reset state ***/
void OPAMP_DeInit(uint32_t OPAMP_Selection);
/* Initialization and Configuration functions *********************************/
void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct);
void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect);
void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref);
void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection);
/* Calibration functions ******************************************************/
void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState);
void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming);
void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState);
/* OPAMP configuration locking function ***************************************/
void OPAMP_LockConfig(uint32_t OPAMP_Selection);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F30x_OPAMP_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_pwr.h
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@ -1,187 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_pwr.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_PWR_H
#define __STM32F30x_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants
* @{
*/
/** @defgroup PWR_PVD_detection_level
* @{
*/
#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
/**
* @}
*/
/** @defgroup PWR_WakeUp_Pins
* @{
*/
#define PWR_WakeUpPin_1 PWR_CSR_EWUP1
#define PWR_WakeUpPin_2 PWR_CSR_EWUP2
#define PWR_WakeUpPin_3 PWR_CSR_EWUP3
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
((PIN) == PWR_WakeUpPin_2) || \
((PIN) == PWR_WakeUpPin_3))
/**
* @}
*/
/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
* @{
*/
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower PWR_CR_LPSDSR
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
((REGULATOR) == PWR_Regulator_LowPower))
/**
* @}
*/
/** @defgroup PWR_SLEEP_mode_entry
* @{
*/
#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
/**
* @}
*/
/** @defgroup PWR_STOP_mode_entry
* @{
*/
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
/**
* @}
*/
/** @defgroup PWR_Flag
* @{
*/
#define PWR_FLAG_WU PWR_CSR_WUF
#define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the PWR configuration to the default reset state ******/
void PWR_DeInit(void);
/* Backup Domain Access function **********************************************/
void PWR_BackupAccessCmd(FunctionalState NewState);
/* PVD configuration functions ************************************************/
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_PVDCmd(FunctionalState NewState);
/* WakeUp pins configuration functions ****************************************/
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
/* Low Power modes configuration functions ************************************/
void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
/* Flags management functions *************************************************/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_PWR_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

699
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_rcc.h
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@ -1,699 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_rcc.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the RCC
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_RCC_H
#define __STM32F30x_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup RCC
* @{
*/
/* Exported types ------------------------------------------------------------*/
typedef struct
{
uint32_t SYSCLK_Frequency;
uint32_t HCLK_Frequency;
uint32_t PCLK1_Frequency;
uint32_t PCLK2_Frequency;
uint32_t ADC12CLK_Frequency;
uint32_t ADC34CLK_Frequency;
uint32_t I2C1CLK_Frequency;
uint32_t I2C2CLK_Frequency;
uint32_t I2C3CLK_Frequency;
uint32_t TIM1CLK_Frequency;
uint32_t HRTIM1CLK_Frequency;
uint32_t TIM8CLK_Frequency;
uint32_t USART1CLK_Frequency;
uint32_t USART2CLK_Frequency;
uint32_t USART3CLK_Frequency;
uint32_t UART4CLK_Frequency;
uint32_t UART5CLK_Frequency;
uint32_t TIM15CLK_Frequency;
uint32_t TIM16CLK_Frequency;
uint32_t TIM17CLK_Frequency;
}RCC_ClocksTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_Exported_Constants
* @{
*/
/** @defgroup RCC_HSE_configuration
* @{
*/
#define RCC_HSE_OFF ((uint8_t)0x00)
#define RCC_HSE_ON ((uint8_t)0x01)
#define RCC_HSE_Bypass ((uint8_t)0x05)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_Bypass))
/**
* @}
*/
/** @defgroup RCC_PLL_Clock_Source
* @{
*/
#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
((SOURCE) == RCC_PLLSource_PREDIV1))
/**
* @}
*/
/** @defgroup RCC_PLL_Multiplication_Factor
* @{
*/
#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
((MUL) == RCC_PLLMul_16))
/**
* @}
*/
/** @defgroup RCC_PREDIV1_division_factor
* @{
*/
#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
/**
* @}
*/
/** @defgroup RCC_System_Clock_Source
* @{
*/
#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
/**
* @}
*/
/** @defgroup RCC_AHB_Clock_Source
* @{
*/
#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
((HCLK) == RCC_SYSCLK_Div512))
/**
* @}
*/
/** @defgroup RCC_APB1_APB2_clock_source
* @{
*/
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
((PCLK) == RCC_HCLK_Div16))
/**
* @}
*/
/** @defgroup RCC_ADC_clock_source
* @{
*/
/* ADC1 & ADC2 */
#define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000)
#define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100)
#define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110)
#define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120)
#define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130)
#define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140)
#define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150)
#define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160)
#define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170)
#define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180)
#define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190)
#define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0)
#define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0)
/* ADC3 & ADC4 */
#define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000)
#define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000)
#define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200)
#define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400)
#define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600)
#define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800)
#define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00)
#define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00)
#define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00)
#define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000)
#define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200)
#define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400)
#define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600)
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
/**
* @}
*/
/** @defgroup RCC_TIM_clock_source
* @{
*/
#define RCC_TIM1CLK_HCLK ((uint32_t)0x00000000)
#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW
#define RCC_TIM8CLK_HCLK ((uint32_t)0x10000000)
#define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200)
#define RCC_TIM15CLK_HCLK ((uint32_t)0x20000000)
#define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400)
#define RCC_TIM16CLK_HCLK ((uint32_t)0x30000000)
#define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800)
#define RCC_TIM17CLK_HCLK ((uint32_t)0x40000000)
#define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000)
#define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \
((TIMCLK) == RCC_TIM15CLK_HCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \
((TIMCLK) == RCC_TIM16CLK_HCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \
((TIMCLK) == RCC_TIM17CLK_HCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK))
/**
* @}
*/
/** @defgroup RCC_HRTIM_clock_source
* @{
*/
#define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000)
#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW
#define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK))
/**
* @}
*/
/** @defgroup RCC_I2C_clock_source
* @{
*/
#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
#define RCC_I2C2CLK_HSI ((uint32_t)0x10000000)
#define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020)
#define RCC_I2C3CLK_HSI ((uint32_t)0x20000000)
#define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040)
#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \
((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK))
/**
* @}
*/
/** @defgroup RCC_USART_clock_source
* @{
*/
#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
#define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
#define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000)
#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000)
#define RCC_USART2CLK_LSE ((uint32_t)0x20020000)
#define RCC_USART2CLK_HSI ((uint32_t)0x20030000)
#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000)
#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000)
#define RCC_USART3CLK_LSE ((uint32_t)0x30080000)
#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000)
#define RCC_UART4CLK_PCLK ((uint32_t)0x40000000)
#define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000)
#define RCC_UART4CLK_LSE ((uint32_t)0x40200000)
#define RCC_UART4CLK_HSI ((uint32_t)0x40300000)
#define RCC_UART5CLK_PCLK ((uint32_t)0x50000000)
#define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000)
#define RCC_UART5CLK_LSE ((uint32_t)0x50800000)
#define RCC_UART5CLK_HSI ((uint32_t)0x50C00000)
#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
/**
* @}
*/
/** @defgroup RCC_Interrupt_Source
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_CSS ((uint8_t)0x80)
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup RCC_LSE_configuration
* @{
*/
#define RCC_LSE_OFF ((uint32_t)0x00000000)
#define RCC_LSE_ON RCC_BDCR_LSEON
#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_Bypass))
/**
* @}
*/
/** @defgroup RCC_RTC_Clock_Source
* @{
*/
#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
((SOURCE) == RCC_RTCCLKSource_LSI) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
/**
* @}
*/
/** @defgroup RCC_I2S_Clock_Source
* @{
*/
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
/** @defgroup RCC_LSE_Drive_Configuration
* @{
*/
#define RCC_LSEDrive_Low ((uint32_t)0x00000000)
#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
#define RCC_LSEDrive_High RCC_BDCR_LSEDRV
#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
/**
* @}
*/
/** @defgroup RCC_AHB_Peripherals
* @{
*/
#define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
#define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_APB2_Peripherals
* @{
*/
#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
#define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN
#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
#define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFF887FE) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_APB1_Peripherals
* @{
*/
#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
#define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN
#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
#define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN
#define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN
#define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN
#define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup RCC_MCO_Clock_Source
* @{
*/
#define RCC_MCOSource_NoClock ((uint8_t)0x00)
#define RCC_MCOSource_LSI ((uint8_t)0x02)
#define RCC_MCOSource_LSE ((uint8_t)0x03)
#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
#define RCC_MCOSource_HSI ((uint8_t)0x05)
#define RCC_MCOSource_HSE ((uint8_t)0x06)
#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \
((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \
((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
/**
* @}
*/
/** @defgroup RCC_MCOPrescaler
* @{
*/
#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
((PRESCALER) == RCC_MCOPrescaler_2) || \
((PRESCALER) == RCC_MCOPrescaler_4) || \
((PRESCALER) == RCC_MCOPrescaler_8) || \
((PRESCALER) == RCC_MCOPrescaler_16) || \
((PRESCALER) == RCC_MCOPrescaler_32) || \
((PRESCALER) == RCC_MCOPrescaler_64) || \
((PRESCALER) == RCC_MCOPrescaler_128))
/**
* @}
*/
/** @defgroup RCC_USB_Device_clock_source
* @{
*/
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
/**
* @}
*/
/** @defgroup RCC_Flag
* @{
*/
#define RCC_FLAG_HSIRDY ((uint8_t)0x01)
#define RCC_FLAG_HSERDY ((uint8_t)0x11)
#define RCC_FLAG_PLLRDY ((uint8_t)0x19)
#define RCC_FLAG_MCOF ((uint8_t)0x9C)
#define RCC_FLAG_LSERDY ((uint8_t)0x21)
#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
#define RCC_FLAG_OBLRST ((uint8_t)0x59)
#define RCC_FLAG_PINRST ((uint8_t)0x5A)
#define RCC_FLAG_PORRST ((uint8_t)0x5B)
#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
((FLAG) == RCC_FLAG_MCOF))
#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the RCC clock configuration to the default reset state */
void RCC_DeInit(void);
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
void RCC_HSEConfig(uint8_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_LSEConfig(uint32_t RCC_LSE);
void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
void RCC_LSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
#ifdef STM32F303xC
void RCC_MCOConfig(uint8_t RCC_MCOSource);
#else
void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
#endif /* STM32F303xC */
/* System, AHB and APB busses clocks configuration functions ******************/
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
/* Peripheral clocks configuration functions **********************************/
void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK);
void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK);
void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK);
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_RCC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_rtc.h
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@ -1,852 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_rtc.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_RTC_H
#define __STM32F30x_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup RTC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief RTC Init structures definition
*/
typedef struct
{
uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
This parameter can be a value of @ref RTC_Hour_Formats */
uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be set to a value lower than 0x7F */
uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
This parameter must be set to a value lower than 0x1FFF */
}RTC_InitTypeDef;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
This parameter must be set to a value in the 0-12 range
if the RTC_HourFormat_12 is selected or 0-23 range if
the RTC_HourFormat_24 is selected. */
uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be set to a value in the 0-59 range. */
uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be set to a value in the 0-59 range. */
uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
}RTC_TimeTypeDef;
/**
* @brief RTC Date structure definition
*/
typedef struct
{
uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
This parameter can be a value of @ref RTC_WeekDay_Definitions */
uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).
This parameter can be a value of @ref RTC_Month_Date_Definitions */
uint8_t RTC_Date; /*!< Specifies the RTC Date.
This parameter must be set to a value in the 1-31 range. */
uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
This parameter must be set to a value in the 0-99 range. */
}RTC_DateTypeDef;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
If the Alarm Date is selected, this parameter
must be set to a value in the 1-31 range.
If the Alarm WeekDay is selected, this
parameter can be a value of @ref RTC_WeekDay_Definitions */
}RTC_AlarmTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_Exported_Constants
* @{
*/
/** @defgroup RTC_Hour_Formats
* @{
*/
#define RTC_HourFormat_24 ((uint32_t)0x00000000)
#define RTC_HourFormat_12 ((uint32_t)0x00000040)
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
((FORMAT) == RTC_HourFormat_24))
/**
* @}
*/
/** @defgroup RTC_Asynchronous_Predivider
* @{
*/
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
/**
* @}
*/
/** @defgroup RTC_Synchronous_Predivider
* @{
*/
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
/**
* @}
*/
/** @defgroup RTC_Time_Definitions
* @{
*/
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
/**
* @}
*/
/** @defgroup RTC_AM_PM_Definitions
* @{
*/
#define RTC_H12_AM ((uint8_t)0x00)
#define RTC_H12_PM ((uint8_t)0x40)
#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
/**
* @}
*/
/** @defgroup RTC_Year_Date_Definitions
* @{
*/
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
/**
* @}
*/
/** @defgroup RTC_Month_Date_Definitions
* @{
*/
/* Coded in BCD format */
#define RTC_Month_January ((uint8_t)0x01)
#define RTC_Month_February ((uint8_t)0x02)
#define RTC_Month_March ((uint8_t)0x03)
#define RTC_Month_April ((uint8_t)0x04)
#define RTC_Month_May ((uint8_t)0x05)
#define RTC_Month_June ((uint8_t)0x06)
#define RTC_Month_July ((uint8_t)0x07)
#define RTC_Month_August ((uint8_t)0x08)
#define RTC_Month_September ((uint8_t)0x09)
#define RTC_Month_October ((uint8_t)0x10)
#define RTC_Month_November ((uint8_t)0x11)
#define RTC_Month_December ((uint8_t)0x12)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
/**
* @}
*/
/** @defgroup RTC_WeekDay_Definitions
* @{
*/
#define RTC_Weekday_Monday ((uint8_t)0x01)
#define RTC_Weekday_Tuesday ((uint8_t)0x02)
#define RTC_Weekday_Wednesday ((uint8_t)0x03)
#define RTC_Weekday_Thursday ((uint8_t)0x04)
#define RTC_Weekday_Friday ((uint8_t)0x05)
#define RTC_Weekday_Saturday ((uint8_t)0x06)
#define RTC_Weekday_Sunday ((uint8_t)0x07)
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
((WEEKDAY) == RTC_Weekday_Tuesday) || \
((WEEKDAY) == RTC_Weekday_Wednesday) || \
((WEEKDAY) == RTC_Weekday_Thursday) || \
((WEEKDAY) == RTC_Weekday_Friday) || \
((WEEKDAY) == RTC_Weekday_Saturday) || \
((WEEKDAY) == RTC_Weekday_Sunday))
/**
* @}
*/
/** @defgroup RTC_Alarm_Definitions
* @{
*/
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
((WEEKDAY) == RTC_Weekday_Tuesday) || \
((WEEKDAY) == RTC_Weekday_Wednesday) || \
((WEEKDAY) == RTC_Weekday_Thursday) || \
((WEEKDAY) == RTC_Weekday_Friday) || \
((WEEKDAY) == RTC_Weekday_Saturday) || \
((WEEKDAY) == RTC_Weekday_Sunday))
/**
* @}
*/
/** @defgroup RTC_AlarmDateWeekDay_Definitions
* @{
*/
#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
/**
* @}
*/
/** @defgroup RTC_AlarmMask_Definitions
* @{
*/
#define RTC_AlarmMask_None ((uint32_t)0x00000000)
#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
#define RTC_AlarmMask_All ((uint32_t)0x80808080)
#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
/**
* @}
*/
/** @defgroup RTC_Alarms_Definitions
* @{
*/
#define RTC_Alarm_A ((uint32_t)0x00000100)
#define RTC_Alarm_B ((uint32_t)0x00000200)
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
/**
* @}
*/
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
* @{
*/
#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
There is no comparison on sub seconds
for Alarm */
#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
comparison. Only SS[0] is compared. */
#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
comparison. Only SS[1:0] are compared */
#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
comparison. Only SS[2:0] are compared */
#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
comparison. Only SS[3:0] are compared */
#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
comparison. Only SS[4:0] are compared */
#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
comparison. Only SS[5:0] are compared */
#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
comparison. Only SS[6:0] are compared */
#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
comparison. Only SS[7:0] are compared */
#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
comparison. Only SS[8:0] are compared */
#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
comparison. Only SS[9:0] are compared */
#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
comparison. Only SS[10:0] are compared */
#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
comparison.Only SS[11:0] are compared */
#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
comparison. Only SS[12:0] are compared */
#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
comparison.Only SS[13:0] are compared */
#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
to activate alarm. */
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
((MASK) == RTC_AlarmSubSecondMask_SS14) || \
((MASK) == RTC_AlarmSubSecondMask_None))
/**
* @}
*/
/** @defgroup RTC_Alarm_Sub_Seconds_Value
* @{
*/
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
/**
* @}
*/
/** @defgroup RTC_Wakeup_Timer_Definitions
* @{
*/
#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
/**
* @}
*/
/** @defgroup RTC_Time_Stamp_Edges_definitions
* @{
*/
#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
((EDGE) == RTC_TimeStampEdge_Falling))
/**
* @}
*/
/** @defgroup RTC_Output_selection_Definitions
* @{
*/
#define RTC_Output_Disable ((uint32_t)0x00000000)
#define RTC_Output_AlarmA ((uint32_t)0x00200000)
#define RTC_Output_AlarmB ((uint32_t)0x00400000)
#define RTC_Output_WakeUp ((uint32_t)0x00600000)
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
((OUTPUT) == RTC_Output_AlarmA) || \
((OUTPUT) == RTC_Output_AlarmB) || \
((OUTPUT) == RTC_Output_WakeUp))
/**
* @}
*/
/** @defgroup RTC_Output_Polarity_Definitions
* @{
*/
#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
((POL) == RTC_OutputPolarity_Low))
/**
* @}
*/
/** @defgroup RTC_Digital_Calibration_Definitions
* @{
*/
#define RTC_CalibSign_Positive ((uint32_t)0x00000000)
#define RTC_CalibSign_Negative ((uint32_t)0x00000080)
#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
((SIGN) == RTC_CalibSign_Negative))
#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
/**
* @}
*/
/** @defgroup RTC_Calib_Output_selection_Definitions
* @{
*/
#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
((OUTPUT) == RTC_CalibOutput_1Hz))
/**
* @}
*/
/** @defgroup RTC_Smooth_calib_period_Definitions
* @{
*/
#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
period is 32s, else 2exp20 RTCCLK seconds */
#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
period is 16s, else 2exp19 RTCCLK seconds */
#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
period is 8s, else 2exp18 RTCCLK seconds */
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
((PERIOD) == RTC_SmoothCalibPeriod_8sec))
/**
* @}
*/
/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
* @{
*/
#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
during a X -second window = Y - CALM[8:0].
with Y = 512, 256, 128 when X = 32, 16, 8 */
#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
during a 32-second window = CALM[8:0]. */
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
/**
* @}
*/
/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
* @{
*/
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
/**
* @}
*/
/** @defgroup RTC_DayLightSaving_Definitions
* @{
*/
#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
((SAVE) == RTC_DayLightSaving_ADD1H))
#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
((OPERATION) == RTC_StoreOperation_Set))
/**
* @}
*/
/** @defgroup RTC_Tamper_Trigger_Definitions
* @{
*/
#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
((TRIGGER) == RTC_TamperTrigger_HighLevel))
/**
* @}
*/
/** @defgroup RTC_Tamper_Filter_Definitions
* @{
*/
#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
consecutive samples at the active level */
#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
consecutive samples at the active level */
#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
consecutive samples at the active leve. */
#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
((FILTER) == RTC_TamperFilter_2Sample) || \
((FILTER) == RTC_TamperFilter_4Sample) || \
((FILTER) == RTC_TamperFilter_8Sample))
/**
* @}
*/
/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
* @{
*/
#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 32768 */
#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 16384 */
#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 8192 */
#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 4096 */
#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 2048 */
#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 1024 */
#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 512 */
#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 256 */
#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
/**
* @}
*/
/** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
* @{
*/
#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
sampling during 1 RTCCLK cycle */
#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
sampling during 2 RTCCLK cycles */
#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
sampling during 4 RTCCLK cycles */
#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
sampling during 8 RTCCLK cycles */
#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
/**
* @}
*/
/** @defgroup RTC_Tamper_Pins_Definitions
* @{
*/
#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
input tamper 1 */
#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
input tamper 2 */
#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
input tamper 3 */
#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
/**
* @}
*/
/** @defgroup RTC_Output_Type_ALARM_OUT
* @{
*/
#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
((TYPE) == RTC_OutputType_PushPull))
/**
* @}
*/
/** @defgroup RTC_Add_1_Second_Parameter_Definitions
* @{
*/
#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
((SEL) == RTC_ShiftAdd1S_Set))
/**
* @}
*/
/** @defgroup RTC_Substract_Fraction_Of_Second_Value
* @{
*/
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
/**
* @}
*/
/** @defgroup RTC_Backup_Registers_Definitions
* @{
*/
#define RTC_BKP_DR0 ((uint32_t)0x00000000)
#define RTC_BKP_DR1 ((uint32_t)0x00000001)
#define RTC_BKP_DR2 ((uint32_t)0x00000002)
#define RTC_BKP_DR3 ((uint32_t)0x00000003)
#define RTC_BKP_DR4 ((uint32_t)0x00000004)
#define RTC_BKP_DR5 ((uint32_t)0x00000005)
#define RTC_BKP_DR6 ((uint32_t)0x00000006)
#define RTC_BKP_DR7 ((uint32_t)0x00000007)
#define RTC_BKP_DR8 ((uint32_t)0x00000008)
#define RTC_BKP_DR9 ((uint32_t)0x00000009)
#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
((BKP) == RTC_BKP_DR1) || \
((BKP) == RTC_BKP_DR2) || \
((BKP) == RTC_BKP_DR3) || \
((BKP) == RTC_BKP_DR4) || \
((BKP) == RTC_BKP_DR5) || \
((BKP) == RTC_BKP_DR6) || \
((BKP) == RTC_BKP_DR7) || \
((BKP) == RTC_BKP_DR8) || \
((BKP) == RTC_BKP_DR9) || \
((BKP) == RTC_BKP_DR10) || \
((BKP) == RTC_BKP_DR11) || \
((BKP) == RTC_BKP_DR12) || \
((BKP) == RTC_BKP_DR13) || \
((BKP) == RTC_BKP_DR14) || \
((BKP) == RTC_BKP_DR15))
/**
* @}
*/
/** @defgroup RTC_Input_parameter_format_definitions
* @{
*/
#define RTC_Format_BIN ((uint32_t)0x000000000)
#define RTC_Format_BCD ((uint32_t)0x000000001)
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
/**
* @}
*/
/** @defgroup RTC_Flags_Definitions
* @{
*/
#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
#define RTC_FLAG_TSF ((uint32_t)0x00000800)
#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
#define RTC_FLAG_INITF ((uint32_t)0x00000040)
#define RTC_FLAG_RSF ((uint32_t)0x00000020)
#define RTC_FLAG_INITS ((uint32_t)0x00000010)
#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
((FLAG) == RTC_FLAG_SHPF))
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
/**
* @}
*/
/** @defgroup RTC_Interrupts_Definitions
* @{
*/
#define RTC_IT_TS ((uint32_t)0x00008000)
#define RTC_IT_WUT ((uint32_t)0x00004000)
#define RTC_IT_ALRB ((uint32_t)0x00002000)
#define RTC_IT_ALRA ((uint32_t)0x00001000)
#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
#define RTC_IT_TAMP3 ((uint32_t)0x00080000)
#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
((IT) == RTC_IT_TAMP3))
#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the RTC configuration to the default reset state *****/
ErrorStatus RTC_DeInit(void);
/* Initialization and Configuration functions *********************************/
ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
void RTC_WriteProtectionCmd(FunctionalState NewState);
ErrorStatus RTC_EnterInitMode(void);
void RTC_ExitInitMode(void);
ErrorStatus RTC_WaitForSynchro(void);
ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
void RTC_BypassShadowCmd(FunctionalState NewState);
/* Time and Date configuration functions **************************************/
ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
uint32_t RTC_GetSubSecond(void);
ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
/* Alarms (Alarm A and Alarm B) configuration functions **********************/
void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
/* WakeUp Timer configuration functions ***************************************/
void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
uint32_t RTC_GetWakeUpCounter(void);
ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
/* Daylight Saving configuration functions ************************************/
void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
uint32_t RTC_GetStoreOperation(void);
/* Output pin Configuration function ******************************************/
void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
/* Digital Calibration configuration functions ********************************/
void RTC_CalibOutputCmd(FunctionalState NewState);
void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
uint32_t RTC_SmoothCalibPlusPulses,
uint32_t RTC_SmouthCalibMinusPulsesValue);
/* TimeStamp configuration functions ******************************************/
void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
RTC_DateTypeDef* RTC_StampDateStruct);
uint32_t RTC_GetTimeStampSubSecond(void);
/* Tampers configuration functions ********************************************/
void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
void RTC_TamperPullUpCmd(FunctionalState NewState);
/* Backup Data Registers configuration functions ******************************/
void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
/* Output Type Config configuration functions *********************************/
void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
/* RTC_Shift_control_synchonisation_functions *********************************/
ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
/* Interrupts and flags management functions **********************************/
void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
void RTC_ClearFlag(uint32_t RTC_FLAG);
ITStatus RTC_GetITStatus(uint32_t RTC_IT);
void RTC_ClearITPendingBit(uint32_t RTC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F30x_RTC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

606
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_spi.h
View file

@ -1,606 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_spi.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the SPI
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_SPI_H
#define __STM32F30x_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief SPI Init structure definition
*/
typedef struct
{
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */
uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
This parameter can be a value of @ref SPI_mode */
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
}SPI_InitTypeDef;
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
}I2S_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_Exported_Constants
* @{
*/
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
((PERIPH) == SPI2) || \
((PERIPH) == SPI3))
#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
((PERIPH) == SPI2) || \
((PERIPH) == SPI3) || \
((PERIPH) == I2S2ext) || \
((PERIPH) == I2S3ext))
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
((PERIPH) == SPI3))
#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
((PERIPH) == SPI3) || \
((PERIPH) == I2S2ext) || \
((PERIPH) == I2S3ext))
#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
((PERIPH) == I2S3ext))
/** @defgroup SPI_data_direction
* @{
*/
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
((MODE) == SPI_Direction_2Lines_RxOnly) || \
((MODE) == SPI_Direction_1Line_Rx) || \
((MODE) == SPI_Direction_1Line_Tx))
/**
* @}
*/
/** @defgroup SPI_mode
* @{
*/
#define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
((MODE) == SPI_Mode_Slave))
/**
* @}
*/
/** @defgroup SPI_data_size
* @{
*/
#define SPI_DataSize_4b ((uint16_t)0x0300)
#define SPI_DataSize_5b ((uint16_t)0x0400)
#define SPI_DataSize_6b ((uint16_t)0x0500)
#define SPI_DataSize_7b ((uint16_t)0x0600)
#define SPI_DataSize_8b ((uint16_t)0x0700)
#define SPI_DataSize_9b ((uint16_t)0x0800)
#define SPI_DataSize_10b ((uint16_t)0x0900)
#define SPI_DataSize_11b ((uint16_t)0x0A00)
#define SPI_DataSize_12b ((uint16_t)0x0B00)
#define SPI_DataSize_13b ((uint16_t)0x0C00)
#define SPI_DataSize_14b ((uint16_t)0x0D00)
#define SPI_DataSize_15b ((uint16_t)0x0E00)
#define SPI_DataSize_16b ((uint16_t)0x0F00)
#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
((SIZE) == SPI_DataSize_5b) || \
((SIZE) == SPI_DataSize_6b) || \
((SIZE) == SPI_DataSize_7b) || \
((SIZE) == SPI_DataSize_8b) || \
((SIZE) == SPI_DataSize_9b) || \
((SIZE) == SPI_DataSize_10b) || \
((SIZE) == SPI_DataSize_11b) || \
((SIZE) == SPI_DataSize_12b) || \
((SIZE) == SPI_DataSize_13b) || \
((SIZE) == SPI_DataSize_14b) || \
((SIZE) == SPI_DataSize_15b) || \
((SIZE) == SPI_DataSize_16b))
/**
* @}
*/
/** @defgroup SPI_CRC_length
* @{
*/
#define SPI_CRCLength_8b ((uint16_t)0x0000)
#define SPI_CRCLength_16b ((uint16_t)0x0800)
#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
((LENGTH) == SPI_CRCLength_16b))
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity
* @{
*/
#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002)
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
((CPOL) == SPI_CPOL_High))
/**
* @}
*/
/** @defgroup SPI_Clock_Phase
* @{
*/
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
((CPHA) == SPI_CPHA_2Edge))
/**
* @}
*/
/** @defgroup SPI_Slave_Select_management
* @{
*/
#define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
((NSS) == SPI_NSS_Hard))
/**
* @}
*/
/** @defgroup SPI_BaudRate_Prescaler
* @{
*/
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
((PRESCALER) == SPI_BaudRatePrescaler_256))
/**
* @}
*/
/** @defgroup SPI_MSB_LSB_transmission
* @{
*/
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
((BIT) == SPI_FirstBit_LSB))
/**
* @}
*/
/** @defgroup I2S_Mode
* @{
*/
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
((MODE) == I2S_Mode_SlaveRx) || \
((MODE) == I2S_Mode_MasterTx)|| \
((MODE) == I2S_Mode_MasterRx))
/**
* @}
*/
/** @defgroup I2S_Standard
* @{
*/
#define I2S_Standard_Phillips ((uint16_t)0x0000)
#define I2S_Standard_MSB ((uint16_t)0x0010)
#define I2S_Standard_LSB ((uint16_t)0x0020)
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
((STANDARD) == I2S_Standard_MSB) || \
((STANDARD) == I2S_Standard_LSB) || \
((STANDARD) == I2S_Standard_PCMShort) || \
((STANDARD) == I2S_Standard_PCMLong))
/**
* @}
*/
/** @defgroup I2S_Data_Format
* @{
*/
#define I2S_DataFormat_16b ((uint16_t)0x0000)
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define I2S_DataFormat_24b ((uint16_t)0x0003)
#define I2S_DataFormat_32b ((uint16_t)0x0005)
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
((FORMAT) == I2S_DataFormat_16bextended) || \
((FORMAT) == I2S_DataFormat_24b) || \
((FORMAT) == I2S_DataFormat_32b))
/**
* @}
*/
/** @defgroup I2S_MCLK_Output
* @{
*/
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
((OUTPUT) == I2S_MCLKOutput_Disable))
/**
* @}
*/
/** @defgroup I2S_Audio_Frequency
* @{
*/
#define I2S_AudioFreq_192k ((uint32_t)192000)
#define I2S_AudioFreq_96k ((uint32_t)96000)
#define I2S_AudioFreq_48k ((uint32_t)48000)
#define I2S_AudioFreq_44k ((uint32_t)44100)
#define I2S_AudioFreq_32k ((uint32_t)32000)
#define I2S_AudioFreq_22k ((uint32_t)22050)
#define I2S_AudioFreq_16k ((uint32_t)16000)
#define I2S_AudioFreq_11k ((uint32_t)11025)
#define I2S_AudioFreq_8k ((uint32_t)8000)
#define I2S_AudioFreq_Default ((uint32_t)2)
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
((FREQ) <= I2S_AudioFreq_192k)) || \
((FREQ) == I2S_AudioFreq_Default))
/**
* @}
*/
/** @defgroup I2S_Clock_Polarity
* @{
*/
#define I2S_CPOL_Low ((uint16_t)0x0000)
#define I2S_CPOL_High ((uint16_t)0x0008)
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
((CPOL) == I2S_CPOL_High))
/**
* @}
*/
/** @defgroup SPI_FIFO_reception_threshold
* @{
*/
#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
#define SPI_RxFIFOThreshold_QF ((uint16_t)0x1000)
#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
((THRESHOLD) == SPI_RxFIFOThreshold_QF))
/**
* @}
*/
/** @defgroup SPI_I2S_DMA_transfer_requests
* @{
*/
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
/**
* @}
*/
/** @defgroup SPI_last_DMA_transfers
* @{
*/
#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
/**
* @}
*/
/** @defgroup SPI_NSS_internal_software_management
* @{
*/
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
((INTERNAL) == SPI_NSSInternalSoft_Reset))
/**
* @}
*/
/** @defgroup SPI_CRC_Transmit_Receive
* @{
*/
#define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_CRC_Rx ((uint8_t)0x01)
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
/**
* @}
*/
/** @defgroup SPI_direction_transmit_receive
* @{
*/
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_Direction_Tx ((uint16_t)0x4000)
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
((DIRECTION) == SPI_Direction_Tx))
/**
* @}
*/
/** @defgroup SPI_I2S_interrupts_definition
* @{
*/
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
((IT) == SPI_I2S_IT_RXNE) || \
((IT) == SPI_I2S_IT_ERR))
#define I2S_IT_UDR ((uint8_t)0x53)
#define SPI_IT_MODF ((uint8_t)0x55)
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_I2S_IT_FRE ((uint8_t)0x58)
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
/**
* @}
*/
/** @defgroup SPI_transmission_fifo_status_level
* @{
*/
#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
/**
* @}
*/
/** @defgroup SPI_reception_fifo_status_level
* @{
*/
#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
/**
* @}
*/
/** @defgroup SPI_I2S_flags_definition
* @{
*/
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define I2S_FLAG_UDR ((uint16_t)0x0008)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
#define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)
#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
((FLAG) == I2S_FLAG_UDR))
/**
* @}
*/
/** @defgroup SPI_CRC_polynomial
* @{
*/
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the SPI configuration to the default reset state*******/
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
/* Initialization and Configuration functions *********************************/
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
/* Data transfers functions ***************************************************/
void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
/* Hardware CRC Calculation functions *****************************************/
void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
/* DMA transfers management functions *****************************************/
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
/* Interrupts and flags management functions **********************************/
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F30x_SPI_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

345
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_syscfg.h
View file

@ -1,345 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_syscfg.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the SYSCFG firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/*!< Define to prevent recursive inclusion -----------------------------------*/
#ifndef __STM32F30x_SYSCFG_H
#define __STM32F30x_SYSCFG_H
#ifdef __cplusplus
extern "C" {
#endif
/*!< Includes ----------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup SYSCFG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSCFG_Exported_Constants
* @{
*/
/** @defgroup SYSCFG_EXTI_Port_Sources
* @{
*/
#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
((PORTSOURCE) == EXTI_PortSourceGPIOF))
/**
* @}
*/
/** @defgroup SYSCFG_EXTI_Pin_sources
* @{
*/
#define EXTI_PinSource0 ((uint8_t)0x00)
#define EXTI_PinSource1 ((uint8_t)0x01)
#define EXTI_PinSource2 ((uint8_t)0x02)
#define EXTI_PinSource3 ((uint8_t)0x03)
#define EXTI_PinSource4 ((uint8_t)0x04)
#define EXTI_PinSource5 ((uint8_t)0x05)
#define EXTI_PinSource6 ((uint8_t)0x06)
#define EXTI_PinSource7 ((uint8_t)0x07)
#define EXTI_PinSource8 ((uint8_t)0x08)
#define EXTI_PinSource9 ((uint8_t)0x09)
#define EXTI_PinSource10 ((uint8_t)0x0A)
#define EXTI_PinSource11 ((uint8_t)0x0B)
#define EXTI_PinSource12 ((uint8_t)0x0C)
#define EXTI_PinSource13 ((uint8_t)0x0D)
#define EXTI_PinSource14 ((uint8_t)0x0E)
#define EXTI_PinSource15 ((uint8_t)0x0F)
#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
((PINSOURCE) == EXTI_PinSource1) || \
((PINSOURCE) == EXTI_PinSource2) || \
((PINSOURCE) == EXTI_PinSource3) || \
((PINSOURCE) == EXTI_PinSource4) || \
((PINSOURCE) == EXTI_PinSource5) || \
((PINSOURCE) == EXTI_PinSource6) || \
((PINSOURCE) == EXTI_PinSource7) || \
((PINSOURCE) == EXTI_PinSource8) || \
((PINSOURCE) == EXTI_PinSource9) || \
((PINSOURCE) == EXTI_PinSource10) || \
((PINSOURCE) == EXTI_PinSource11) || \
((PINSOURCE) == EXTI_PinSource12) || \
((PINSOURCE) == EXTI_PinSource13) || \
((PINSOURCE) == EXTI_PinSource14) || \
((PINSOURCE) == EXTI_PinSource15))
/**
* @}
*/
/** @defgroup SYSCFG_Memory_Remap_Config
* @{
*/
#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM))
/**
* @}
*/
/** @defgroup SYSCFG_DMA_Remap_Config
* @{
*/
#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /*!< Remap TIM17 DMA requests from channel1 to channel2 */
#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /*!< Remap TIM16 DMA requests from channel3 to channel4 */
#define SYSCFG_DMARemap_ADC2ADC4 SYSCFG_CFGR1_ADC24_DMA_RMP /*!< Remap ADC2 and ADC4 DMA requests */
#define SYSCFG_DMARemap_TIM6DAC1Ch1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /* Remap TIM6/DAC1 Ch1 DMA requests */
#define SYSCFG_DMARemap_TIM7DAC1Ch2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /* Remap TIM7/DAC1 Ch2 DMA requests */
#define SYSCFG_DMARemap_DAC2Ch1 SYSCFG_CFGR1_DAC2Ch1_DMA_RMP /* Remap DAC2 Ch1 DMA requests */
#define SYSCFG_DMARemapCh2_SPI1_RX ((uint32_t)0x80000003) /* Remap SPI1 RX DMA CH2 requests */
#define SYSCFG_DMARemapCh4_SPI1_RX ((uint32_t)0x80000001) /* Remap SPI1 RX DMA CH4 requests */
#define SYSCFG_DMARemapCh6_SPI1_RX ((uint32_t)0x80000002) /* Remap SPI1 RX DMA CH6 requests */
#define SYSCFG_DMARemapCh3_SPI1_TX ((uint32_t)0x8000000C) /* Remap SPI1 TX DMA CH2 requests */
#define SYSCFG_DMARemapCh5_SPI1_TX ((uint32_t)0x80000004) /* Remap SPI1 TX DMA CH5 requests */
#define SYSCFG_DMARemapCh7_SPI1_TX ((uint32_t)0x80000008) /* Remap SPI1 TX DMA CH7 requests */
#define SYSCFG_DMARemapCh7_I2C1_RX ((uint32_t)0x80000030) /* Remap I2C1 RX DMA CH7 requests */
#define SYSCFG_DMARemapCh3_I2C1_RX ((uint32_t)0x80000010) /* Remap I2C1 RX DMA CH3 requests */
#define SYSCFG_DMARemapCh5_I2C1_RX ((uint32_t)0x80000020) /* Remap I2C1 RX DMA CH5 requests */
#define SYSCFG_DMARemapCh6_I2C1_TX ((uint32_t)0x800000C0) /* Remap I2C1 TX DMA CH6 requests */
#define SYSCFG_DMARemapCh2_I2C1_TX ((uint32_t)0x80000040) /* Remap I2C1 TX DMA CH2 requests */
#define SYSCFG_DMARemapCh4_I2C1_TX ((uint32_t)0x80000080) /* Remap I2C1 TX DMA CH4 requests */
#define SYSCFG_DMARemapCh4_ADC2 ((uint32_t)0x80000300) /* Remap ADC2 DMA1 Ch4 requests */
#define SYSCFG_DMARemapCh2_ADC2 ((uint32_t)0x80000200) /* Remap ADC2 DMA1 Ch2 requests */
/* SYSCFG_DMA_Remap_Legacy */
#define SYSCFG_DMARemap_TIM6DAC1 SYSCFG_DMARemap_TIM6DAC1Ch1 /*!< Remap TIM6/DAC1 DMA requests */
#define SYSCFG_DMARemap_TIM7DAC2 SYSCFG_DMARemap_TIM7DAC1Ch2 /*!< Remap TIM7/DAC2 DMA requests */
#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
((REMAP) == SYSCFG_DMARemap_TIM16) || \
((REMAP) == SYSCFG_DMARemap_ADC2ADC4) || \
((REMAP) == SYSCFG_DMARemap_TIM6DAC1Ch1) || \
((REMAP) == SYSCFG_DMARemap_TIM7DAC1Ch2) || \
((REMAP) == SYSCFG_DMARemap_DAC2Ch1) || \
((REMAP) == SYSCFG_DMARemapCh2_SPI1_RX) || \
((REMAP) == SYSCFG_DMARemapCh4_SPI1_RX) || \
((REMAP) == SYSCFG_DMARemapCh6_SPI1_RX) || \
((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \
((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \
((REMAP) == SYSCFG_DMARemapCh7_SPI1_TX) || \
((REMAP) == SYSCFG_DMARemapCh7_I2C1_RX) || \
((REMAP) == SYSCFG_DMARemapCh3_I2C1_RX) || \
((REMAP) == SYSCFG_DMARemapCh5_I2C1_RX) || \
((REMAP) == SYSCFG_DMARemapCh6_I2C1_TX) || \
((REMAP) == SYSCFG_DMARemapCh2_I2C1_TX) || \
((REMAP) == SYSCFG_DMARemapCh4_I2C1_TX) || \
((REMAP) == SYSCFG_DMARemapCh4_ADC2) || \
((REMAP) == SYSCFG_DMARemapCh2_ADC2))
/**
* @}
*/
/** @defgroup SYSCFG_Trigger_Remap_Config
* @{
*/
#define SYSCFG_TriggerRemap_DACTIM3 SYSCFG_CFGR1_DAC1_TRIG1_RMP /*!< Remap DAC trigger to TIM3 */
#define SYSCFG_TriggerRemap_TIM1TIM17 SYSCFG_CFGR1_TIM1_ITR3_RMP /*!< Remap TIM1 ITR3 to TIM17 OC */
#define SYSCFG_TriggerRemap_DACHRTIM1_TRIG1 ((uint32_t)0x80010000) /*!< Remap DAC trigger to HRTIM1 TRIG1 */
#define SYSCFG_TriggerRemap_DACHRTIM1_TRIG2 ((uint32_t)0x80020000) /*!< Remap DAC trigger to HRTIM1 TRIG2 */
#define IS_SYSCFG_TRIGGER_REMAP(REMAP) (((REMAP) == SYSCFG_TriggerRemap_DACTIM3) || \
((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG1) || \
((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG2) || \
((REMAP) == SYSCFG_TriggerRemap_TIM1TIM17))
/**
* @}
*/
/** @defgroup SYSCFG_EncoderRemap_Config
* @{
*/
#define SYSCFG_EncoderRemap_No ((uint32_t)0x00000000) /*!< No redirection */
#define SYSCFG_EncoderRemap_TIM2 SYSCFG_CFGR1_ENCODER_MODE_0 /*!< Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2 */
#define SYSCFG_EncoderRemap_TIM3 SYSCFG_CFGR1_ENCODER_MODE_1 /*!< Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2 */
#define SYSCFG_EncoderRemap_TIM4 SYSCFG_CFGR1_ENCODER_MODE /*!< Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2 */
#define IS_SYSCFG_ENCODER_REMAP(REMAP) (((REMAP) == SYSCFG_EncoderRemap_No) || \
((REMAP) == SYSCFG_EncoderRemap_TIM2) || \
((REMAP) == SYSCFG_EncoderRemap_TIM3) || \
((REMAP) == SYSCFG_EncoderRemap_TIM4))
/**
* @}
*/
/** @defgroup SYSCFG_I2C_FastModePlus_Config
* @{
*/
#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
((PIN) == SYSCFG_I2CFastModePlus_PB9) || \
((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
((PIN) == SYSCFG_I2CFastModePlus_I2C2))
/**
* @}
*/
/** @defgroup SYSCFG_FPU_Interrupt_Config
* @{
*/
#define SYSCFG_IT_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Inexact Interrupt enable (interrupt disabled by default) */
#define SYSCFG_IT_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Input denormal Interrupt enable */
#define SYSCFG_IT_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Overflow Interrupt enable */
#define SYSCFG_IT_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Underflow Interrupt enable */
#define SYSCFG_IT_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Divide-by-zero Interrupt enable */
#define SYSCFG_IT_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Invalid operation Interrupt enable */
#define IS_SYSCFG_IT(IT) ((((IT) & (uint32_t)0x03FFFFFF) == 0) && ((IT) != 0))
/**
* @}
*/
/** @defgroup SYSCFG_Lock_Config
* @{
*/
#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \
((CONFIG) == SYSCFG_Break_SRAMParity) || \
((CONFIG) == SYSCFG_Break_Lockup))
/**
* @}
*/
/** @defgroup SYSCFG_SRAMWRP_Config
* @{
*/
#define SYSCFG_SRAMWRP_Page0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
#define SYSCFG_SRAMWRP_Page1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
#define SYSCFG_SRAMWRP_Page2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
#define SYSCFG_SRAMWRP_Page3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
#define SYSCFG_SRAMWRP_Page4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
#define SYSCFG_SRAMWRP_Page5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
#define SYSCFG_SRAMWRP_Page6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
#define SYSCFG_SRAMWRP_Page7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
#define IS_SYSCFG_PAGE(PAGE)((((PAGE) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((PAGE) != 0x00000000))
/**
* @}
*/
/** @defgroup SYSCFG_flags_definition
* @{
*/
#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE
#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the SYSCFG configuration to the default reset state **/
void SYSCFG_DeInit(void);
/* SYSCFG configuration functions *********************************************/
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState);
void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap);
void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState);
void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState);
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
void SYSCFG_BypassParityCheckDisable(void);
void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP);
FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F30x_SYSCFG_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f30x_usart.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the USART
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_USART_H
#define __STM32F30x_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup USART
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief USART Init Structure definition
*/
typedef struct
{
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint32_t USART_Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control*/
} USART_InitTypeDef;
/**
* @brief USART Clock Init Structure definition
*/
typedef struct
{
uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */
uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup USART_Exported_Constants
* @{
*/
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3) || \
((PERIPH) == UART4) || \
((PERIPH) == UART5))
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3))
#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3) || \
((PERIPH) == UART4))
/** @defgroup USART_Word_Length
* @{
*/
#define USART_WordLength_8b ((uint32_t)0x00000000)
#define USART_WordLength_9b USART_CR1_M
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
((LENGTH) == USART_WordLength_9b))
/**
* @}
*/
/** @defgroup USART_Stop_Bits
* @{
*/
#define USART_StopBits_1 ((uint32_t)0x00000000)
#define USART_StopBits_2 USART_CR2_STOP_1
#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
((STOPBITS) == USART_StopBits_2) || \
((STOPBITS) == USART_StopBits_1_5))
/**
* @}
*/
/** @defgroup USART_Parity
* @{
*/
#define USART_Parity_No ((uint32_t)0x00000000)
#define USART_Parity_Even USART_CR1_PCE
#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
((PARITY) == USART_Parity_Even) || \
((PARITY) == USART_Parity_Odd))
/**
* @}
*/
/** @defgroup USART_Mode
* @{
*/
#define USART_Mode_Rx USART_CR1_RE
#define USART_Mode_Tx USART_CR1_TE
#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
((MODE) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup USART_Hardware_Flow_Control
* @{
*/
#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
#define USART_HardwareFlowControl_RTS USART_CR3_RTSE
#define USART_HardwareFlowControl_CTS USART_CR3_CTSE
#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == USART_HardwareFlowControl_None) || \
((CONTROL) == USART_HardwareFlowControl_RTS) || \
((CONTROL) == USART_HardwareFlowControl_CTS) || \
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
/**
* @}
*/
/** @defgroup USART_Clock
* @{
*/
#define USART_Clock_Disable ((uint32_t)0x00000000)
#define USART_Clock_Enable USART_CR2_CLKEN
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
((CLOCK) == USART_Clock_Enable))
/**
* @}
*/
/** @defgroup USART_Clock_Polarity
* @{
*/
#define USART_CPOL_Low ((uint32_t)0x00000000)
#define USART_CPOL_High USART_CR2_CPOL
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
/**
* @}
*/
/** @defgroup USART_Clock_Phase
* @{
*/
#define USART_CPHA_1Edge ((uint32_t)0x00000000)
#define USART_CPHA_2Edge USART_CR2_CPHA
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
/**
* @}
*/
/** @defgroup USART_Last_Bit
* @{
*/
#define USART_LastBit_Disable ((uint32_t)0x00000000)
#define USART_LastBit_Enable USART_CR2_LBCL
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
((LASTBIT) == USART_LastBit_Enable))
/**
* @}
*/
/** @defgroup USART_DMA_Requests
* @{
*/
#define USART_DMAReq_Tx USART_CR3_DMAT
#define USART_DMAReq_Rx USART_CR3_DMAR
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
((DMAREQ) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup USART_DMA_Recception_Error
* @{
*/
#define USART_DMAOnError_Enable ((uint32_t)0x00000000)
#define USART_DMAOnError_Disable USART_CR3_DDRE
#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
((DMAERROR) == USART_DMAOnError_Enable))
/**
* @}
*/
/** @defgroup USART_MuteMode_WakeUp_methods
* @{
*/
#define USART_WakeUp_IdleLine ((uint32_t)0x00000000)
#define USART_WakeUp_AddressMark USART_CR1_WAKE
#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
((WAKEUP) == USART_WakeUp_AddressMark))
/**
* @}
*/
/** @defgroup USART_Address_Detection
* @{
*/
#define USART_AddressLength_4b ((uint32_t)0x00000000)
#define USART_AddressLength_7b USART_CR2_ADDM7
#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
((ADDRESS) == USART_AddressLength_7b))
/**
* @}
*/
/** @defgroup USART_StopMode_WakeUp_methods
* @{
*/
#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)
#define USART_WakeUpSource_StartBit USART_CR3_WUS_1
#define USART_WakeUpSource_RXNE (uint32_t)(USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
((SOURCE) == USART_WakeUpSource_StartBit) || \
((SOURCE) == USART_WakeUpSource_RXNE))
/**
* @}
*/
/** @defgroup USART_LIN_Break_Detection_Length
* @{
*/
#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)
#define USART_LINBreakDetectLength_11b USART_CR2_LBDL
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
((LENGTH) == USART_LINBreakDetectLength_11b))
/**
* @}
*/
/** @defgroup USART_IrDA_Low_Power
* @{
*/
#define USART_IrDAMode_LowPower USART_CR3_IRLP
#define USART_IrDAMode_Normal ((uint32_t)0x00000000)
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
((MODE) == USART_IrDAMode_Normal))
/**
* @}
*/
/** @defgroup USART_DE_Polarity
* @{
*/
#define USART_DEPolarity_High ((uint32_t)0x00000000)
#define USART_DEPolarity_Low USART_CR3_DEP
#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
((POLARITY) == USART_DEPolarity_High))
/**
* @}
*/
/** @defgroup USART_Inversion_Pins
* @{
*/
#define USART_InvPin_Tx USART_CR2_TXINV
#define USART_InvPin_Rx USART_CR2_RXINV
#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
((PIN) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup USART_AutoBaudRate_Mode
* @{
*/
#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)
#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0
#define USART_AutoBaudRate_0x7FFrame USART_CR2_ABRMODE_1
#define USART_AutoBaudRate_0x55Frame (USART_CR2_ABRMODE_0 | USART_CR2_ABRMODE_1)
#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
((MODE) == USART_AutoBaudRate_FallingEdge) || \
((MODE) == USART_AutoBaudRate_0x7FFrame) || \
((MODE) == USART_AutoBaudRate_0x55Frame))
/**
* @}
*/
/** @defgroup USART_OVR_DETECTION
* @{
*/
#define USART_OVRDetection_Enable ((uint32_t)0x00000000)
#define USART_OVRDetection_Disable USART_CR3_OVRDIS
#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
((OVR) == USART_OVRDetection_Disable))
/**
* @}
*/
/** @defgroup USART_Request
* @{
*/
#define USART_Request_ABRRQ USART_RQR_ABRRQ
#define USART_Request_SBKRQ USART_RQR_SBKRQ
#define USART_Request_MMRQ USART_RQR_MMRQ
#define USART_Request_RXFRQ USART_RQR_RXFRQ
#define USART_Request_TXFRQ USART_RQR_TXFRQ
#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
((REQUEST) == USART_Request_RXFRQ) || \
((REQUEST) == USART_Request_MMRQ) || \
((REQUEST) == USART_Request_SBKRQ) || \
((REQUEST) == USART_Request_ABRRQ))
/**
* @}
*/
/** @defgroup USART_Flags
* @{
*/
#define USART_FLAG_REACK USART_ISR_REACK
#define USART_FLAG_TEACK USART_ISR_TEACK
#define USART_FLAG_WU USART_ISR_WUF
#define USART_FLAG_RWU USART_ISR_RWU
#define USART_FLAG_SBK USART_ISR_SBKF
#define USART_FLAG_CM USART_ISR_CMF
#define USART_FLAG_BUSY USART_ISR_BUSY
#define USART_FLAG_ABRF USART_ISR_ABRF
#define USART_FLAG_ABRE USART_ISR_ABRE
#define USART_FLAG_EOB USART_ISR_EOBF
#define USART_FLAG_RTO USART_ISR_RTOF
#define USART_FLAG_nCTSS USART_ISR_CTS
#define USART_FLAG_CTS USART_ISR_CTSIF
#define USART_FLAG_LBD USART_ISR_LBD
#define USART_FLAG_TXE USART_ISR_TXE
#define USART_FLAG_TC USART_ISR_TC
#define USART_FLAG_RXNE USART_ISR_RXNE
#define USART_FLAG_IDLE USART_ISR_IDLE
#define USART_FLAG_ORE USART_ISR_ORE
#define USART_FLAG_NE USART_ISR_NE
#define USART_FLAG_FE USART_ISR_FE
#define USART_FLAG_PE USART_ISR_PE
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
/**
* @}
*/
/** @defgroup USART_Interrupt_definition
* @brief USART Interrupt definition
* USART_IT possible values
* Elements values convention: 0xZZZZYYXX
* XX: Position of the corresponding Interrupt
* YY: Register index
* ZZZZ: Flag position
* @{
*/
#define USART_IT_WU ((uint32_t)0x00140316)
#define USART_IT_CM ((uint32_t)0x0011010E)
#define USART_IT_EOB ((uint32_t)0x000C011B)
#define USART_IT_RTO ((uint32_t)0x000B011A)
#define USART_IT_PE ((uint32_t)0x00000108)
#define USART_IT_TXE ((uint32_t)0x00070107)
#define USART_IT_TC ((uint32_t)0x00060106)
#define USART_IT_RXNE ((uint32_t)0x00050105)
#define USART_IT_IDLE ((uint32_t)0x00040104)
#define USART_IT_LBD ((uint32_t)0x00080206)
#define USART_IT_CTS ((uint32_t)0x0009030A)
#define USART_IT_ERR ((uint32_t)0x00000300)
#define USART_IT_ORE ((uint32_t)0x00030300)
#define USART_IT_NE ((uint32_t)0x00020300)
#define USART_IT_FE ((uint32_t)0x00010300)
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
/**
* @}
*/
/** @defgroup USART_Global_definition
* @{
*/
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Initialization and Configuration functions *********************************/
void USART_DeInit(USART_TypeDef* USARTx);
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
/* STOP Mode functions ********************************************************/
void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource);
/* AutoBaudRate functions *****************************************************/
void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
/* Data transfers functions ***************************************************/
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
/* Multi-Processor Communication functions ************************************/
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
/* LIN mode functions *********************************************************/
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
/* Half-duplex mode function **************************************************/
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
/* Smartcard mode functions ***************************************************/
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);
void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);
/* IrDA mode functions ********************************************************/
void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
/* RS485 mode functions *******************************************************/
void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
/* DMA transfers management functions *****************************************/
void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
/* Interrupts and flags management functions **********************************/
void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_USART_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_wwdg.h
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@ -1,109 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_wwdg.h
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file contains all the functions prototypes for the WWDG
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F30x_WWDG_H
#define __STM32F30x_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_Exported_Constants
* @{
*/
/** @defgroup WWDG_Prescaler
* @{
*/
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
((PRESCALER) == WWDG_Prescaler_2) || \
((PRESCALER) == WWDG_Prescaler_4) || \
((PRESCALER) == WWDG_Prescaler_8))
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the WWDG configuration to the default reset state ****/
void WWDG_DeInit(void);
/* Prescaler, Refresh window and Counter configuration functions **************/
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableIT(void);
void WWDG_SetCounter(uint8_t Counter);
/* WWDG activation functions **************************************************/
void WWDG_Enable(uint8_t Counter);
/* Interrupts and flags management functions **********************************/
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F30x_WWDG_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c
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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_can.c
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504
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c
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/**
******************************************************************************
* @file stm32f30x_comp.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the 7 analog comparators (COMP1, COMP2...COMP7) peripheral:
* + Comparators configuration
* + Window mode control
*
@verbatim
==============================================================================
##### COMP Peripheral features #####
==============================================================================
[..]
The device integrates 7 analog comparators COMP1, COMP2...COMP7:
(#) The non inverting input and inverting input can be set to GPIO pins
as shown in table1. COMP Inputs below.
(#) The COMP output is internally is available using COMP_GetOutputLevel()
and can be set on GPIO pins. Refer to table 2. COMP Outputs below.
(#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...)
Refer to table 3. COMP Outputs redirection to embedded timers below.
(#) The comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
mode and only COMP1, COMP3 and COMP5 non inverting input can be used as non-inverting input.
(#) The seven comparators have interrupt capability with wake-up
from Sleep and Stop modes (through the EXTI controller):
(++) COMP1 is internally connected to EXTI Line 21
(++) COMP2 is internally connected to EXTI Line 22
(++) COMP3 is internally connected to EXTI Line 29
(++) COMP4 is internally connected to EXTI Line 30
(++) COMP5 is internally connected to EXTI Line 31
(++) COMP6 is internally connected to EXTI Line 32
(++) COMP7 is internally connected to EXTI Line 33
[..] Table 1. COMP Inputs
+------------------------------------------------------------------------------------------+
| | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|-----------------|----------------|---------------|---------------------------------------|
| | 1/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
| | 1/2 VREFINT | OK | OK | OK | OK | OK | OK | OK |
| | 3/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
| Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK |
| | DAC1 OUT1(PA4) | OK | OK | OK | OK | OK | OK | OK |
| | DAC1 OUT2(PA5) | OK | OK | OK | OK | OK | OK | OK |
| | IO1 | PA0 | PA2 | PD15 | PE8 | PD13 | PD10 | PC0 |
| | IO2 | --- | --- | PB12 | PB2 | PB10 | PB15 | --- |
| | DAC2 OUT1(PA6) | --- | OK | --- | OK | --- | OK | --- |
|-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
| Non Inverting | IO1 | PA1 | PA7 | PB14 | PB0 | PD12 | PD11 | PA0 |
| Input | IO2 | --- | PA3 | PD14 | PE7 | PB13 | PB11 | PC1 |
+------------------------------------------------------------------------------------------+
[..] Table 2. COMP Outputs
+-------------------------------------------------------+
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|-------|-------|-------|-------|-------|-------|-------|
| PA0 | PA2 | PB1 | PC8 | PC7 | PA10 | PC2 |
| PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- |
| PA6 | PA12 | --- | --- | --- | --- | --- |
| PA11 | PB9 | --- | --- | --- | --- | --- |
| PB8 | --- | --- | --- | --- | --- | --- |
+-------------------------------------------------------+
[..] Table 3. COMP Outputs redirection to embedded timers
+----------------------------------------------------------------------------------------------------------------------+
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|----------------|----------------|----------------|----------------|----------------|----------------|----------------|
| TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN |
| | | | | | | |
| TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
| | | | | | | |
| TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN |
| | | | | | | |
| TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
| | | | | | | |
| TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
| + | + | + | + | + | + | + |
| TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
| | | | | | | |
| TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
| | | | | | | |
| TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
| | | | | | | |
| TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
| | | | | | | |
| TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
| | | | | | | |
| TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
| | | | | | | |
| TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
+----------------------------------------------------------------------------------------------------------------------+
[..] Table 4. COMP Outputs blanking sources
+----------------------------------------------------------------------------------------------------------------------+
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|----------------|----------------|----------------|----------------|----------------|----------------|----------------|
| TIM1 OC5 | TIM1 OC5 | TIM1 OC5 | TIM3 OC4 | TIM3 OC3 | TIM2 OC4 | TIM1 OC5 |
| | | | | | | |
| TIM2 OC3 | TIM2 OC3 | -------- | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 |
| | | | | | | |
| TIM3 OC3 | TIM3 OC3 | TIM2 OC4 | TIM15 OC1 | TIM8 BKIN | TIM15 OC2 | TIM15 OC2 |
| | | | | | | |
+----------------------------------------------------------------------------------------------------------------------+
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions to configure and program the Comparators
of all STM32F30x devices.
To use the comparator, perform the following steps:
(#) Enable the SYSCFG APB clock to get write access to comparator
register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
(#) Configure the comparator input in analog mode using GPIO_Init()
(#) Configure the comparator output in alternate function mode
using GPIO_Init() and use GPIO_PinAFConfig() function to map the
comparator output to the GPIO pin
(#) Configure the comparator using COMP_Init() function:
(++) Select the inverting input
(++) Select the non-inverting input
(++) Select the output polarity
(++) Select the output redirection
(++) Select the hysteresis level
(++) Select the power mode
(#) Enable the comparator using COMP_Cmd() function
(#) If required enable the COMP interrupt by configuring and enabling
EXTI line in Interrupt mode and selecting the desired sensitivity
level using EXTI_Init() function. After that enable the comparator
interrupt vector using NVIC_Init() function.
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_comp.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup COMP
* @brief COMP driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* CSR register Mask */
#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00000003)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup COMP_Private_Functions
* @{
*/
/** @defgroup COMP_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes COMP peripheral registers to their default reset values.
* @note Deinitialization can't be performed if the COMP configuration is locked.
* To unlock the configuration, perform a system reset.
* @param COMP_Selection: the selected comparator.
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
* to select the COMP peripheral.
* @param None
* @retval None
*/
void COMP_DeInit(uint32_t COMP_Selection)
{
/*!< Set COMP_CSR register to reset value */
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) = ((uint32_t)0x00000000);
}
/**
* @brief Initializes the COMP peripheral according to the specified parameters
* in COMP_InitStruct
* @note If the selected comparator is locked, initialization can't be performed.
* To unlock the configuration, perform a system reset.
* @note By default, PA1 is selected as COMP1 non inverting input.
* To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
* @param COMP_Selection: the selected comparator.
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
* to select the COMP peripheral.
* @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
* the configuration information for the specified COMP peripheral.
* - COMP_InvertingInput specifies the inverting input of COMP
* - COMP_NonInvertingInput specifies the non inverting input of COMP
* - COMP_Output connect COMP output to selected timer
* input (Input capture / Output Compare Reference Clear / Break Input)
* - COMP_BlankingSrce specifies the blanking source of COMP
* - COMP_OutputPol select output polarity
* - COMP_Hysteresis configures COMP hysteresis value
* - COMP_Mode configures COMP power mode
* @retval None
*/
void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
assert_param(IS_COMP_NONINVERTING_INPUT(COMP_InitStruct->COMP_NonInvertingInput));
assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
assert_param(IS_COMP_BLANKING_SOURCE(COMP_InitStruct->COMP_BlankingSrce));
assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));
assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
/*!< Get the COMPx_CSR register value */
tmpreg = *(__IO uint32_t *) (COMP_BASE + COMP_Selection);
/*!< Clear the COMP1SW1, COMPxINSEL, COMPxOUTSEL, COMPxPOL, COMPxHYST and COMPxMODE bits */
tmpreg &= (uint32_t) (COMP_CSR_CLEAR_MASK);
/*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
/*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
/*!< Set COMPxNONINSEL bits according to COMP_InitStruct->COMP_NonInvertingInput value */
/*!< Set COMPxBLANKING bits according to COMP_InitStruct->COMP_BlankingSrce value */
/*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
/*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
/*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
/*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */
tmpreg |= (uint32_t)(COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_NonInvertingInput |
COMP_InitStruct->COMP_Output | COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_BlankingSrce |
COMP_InitStruct->COMP_Hysteresis | COMP_InitStruct->COMP_Mode);
/*!< Write to COMPx_CSR register */
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) = tmpreg;
}
/**
* @brief Fills each COMP_InitStruct member with its default value.
* @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
{
COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;
COMP_InitStruct->COMP_NonInvertingInput = COMP_NonInvertingInput_IO1;
COMP_InitStruct->COMP_Output = COMP_Output_None;
COMP_InitStruct->COMP_BlankingSrce = COMP_BlankingSrce_None;
COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;
COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;
}
/**
* @brief Enable or disable the COMP peripheral.
* @note If the selected comparator is locked, enable/disable can't be performed.
* To unlock the configuration, perform a system reset.
* @param COMP_Selection: the selected comparator.
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
* to select the COMP peripheral.
* @param NewState: new state of the COMP peripheral.
* This parameter can be: ENABLE or DISABLE.
* When enabled, the comparator compares the non inverting input with
* the inverting input and the comparison result is available
* on comparator output.
* When disabled, the comparator doesn't perform comparison and the
* output level is low.
* @retval None
*/
void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected COMPx peripheral */
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxEN);
}
else
{
/* Disable the selected COMP peripheral */
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxEN);
}
}
/**
* @brief Close or Open the SW1 switch.
* @note If the COMP1 is locked, Close/Open the SW1 switch can't be performed.
* To unlock the configuration, perform a system reset.
* @note This switch is solely intended to redirect signals onto high
* impedance input, such as COMP1 non-inverting input (highly resistive switch)
* @param NewState: New state of the analog switch.
* This parameter can be
* ENABLE so the SW1 is closed; PA1 is connected to PA4
* or DISABLE so the SW1 switch is open; PA1 is disconnected from PA4
* @retval None
*/
void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState)
{
/* Check the parameter */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Close SW1 switch */
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMP1SW1);
}
else
{
/* Open SW1 switch */
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMP1SW1);
}
}
/**
* @brief Return the output level (high or low) of the selected comparator.
* The output level depends on the selected polarity.
* If the polarity is not inverted:
* - Comparator output is low when the non-inverting input is at a lower
* voltage than the inverting input
* - Comparator output is high when the non-inverting input is at a higher
* voltage than the inverting input
* If the polarity is inverted:
* - Comparator output is high when the non-inverting input is at a lower
* voltage than the inverting input
* - Comparator output is low when the non-inverting input is at a higher
* voltage than the inverting input
* @param COMP_Selection: the selected comparator.
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
* to select the COMP peripheral.
* @retval Returns the selected comparator output level: low or high.
*
*/
uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
{
uint32_t compout = 0x0;
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
/* Check if selected comparator output is high */
if ((*(__IO uint32_t *) (COMP_BASE + COMP_Selection) & (COMP_CSR_COMPxOUT)) != 0)
{
compout = COMP_OutputLevel_High;
}
else
{
compout = COMP_OutputLevel_Low;
}
/* Return the comparator output level */
return (uint32_t)(compout);
}
/**
* @}
*/
/** @defgroup COMP_Group2 Window mode control function
* @brief Window mode control function
*
@verbatim
===============================================================================
##### Window mode control function #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the window mode.
* Window mode for comparators makes use of two comparators:
* COMP1 and COM2, COMP3 and COMP4, COMP5 and COMP6.
* In window mode, COMPx and COMPx-1 (where x can be 2, 4 or 6)
* non inverting inputs are connected together and only COMPx-1 non
* inverting input can be used.
* e.g When window mode enabled for COMP4, COMP3 non inverting input (PB14 or PD14)
* is to be used.
* @note If the COMPx is locked, ENABLE/DISABLE the window mode can't be performed.
* To unlock the configuration, perform a system reset.
* @param COMP_Selection: the selected comparator.
* This parameter can be COMP_Selection_COMPx where x can be 2, 4 or 6
* to select the COMP peripheral.
* param NewState: new state of the window mode.
* This parameter can be ENABLE or DISABLE.
* When enbaled, COMPx and COMPx-1 non inverting inputs are connected together.
* When disabled, COMPx and COMPx-1 non inverting inputs are disconnected.
* @retval None
*/
void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_COMP_WINDOW(COMP_Selection));
if (NewState != DISABLE)
{
/* Enable the window mode */
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) COMP_CSR_COMPxWNDWEN;
}
else
{
/* Disable the window mode */
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxWNDWEN);
}
}
/**
* @}
*/
/** @defgroup COMP_Group3 COMP configuration locking function
* @brief COMP1, COMP2,...COMP7 configuration locking function
* COMP1, COMP2,...COMP7 configuration can be locked each separately.
* Unlocking is performed by system reset.
*
@verbatim
===============================================================================
##### Configuration Lock function #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Lock the selected comparator (COMP1/COMP2) configuration.
* @note Locking the configuration means that all control bits are read-only.
* To unlock the comparator configuration, perform a system reset.
* @param COMP_Selection: the selected comparator.
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
* to select the COMP peripheral.
* @retval None
*/
void COMP_LockConfig(uint32_t COMP_Selection)
{
/* Check the parameter */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
/* Set the lock bit corresponding to selected comparator */
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxLOCK);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

354
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c
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@ -1,354 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_crc.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of CRC computation unit peripheral:
* + Configuration of the CRC computation unit
* + CRC computation of one/many 32-bit data
* + CRC Independent register (IDR) access
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(#) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)
function.
(#) Select the polynomial size: 7-bit, 8-bit, 16-bit or 32-bit.
(#) Set the polynomial coefficients using CRC_SetPolynomial();
(#) If required, select the reverse operation on input data
using CRC_ReverseInputDataSelect();
(#) If required, enable the reverse operation on output data
using CRC_ReverseOutputDataCmd(Enable);
(#) If required, set the initialization remainder value using
CRC_SetInitRegister();
(#) use CRC_CalcCRC() function to compute the CRC of a 32-bit data
or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit
data buffer.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_crc.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRC_Private_Functions
* @{
*/
/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions
* @brief Configuration of the CRC computation unit functions
*
@verbatim
===============================================================================
##### CRC configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes CRC peripheral registers to their default reset values.
* @param None
* @retval None
*/
void CRC_DeInit(void)
{
/* Set DR register to reset value */
CRC->DR = 0xFFFFFFFF;
/* Set the POL register to the reset value: 0x04C11DB7 */
CRC->POL = 0x04C11DB7;
/* Reset IDR register */
CRC->IDR = 0x00;
/* Set INIT register to reset value */
CRC->INIT = 0xFFFFFFFF;
/* Reset the CRC calculation unit */
CRC->CR = CRC_CR_RESET;
}
/**
* @brief Resets the CRC calculation unit and sets INIT register content in DR register.
* @param None
* @retval None
*/
void CRC_ResetDR(void)
{
/* Reset CRC generator */
CRC->CR |= CRC_CR_RESET;
}
/**
* @brief Selects the polynomial size.
* @param CRC_PolSize: Specifies the polynomial size.
* This parameter can be:
* @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation
* @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation
* @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation
* @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation
* @retval None
*/
void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize)
{
uint32_t tmpcr = 0;
/* Check the parameter */
assert_param(IS_CRC_POL_SIZE(CRC_PolSize));
/* Get CR register value */
tmpcr = CRC->CR;
/* Reset POL_SIZE bits */
tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE);
/* Set the polynomial size */
tmpcr |= (uint32_t)CRC_PolSize;
/* Write to CR register */
CRC->CR = (uint32_t)tmpcr;
}
/**
* @brief Selects the reverse operation to be performed on input data.
* @param CRC_ReverseInputData: Specifies the reverse operation on input data.
* This parameter can be:
* @arg CRC_ReverseInputData_No: No reverse operation is performed
* @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
* @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
* @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
* @retval None
*/
void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
{
uint32_t tmpcr = 0;
/* Check the parameter */
assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
/* Get CR register value */
tmpcr = CRC->CR;
/* Reset REV_IN bits */
tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
/* Set the reverse operation */
tmpcr |= (uint32_t)CRC_ReverseInputData;
/* Write to CR register */
CRC->CR = (uint32_t)tmpcr;
}
/**
* @brief Enables or disable the reverse operation on output data.
* The reverse operation on output data is performed on 32-bit.
* @param NewState: new state of the reverse operation on output data.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CRC_ReverseOutputDataCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable reverse operation on output data */
CRC->CR |= CRC_CR_REV_OUT;
}
else
{
/* Disable reverse operation on output data */
CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
}
}
/**
* @brief Initializes the INIT register.
* @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register
* @param CRC_InitValue: Programmable initial CRC value
* @retval None
*/
void CRC_SetInitRegister(uint32_t CRC_InitValue)
{
CRC->INIT = CRC_InitValue;
}
/**
* @brief Initializes the polynomail coefficients.
* @param CRC_Pol: Polynomial to be used for CRC calculation.
* @retval None
*/
void CRC_SetPolynomial(uint32_t CRC_Pol)
{
CRC->POL = CRC_Pol;
}
/**
* @}
*/
/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions
* @brief CRC computation of one/many 32-bit data functions
*
@verbatim
===============================================================================
##### CRC computation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Computes the 32-bit CRC of a given data word(32-bit).
* @param CRC_Data: data word(32-bit) to compute its CRC
* @retval 32-bit CRC
*/
uint32_t CRC_CalcCRC(uint32_t CRC_Data)
{
CRC->DR = CRC_Data;
return (CRC->DR);
}
/**
* @brief Computes the 16-bit CRC of a given 16-bit data.
* @param CRC_Data: data half-word(16-bit) to compute its CRC
* @retval 16-bit CRC
*/
uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data)
{
*(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data;
return (CRC->DR);
}
/**
* @brief Computes the 8-bit CRC of a given 8-bit data.
* @param CRC_Data: 8-bit data to compute its CRC
* @retval 8-bit CRC
*/
uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data)
{
*(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data;
return (CRC->DR);
}
/**
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
* @param pBuffer: pointer to the buffer containing the data to be computed
* @param BufferLength: length of the buffer to be computed
* @retval 32-bit CRC
*/
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0;
for(index = 0; index < BufferLength; index++)
{
CRC->DR = pBuffer[index];
}
return (CRC->DR);
}
/**
* @brief Returns the current CRC value.
* @param None
* @retval 32-bit CRC
*/
uint32_t CRC_GetCRC(void)
{
return (CRC->DR);
}
/**
* @}
*/
/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions
* @brief CRC Independent Register (IDR) access (write/read) functions
*
@verbatim
===============================================================================
##### CRC Independent Register (IDR) access functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Stores an 8-bit data in the Independent Data(ID) register.
* @param CRC_IDValue: 8-bit value to be stored in the ID register
* @retval None
*/
void CRC_SetIDRegister(uint8_t CRC_IDValue)
{
CRC->IDR = CRC_IDValue;
}
/**
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
* @param None
* @retval 8-bit value of the ID register
*/
uint8_t CRC_GetIDRegister(void)
{
return (CRC->IDR);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

754
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_dac.c
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@ -1,754 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_dac.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
* + DAC channels configuration: trigger, output buffer, data format
* + DMA management
* + Interrupts and flags management
*
@verbatim
===============================================================================
##### DAC Peripheral features #####
===============================================================================
[..] The device integrates two 12-bit Digital Analog Converters that can
be used independently or simultaneously (dual mode):
(#) DAC1 integrates two DAC channels:
(++) DAC1 channel 1 with DAC1_OUT1 as output
(++) DAC1 channel 2 with DAC1_OUT2 as output
(++) The two channels can be used independently or simultaneously (dual mode)
(#) DAC2 integrates only one channel DAC2 channel 1 with DAC2_OUT1 as output
[..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
DAC_SetChannel1Data()/DAC_SetChannel2Data.
[..] Digital to Analog conversion can be triggered by:
(#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
The used pin (GPIOx_Pin9) must be configured in input mode.
(#) Timers TRGO: TIM2, TIM8/TIM3, TIM4, TIM6, TIM7, and TIM15
(DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
The timer TRGO event should be selected using TIM_SelectOutputTrigger()
(++) To trigger DAC conversions by TIM3 instead of TIM8 follow
this sequence:
(+++) Enable SYSCFG APB clock by calling
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
(+++) Select DAC_Trigger_T3_TRGO when calling DAC_Init()
(+++) Remap the DAC trigger from TIM8 to TIM3 by calling
SYSCFG_TriggerRemapConfig(SYSCFG_TriggerRemap_DACTIM3, ENABLE)
(#) Software using DAC_Trigger_Software
[..] Each DAC channel integrates an output buffer that can be used to
reduce the output impedance, and to drive external loads directly
without having to add an external operational amplifier.
To enable, the output buffer use
DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
[..] Refer to the device datasheet for more details about output impedance
value with and without output buffer.
[..] Both DAC channels can be used to generate:
(+) Noise wave using DAC_WaveGeneration_Noise
(+) Triangle wave using DAC_WaveGeneration_Triangle
[..] Wave generation can be disabled using DAC_WaveGeneration_None
[..] The DAC data format can be:
(+) 8-bit right alignment using DAC_Align_8b_R
(+) 12-bit left alignment using DAC_Align_12b_L
(+) 12-bit right alignment using DAC_Align_12b_R
[..] The analog output voltage on each DAC channel pin is determined
by the following equation:
(+) DAC_OUTx = VREF+ * DOR / 4095 with DOR is the Data Output Register.
VREF+ is the input voltage reference (refer to the device datasheet)
e.g. To set DAC_OUT1 to 0.7V, use DAC_SetChannel1Data(DAC_Align_12b_R, 868);
Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
[..] A DMA1 request can be generated when an external trigger (but not
a software trigger) occurs if DMA1 requests are enabled using
DAC_DMACmd()
DMA1 requests are mapped as following:
(+) DAC channel1 is mapped on DMA1 channel3 which must be already
configured
(+) DAC channel2 is mapped on DMA1 channel4 which must be already
configured
##### How to use this driver #####
===============================================================================
[..]
(+) Enable DAC APB1 clock to get write access to DAC registers
using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
(+) Configure DACx_OUTy (DAC1_OUT1: PA4, DAC1_OUT2: PA5, DAC2_OUT1: PA6)
in analog mode.
(+) Configure the DAC channel using DAC_Init()
(+) Enable the DAC channel using DAC_Cmd()
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_dac.h"
#include "stm32f30x_rcc.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup DAC
* @brief DAC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* CR register Mask */
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
/* DAC Dual Channels SWTRIG masks */
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
/* DHR registers offsets */
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
/* DOR register offset */
#define DOR_OFFSET ((uint32_t)0x0000002C)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DAC_Private_Functions
* @{
*/
/** @defgroup DAC_Group1 DAC channels configuration
* @brief DAC channels configuration: trigger, output buffer, data format
*
@verbatim
===============================================================================
##### DAC channels configuration: trigger, output buffer, data format #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the DAC peripheral registers to their default reset values.
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
* @retval None
*/
void DAC_DeInit(DAC_TypeDef* DACx)
{
/* Check the parameters */
assert_param(IS_DAC_ALL_PERIPH(DACx));
if (DACx == DAC1)
{
/* Enable DAC1 reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, ENABLE);
/* Release DAC1 from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, DISABLE);
}
else
{
/* Enable DAC2 reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, ENABLE);
/* Release DAC2 from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, DISABLE);
}
}
/**
* @brief Initializes the DAC peripheral according to the specified
* parameters in the DAC_InitStruct.
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
* contains the configuration information for the specified DAC channel.
* @retval None
*/
void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_ALL_PERIPH(DACx));
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
assert_param(IS_DAC_BUFFER_SWITCH_STATE(DAC_InitStruct->DAC_Buffer_Switch));
/*---------------------------- DAC CR Configuration --------------------------*/
/* Get the DAC CR value */
tmpreg1 = DACx->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
/* Configure for the selected DAC channel: buffer output, trigger, wave generation,
mask/amplitude for wave generation */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set WAVEx bits according to DAC_WaveGeneration value */
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
/* Set BOFFx OUTENx bit according to DAC_Buffer_Switch value */
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_Buffer_Switch);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << DAC_Channel;
/* Write to DAC CR */
DACx->CR = tmpreg1;
}
/**
* @brief Fills each DAC_InitStruct member with its default value.
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
{
/*--------------- Reset DAC init structure parameters values -----------------*/
/* Initialize the DAC_Trigger member */
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
/* Initialize the DAC_WaveGeneration member */
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
/* Initialize the DAC_Buffer_Switch member */
DAC_InitStruct->DAC_Buffer_Switch = DAC_BufferSwitch_Enable;
}
/**
* @brief Enables or disables the specified DAC channel.
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
* @param DAC_Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the DAC channel.
* This parameter can be: ENABLE or DISABLE.
* @note When the DAC channel is enabled the trigger source can no more
* be modified.
* @retval None
*/
void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_ALL_PERIPH(DACx));
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel */
DACx->CR |= (DAC_CR_EN1 << DAC_Channel);
}
else
{
/* Disable the selected DAC channel */
DACx->CR &= (~(DAC_CR_EN1 << DAC_Channel));
}
}
/**
* @brief Enables or disables the selected DAC channel software trigger.
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel software trigger.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_ALL_PERIPH(DACx));
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for the selected DAC channel */
DACx->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
}
else
{
/* Disable software trigger for the selected DAC channel */
DACx->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
}
}
/**
* @brief Enables or disables simultaneously the two DAC channels software
* triggers.
* @param DACx: where x can be 1 to select the DAC1 peripheral.
* @note Dual trigger is not applicable for DAC2 (DAC2 integrates one channel).
* @param NewState: new state of the DAC channels software triggers.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_LIST1_PERIPH(DACx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for both DAC channels */
DACx->SWTRIGR |= DUAL_SWTRIG_SET;
}
else
{
/* Disable software trigger for both DAC channels */
DACx->SWTRIGR &= DUAL_SWTRIG_RESET;
}
}
/**
* @brief Enables or disables the selected DAC channel wave generation.
* @param DACx: where x can be 1 to select the DAC1 peripheral.
* @note Wave generation is not available in DAC2.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_Wave: Specifies the wave type to enable or disable.
* This parameter can be one of the following values:
* @arg DAC_Wave_Noise: noise wave generation
* @arg DAC_Wave_Triangle: triangle wave generation
* @param NewState: new state of the selected DAC channel wave generation.
* This parameter can be: ENABLE or DISABLE.
* @note
* @retval None
*/
void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_LIST1_PERIPH(DACx));
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_WAVE(DAC_Wave));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected wave generation for the selected DAC channel */
DACx->CR |= DAC_Wave << DAC_Channel;
}
else
{
/* Disable the selected wave generation for the selected DAC channel */
DACx->CR &= ~(DAC_Wave << DAC_Channel);
}
}
/**
* @brief Set the specified data holding register value for DAC channel1.
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
* @param DAC_Align: Specifies the data alignment for DAC channel1.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data: Data to be loaded in the selected data holding register.
* @retval None
*/
void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALL_PERIPH(DACx));
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DACx;
tmp += DHR12R1_OFFSET + DAC_Align;
/* Set the DAC channel1 selected data holding register */
*(__IO uint32_t *) tmp = Data;
}
/**
* @brief Set the specified data holding register value for DAC channel2.
* @param DACx: where x can be 1 to select the DAC peripheral.
* @note This function is available only for DAC1.
* @param DAC_Align: Specifies the data alignment for DAC channel2.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None
*/
void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_LIST1_PERIPH(DACx));
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DACx;
tmp += DHR12R2_OFFSET + DAC_Align;
/* Set the DAC channel2 selected data holding register */
*(__IO uint32_t *)tmp = Data;
}
/**
* @brief Set the specified data holding register value for dual channel DAC.
* @param DACx: where x can be 1 to select the DAC peripheral.
* @note This function isn't applicable for DAC2.
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
* holding register.
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
* holding register.
* @note In dual mode, a unique register access is required to write in both
* DAC channels at the same time.
* @retval None
*/
void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
{
uint32_t data = 0, tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_LIST1_PERIPH(DACx));
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (DAC_Align == DAC_Align_8b_R)
{
data = ((uint32_t)Data2 << 8) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16) | Data1;
}
tmp = (uint32_t)DACx;
tmp += DHR12RD_OFFSET + DAC_Align;
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
}
/**
* @brief Returns the last data output value of the selected DAC channel.
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALL_PERIPH(DACx));
assert_param(IS_DAC_CHANNEL(DAC_Channel));
tmp = (uint32_t) DACx;
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
/* Returns the DAC channel data output register value */
return (uint16_t) (*(__IO uint32_t*) tmp);
}
/**
* @}
*/
/** @defgroup DAC_Group2 DMA management functions
* @brief DMA management functions
*
@verbatim
===============================================================================
##### DMA management functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified DAC channel DMA request.
* When enabled DMA1 is generated when an external trigger (EXTI Line9,
* TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel DMA request.
* This parameter can be: ENABLE or DISABLE.
* @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which
* must be already configured.
* @retval None
*/
void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_ALL_PERIPH(DACx));
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel DMA request */
DACx->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
}
else
{
/* Disable the selected DAC channel DMA request */
DACx->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
}
}
/**
* @}
*/
/** @defgroup DAC_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
##### Interrupts and flags management functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified DAC interrupts.
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @note The DMA underrun occurs when a second external trigger arrives before
* the acknowledgement for the first external trigger is received (first request).
* @param NewState: new state of the specified DAC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_ALL_PERIPH(DACx));
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_DAC_IT(DAC_IT));
if (NewState != DISABLE)
{
/* Enable the selected DAC interrupts */
DACx->CR |= (DAC_IT << DAC_Channel);
}
else
{
/* Disable the selected DAC interrupts */
DACx->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
}
}
/**
* @brief Checks whether the specified DAC flag is set or not.
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
* @param DAC_Channel: thee selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_FLAG: specifies the flag to check.
* This parameter can be:
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
* @note The DMA underrun occurs when a second external trigger arrives before
* the acknowledgement for the first external trigger is received (first request).
* @retval The new state of DAC_FLAG (SET or RESET).
*/
FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_DAC_ALL_PERIPH(DACx));
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_FLAG(DAC_FLAG));
/* Check the status of the specified DAC flag */
if ((DACx->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
{
/* DAC_FLAG is set */
bitstatus = SET;
}
else
{
/* DAC_FLAG is reset */
bitstatus = RESET;
}
/* Return the DAC_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DAC channel's pending flags.
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_FLAG: specifies the flag to clear.
* This parameter can be:
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
* @retval None
*/
void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG)
{
/* Check the parameters */
assert_param(IS_DAC_ALL_PERIPH(DACx));
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_FLAG(DAC_FLAG));
/* Clear the selected DAC flags */
DACx->SR = (DAC_FLAG << DAC_Channel);
}
/**
* @brief Checks whether the specified DAC interrupt has occurred or not.
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt source to check.
* This parameter can be:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @note The DMA underrun occurs when a second external trigger arrives before
* the acknowledgement for the first external trigger is received (first request).
* @retval The new state of DAC_IT (SET or RESET).
*/
ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_DAC_ALL_PERIPH(DACx));
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_IT(DAC_IT));
/* Get the DAC_IT enable bit status */
enablestatus = (DACx->CR & (DAC_IT << DAC_Channel)) ;
/* Check the status of the specified DAC interrupt */
if (((DACx->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
{
/* DAC_IT is set */
bitstatus = SET;
}
else
{
/* DAC_IT is reset */
bitstatus = RESET;
}
/* Return the DAC_IT status */
return bitstatus;
}
/**
* @brief Clears the DAC channel's interrupt pending bits.
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @retval None
*/
void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT)
{
/* Check the parameters */
assert_param(IS_DAC_ALL_PERIPH(DACx));
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_IT(DAC_IT));
/* Clear the selected DAC interrupt pending bits */
DACx->SR = (DAC_IT << DAC_Channel);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

213
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c
View file

@ -1,213 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_dbgmcu.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Debug MCU (DBGMCU) peripheral:
* + Device and Revision ID management
* + Peripherals Configuration
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_dbgmcu.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup DBGMCU
* @brief DBGMCU driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DBGMCU_Private_Functions
* @{
*/
/** @defgroup DBGMCU_Group1 Device and Revision ID management functions
* @brief Device and Revision ID management functions
*
@verbatim
==============================================================================
##### Device and Revision ID management functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Returns the device revision identifier.
* @param None
* @retval Device revision identifier
*/
uint32_t DBGMCU_GetREVID(void)
{
return(DBGMCU->IDCODE >> 16);
}
/**
* @brief Returns the device identifier.
* @param None
* @retval Device identifier
*/
uint32_t DBGMCU_GetDEVID(void)
{
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
}
/**
* @}
*/
/** @defgroup DBGMCU_Group2 Peripherals Configuration functions
* @brief Peripherals Configuration
*
@verbatim
==============================================================================
##### Peripherals Configuration functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Configures low power mode behavior when the MCU is in Debug mode.
* @param DBGMCU_Periph: specifies the low power mode.
* This parameter can be any combination of the following values:
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode.
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode.
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode.
* @param NewState: new state of the specified low power mode in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->CR |= DBGMCU_Periph;
}
else
{
DBGMCU->CR &= ~DBGMCU_Periph;
}
}
/**
* @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
* @param DBGMCU_Periph: specifies the APB1 peripheral.
* This parameter can be any combination of the following values:
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted.
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted.
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted.
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted.
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted.
* @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter are stopped when
* Core is halted.
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted.
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted.
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when
* Core is halted.
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when
* Core is halted.
* @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted.
* @param NewState: new state of the specified APB1 peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->APB1FZ |= DBGMCU_Periph;
}
else
{
DBGMCU->APB1FZ &= ~DBGMCU_Periph;
}
}
/**
* @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
* @param DBGMCU_Periph: specifies the APB2 peripheral.
* This parameter can be any combination of the following values:
* @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted.
* @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted.
* @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted.
* @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted.
* @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted.
* @param NewState: new state of the specified APB2 peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->APB2FZ |= DBGMCU_Periph;
}
else
{
DBGMCU->APB2FZ &= ~DBGMCU_Periph;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

866
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c
View file

@ -1,866 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_dma.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access controller (DMA):
* + Initialization and Configuration
* + Data Counter
* + Interrupts and flags management
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(#) Enable The DMA controller clock using
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or
using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
(#) Enable and configure the peripheral to be connected to the DMA channel
(except for internal SRAM / FLASH memories: no initialization is necessary).
(#) For a given Channel, program the Source and Destination addresses,
the transfer Direction, the Buffer Size, the Peripheral and Memory
Incrementation mode and Data Size, the Circular or Normal mode,
the channel transfer Priority and the Memory-to-Memory transfer
mode (if needed) using the DMA_Init() function.
(#) Enable the NVIC and the corresponding interrupt(s) using the function
DMA_ITConfig() if you need to use DMA interrupts.
(#) Enable the DMA channel using the DMA_Cmd() function.
(#) Activate the needed channel Request using PPP_DMACmd() function for
any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
The function allowing this operation is provided in each PPP peripheral
driver (ie. SPI_DMACmd for SPI peripheral).
(#) Optionally, you can configure the number of data to be transferred
when the channel is disabled (ie. after each Transfer Complete event
or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
And you can get the number of remaining data to be transferred using
the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
enabled and running).
(#) To control DMA events you can use one of the following two methods:
(##) Check on DMA channel flags using the function DMA_GetFlagStatus().
(##) Use DMA interrupts through the function DMA_ITConfig() at initialization
phase and DMA_GetITStatus() function into interrupt routines in
communication phase.
After checking on a flag you should clear it using DMA_ClearFlag()
function. And after checking on an interrupt event you should
clear it using DMA_ClearITPendingBit() function.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_dma.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup DMA
* @brief DMA driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
#define FLAG_Mask ((uint32_t)0x10000000) /* DMA2 FLAG mask */
/* DMA1 Channelx interrupt pending bit masks */
#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
/* DMA2 Channelx interrupt pending bit masks */
#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DMA_Private_Functions
* @{
*/
/** @defgroup DMA_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This subsection provides functions allowing to initialize the DMA channel
source and destination addresses, incrementation and data sizes, transfer
direction, buffer size, circular/normal mode selection, memory-to-memory
mode selection and channel priority value.
[..] The DMA_Init() function follows the DMA configuration procedures as described
in reference manual (RM00316).
@endverbatim
* @{
*/
/**
* @brief Deinitializes the DMAy Channelx registers to their default reset
* values.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @retval None
*/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
/* Reset DMAy Channelx control register */
DMAy_Channelx->CCR = 0;
/* Reset DMAy Channelx remaining bytes register */
DMAy_Channelx->CNDTR = 0;
/* Reset DMAy Channelx peripheral address register */
DMAy_Channelx->CPAR = 0;
/* Reset DMAy Channelx memory address register */
DMAy_Channelx->CMAR = 0;
if (DMAy_Channelx == DMA1_Channel1)
{
/* Reset interrupt pending bits for DMA1 Channel1 */
DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
}
else if (DMAy_Channelx == DMA1_Channel2)
{
/* Reset interrupt pending bits for DMA1 Channel2 */
DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
}
else if (DMAy_Channelx == DMA1_Channel3)
{
/* Reset interrupt pending bits for DMA1 Channel3 */
DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
}
else if (DMAy_Channelx == DMA1_Channel4)
{
/* Reset interrupt pending bits for DMA1 Channel4 */
DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
}
else if (DMAy_Channelx == DMA1_Channel5)
{
/* Reset interrupt pending bits for DMA1 Channel5 */
DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
}
else if (DMAy_Channelx == DMA1_Channel6)
{
/* Reset interrupt pending bits for DMA1 Channel6 */
DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
}
else if (DMAy_Channelx == DMA1_Channel7)
{
/* Reset interrupt pending bits for DMA1 Channel7 */
DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
}
else if (DMAy_Channelx == DMA2_Channel1)
{
/* Reset interrupt pending bits for DMA2 Channel1 */
DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
}
else if (DMAy_Channelx == DMA2_Channel2)
{
/* Reset interrupt pending bits for DMA2 Channel2 */
DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
}
else if (DMAy_Channelx == DMA2_Channel3)
{
/* Reset interrupt pending bits for DMA2 Channel3 */
DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
}
else if (DMAy_Channelx == DMA2_Channel4)
{
/* Reset interrupt pending bits for DMA2 Channel4 */
DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
}
else
{
if (DMAy_Channelx == DMA2_Channel5)
{
/* Reset interrupt pending bits for DMA2 Channel5 */
DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
}
}
}
/**
* @brief Initializes the DMAy Channelx according to the specified parameters
* in the DMA_InitStruct.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
/* Get the DMAy_Channelx CCR value */
tmpreg = DMAy_Channelx->CCR;
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmpreg &= CCR_CLEAR_MASK;
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
/* Set DIR bit according to DMA_DIR value */
/* Set CIRC bit according to DMA_Mode value */
/* Set PINC bit according to DMA_PeripheralInc value */
/* Set MINC bit according to DMA_MemoryInc value */
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
/* Set MSIZE bits according to DMA_MemoryDataSize value */
/* Set PL bits according to DMA_Priority value */
/* Set the MEM2MEM bit according to DMA_M2M value */
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
/* Write to DMAy Channelx CCR */
DMAy_Channelx->CCR = tmpreg;
/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
/* Write to DMAy Channelx CNDTR */
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
/* Write to DMAy Channelx CPAR */
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
/* Write to DMAy Channelx CMAR */
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
}
/**
* @brief Fills each DMA_InitStruct member with its default value.
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
{
/*-------------- Reset DMA init structure parameters values ------------------*/
/* Initialize the DMA_PeripheralBaseAddr member */
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
/* Initialize the DMA_MemoryBaseAddr member */
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
/* Initialize the DMA_DIR member */
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
/* Initialize the DMA_BufferSize member */
DMA_InitStruct->DMA_BufferSize = 0;
/* Initialize the DMA_PeripheralInc member */
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
/* Initialize the DMA_MemoryInc member */
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
/* Initialize the DMA_PeripheralDataSize member */
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
/* Initialize the DMA_MemoryDataSize member */
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
/* Initialize the DMA_Mode member */
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
/* Initialize the DMA_Priority member */
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
/* Initialize the DMA_M2M member */
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
}
/**
* @brief Enables or disables the specified DMAy Channelx.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param NewState: new state of the DMAy Channelx.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMAy Channelx */
DMAy_Channelx->CCR |= DMA_CCR_EN;
}
else
{
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
}
}
/**
* @}
*/
/** @defgroup DMA_Group2 Data Counter functions
* @brief Data Counter functions
*
@verbatim
===============================================================================
##### Data Counter functions #####
===============================================================================
[..] This subsection provides function allowing to configure and read the buffer
size (number of data to be transferred).The DMA data counter can be written
only when the DMA channel is disabled (ie. after transfer complete event).
[..] The following function can be used to write the Channel data counter value:
(+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber).
[..]
(@) It is advised to use this function rather than DMA_Init() in situations
where only the Data buffer needs to be reloaded.
[..] The DMA data counter can be read to indicate the number of remaining transfers
for the relative DMA channel. This counter is decremented at the end of each
data transfer and when the transfer is complete:
(+) If Normal mode is selected: the counter is set to 0.
(+) If Circular mode is selected: the counter is reloaded with the initial
value(configured before enabling the DMA channel).
[..] The following function can be used to read the Channel data counter value:
(+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
@endverbatim
* @{
*/
/**
* @brief Sets the number of data units in the current DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DataNumber: The number of data units in the current DMAy Channelx
* transfer.
* @note This function can only be used when the DMAy_Channelx is disabled.
* @retval None.
*/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
/* Write to DMAy Channelx CNDTR */
DMAy_Channelx->CNDTR = DataNumber;
}
/**
* @brief Returns the number of remaining data units in the current
* DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @retval The number of remaining data units in the current DMAy Channelx
* transfer.
*/
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Return the number of remaining data units for DMAy Channelx */
return ((uint16_t)(DMAy_Channelx->CNDTR));
}
/**
* @}
*/
/** @defgroup DMA_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
##### Interrupts and flags management functions #####
===============================================================================
[..] This subsection provides functions allowing to configure the DMA Interrupt
sources and check or clear the flags or pending bits status.
The user should identify which mode will be used in his application to manage
the DMA controller events: Polling mode or Interrupt mode.
*** Polling Mode ***
====================
[..] Each DMA channel can be managed through 4 event Flags (y : DMA Controller
number, x : DMA channel number):
(#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
(#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
(#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
(#) DMAy_FLAG_GLx : to indicate that at least one of the events described
above occurred.
[..]
(@) Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
[..] In this Mode it is advised to use the following functions:
(+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
(+) void DMA_ClearFlag(uint32_t DMA_FLAG);
*** Interrupt Mode ***
======================
[..] Each DMA channel can be managed through 4 Interrupts:
(+) Interrupt Source
(##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
event.
(##) DMA_IT_HT: specifies the interrupt source for the Half-transfer Complete
event.
(##) DMA_IT_TE: specifies the interrupt source for the transfer errors event.
(##) DMA_IT_GL: to indicate that at least one of the interrupts described
above occurred.
-@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
[..] In this Mode it is advised to use the following functions:
(+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
(+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
(+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified DMAy Channelx interrupts.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
* or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @param NewState: new state of the specified DMA interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA interrupts */
DMAy_Channelx->CCR |= DMA_IT;
}
else
{
/* Disable the selected DMA interrupts */
DMAy_Channelx->CCR &= ~DMA_IT;
}
}
/**
* @brief Checks whether the specified DMAy Channelx flag is set or not.
* @param DMAy_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
*
* @note
* The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
* relative to the same channel is set (Transfer Complete, Half-transfer
* Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
* DMAy_FLAG_TEx).
*
* @retval The new state of DMAy_FLAG (SET or RESET).
*/
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
/* Calculate the used DMAy */
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
{
/* Get DMA2 ISR register value */
tmpreg = DMA2->ISR ;
}
else
{
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR ;
}
/* Check the status of the specified DMAy flag */
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
{
/* DMAy_FLAG is set */
bitstatus = SET;
}
else
{
/* DMAy_FLAG is reset */
bitstatus = RESET;
}
/* Return the DMAy_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DMAy Channelx's pending flags.
* @param DMAy_FLAG: specifies the flag to clear.
* This parameter can be any combination (for the same DMA) of the following values:
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
*
* @note
* Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
* relative to the same channel (Transfer Complete, Half-transfer Complete and
* Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
*
* @retval None
*/
void DMA_ClearFlag(uint32_t DMAy_FLAG)
{
/* Check the parameters */
assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
/* Calculate the used DMAy */
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
{
/* Clear the selected DMAy flags */
DMA2->IFCR = DMAy_FLAG;
}
else
{
/* Clear the selected DMAy flags */
DMA1->IFCR = DMAy_FLAG;
}
}
/**
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
* @param DMAy_IT: specifies the DMAy interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
*
* @note
* The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
* interrupts relative to the same channel is set (Transfer Complete,
* Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
* DMAy_IT_HTx or DMAy_IT_TEx).
*
* @retval The new state of DMAy_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_IT(DMAy_IT));
/* Calculate the used DMA */
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
{
/* Get DMA2 ISR register value */
tmpreg = DMA2->ISR;
}
else
{
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR;
}
/* Check the status of the specified DMAy interrupt */
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
{
/* DMAy_IT is set */
bitstatus = SET;
}
else
{
/* DMAy_IT is reset */
bitstatus = RESET;
}
/* Return the DMAy_IT status */
return bitstatus;
}
/**
* @brief Clears the DMAy Channelx's interrupt pending bits.
* @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
* This parameter can be any combination (for the same DMA) of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
*
* @note
* Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
* interrupts relative to the same channel (Transfer Complete, Half-transfer
* Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
* DMAy_IT_TEx).
*
* @retval None
*/
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
{
/* Check the parameters */
assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
/* Calculate the used DMAy */
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
{
/* Clear the selected DMAy interrupt pending bits */
DMA2->IFCR = DMAy_IT;
}
else
{
/* Clear the selected DMAy interrupt pending bits */
DMA1->IFCR = DMAy_IT;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

349
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c
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@ -1,349 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_exti.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the EXTI peripheral:
* + Initialization and Configuration
* + Interrupts and flags management
*
@verbatim
===============================================================================
##### EXTI features #####
===============================================================================
[..] External interrupt/event lines are mapped as following:
(#) All available GPIO pins are connected to the 16 external
interrupt/event lines from EXTI0 to EXTI15.
(#) EXTI line 16 is connected to the PVD output
(#) EXTI line 17 is connected to the RTC Alarm event
(#) EXTI line 18 is connected to USB Device wakeup event
(#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events
(#) EXTI line 20 is connected to the RTC wakeup event
(#) EXTI line 21 is connected to the Comparator 1 wakeup event
(#) EXTI line 22 is connected to the Comparator 2 wakeup event
(#) EXTI line 23 is connected to the I2C1 wakeup event
(#) EXTI line 24 is connected to the I2C2 wakeup event
(#) EXTI line 25 is connected to the USART1 wakeup event
(#) EXTI line 26 is connected to the USART2 wakeup event
(#) EXTI line 27 is reserved
(#) EXTI line 28 is connected to the USART3 wakeup event
(#) EXTI line 29 is connected to the Comparator 3 event
(#) EXTI line 30 is connected to the Comparator 4 event
(#) EXTI line 31 is connected to the Comparator 5 event
(#) EXTI line 32 is connected to the Comparator 6 event
(#) EXTI line 33 is connected to the Comparator 7 event
(#) EXTI line 34 is connected for thr UART4 wakeup event
(#) EXTI line 35 is connected for the UART5 wakeup event
##### How to use this driver #####
===============================================================================
[..] In order to use an I/O pin as an external interrupt source,
follow steps below:
(#) Configure the I/O in input mode using GPIO_Init().
(#) Select the input source pin for the EXTI line using
SYSCFG_EXTILineConfig().
(#) Select the mode(interrupt, event) and configure the trigger
selection (Rising, falling or both) using EXTI_Init(). For the
internal interrupt, the trigger selection is not needed
(the active edge is always the rising one).
(#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
(#) Optionally, you can generate a software interrupt using the function
EXTI_GenerateSWInterrupt().
[..]
(@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_exti.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup EXTI
* @brief EXTI driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup EXTI_Private_Functions
* @{
*/
/** @defgroup EXTI_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the EXTI peripheral registers to their default reset
* values.
* @param None
* @retval None
*/
void EXTI_DeInit(void)
{
EXTI->IMR = 0x1F800000;
EXTI->EMR = 0x00000000;
EXTI->RTSR = 0x00000000;
EXTI->FTSR = 0x00000000;
EXTI->SWIER = 0x00000000;
EXTI->PR = 0xE07FFFFF;
EXTI->IMR2 = 0x0000000C;
EXTI->EMR2 = 0x00000000;
EXTI->RTSR2 = 0x00000000;
EXTI->FTSR2 = 0x00000000;
EXTI->SWIER2 = 0x00000000;
EXTI->PR2 = 0x00000003;
}
/**
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
* EXTI_Line specifies the EXTI line (EXTI0....EXTI35).
* EXTI_Mode specifies which EXTI line is used as interrupt or an event.
* EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
* pending bit will be set.
* EXTI_LineCmd controls (Enable/Disable) the EXTI line.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that
* contains the configuration information for the EXTI peripheral.
* @retval None
*/
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
{
uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
assert_param(IS_EXTI_LINE_ALL(EXTI_InitStruct->EXTI_Line));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
tmp = (uint32_t)EXTI_BASE;
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
/* Clear EXTI line configuration */
*(__IO uint32_t *) (((uint32_t) &(EXTI->IMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
*(__IO uint32_t *) (((uint32_t) &(EXTI->EMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
*(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
tmp = (uint32_t)EXTI_BASE;
/* Clear Rising Falling edge configuration */
*(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
/* Select the trigger for the selected interrupts */
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{
/* Rising Falling edge */
*(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
}
else
{
tmp += EXTI_InitStruct->EXTI_Trigger + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
*(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
}
}
else
{
tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
/* Disable the selected external lines */
*(__IO uint32_t *) tmp &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
}
}
/**
* @brief Fills each EXTI_InitStruct member with its reset value.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Rising_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/**
* @brief Generates a Software interrupt on selected EXTI line.
* @param EXTI_Line: specifies the EXTI line on which the software interrupt
* will be generated.
* This parameter can be any combination of EXTI_Linex where x can be (0..20).
* @retval None
*/
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER)) + ((EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_Line & 0x1F));
}
/**
* @}
*/
/** @defgroup EXTI_Group2 Interrupts and flags management functions
* @brief EXTI Interrupts and flags management functions
*
@verbatim
===============================================================================
##### Interrupts and flags management functions #####
===============================================================================
[..]
This section provides functions allowing to configure the EXTI Interrupts
sources and check or clear the flags or pending bits status.
@endverbatim
* @{
*/
/**
* @brief Checks whether the specified EXTI line flag is set or not.
* @param EXTI_Line: specifies the EXTI line flag to check.
* This parameter can be any combination of EXTI_Linex where x can be (0..20).
* @retval The new state of EXTI_Line (SET or RESET).
*/
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the EXTI's line pending flags.
* @param EXTI_Line: specifies the EXTI lines flags to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..20).
* @retval None
*/
void EXTI_ClearFlag(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
}
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param EXTI_Line: specifies the EXTI line to check.
* This parameter can be any combination of EXTI_Linex where x can be (0..20).
* @retval The new state of EXTI_Line (SET or RESET).
*/
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the EXTI's line pending bits.
* @param EXTI_Line: specifies the EXTI lines to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..20).
* @retval None
*/
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1170
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c
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535
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c
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/**
******************************************************************************
* @file stm32f30x_gpio.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral:
* + Initialization and Configuration functions
* + GPIO Read and Write functions
* + GPIO Alternate functions configuration functions
*
* @verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
(#) Configure the GPIO pin(s) using GPIO_Init()
Four possible configuration are available for each pin:
(++) Input: Floating, Pull-up, Pull-down.
(++) Output: Push-Pull (Pull-up, Pull-down or no Pull),
Open Drain (Pull-up, Pull-down or no Pull).
In output mode, the speed is configurable: Low, Medium, Fast or High.
(++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull),
Open Drain (Pull-up, Pull-down or no Pull).
(++) Analog: required mode when a pin is to be used as ADC channel,
DAC output or comparator input.
(#) Peripherals alternate function:
(++) For ADC, DAC and comparators, configure the desired pin in
analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
(++) For other peripherals (TIM, USART...):
(+++) Connect the pin to the desired peripherals' Alternate
Function (AF) using GPIO_PinAFConfig() function.
(+++) Configure the desired pin in alternate function mode using
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
(+++) Select the type, pull-up/pull-down and output speed via
GPIO_PuPd, GPIO_OType and GPIO_Speed members.
(+++) Call GPIO_Init() function.
(#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
(#) To set/reset the level of a pin configured in output mode use
GPIO_SetBits()/GPIO_ResetBits()
(#) During and just after reset, the alternate functions are not active
and the GPIO pins are configured in input floating mode (except JTAG pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
general-purpose (PC14 and PC15, respectively) when the LSE
oscillator is off. The LSE has priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose
(PF0 and PF1 respectively) when the HSE oscillator is off. The HSE has
the priority over the GPIO function.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_gpio.h"
#include "stm32f30x_rcc.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup GPIO
* @brief GPIO driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Functions
* @{
*/
/** @defgroup GPIO_Group1 Initialization and Configuration
* @brief Initialization and Configuration
*
@verbatim
===============================================================================
##### Initialization and Configuration #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the GPIOx peripheral registers to their default reset
* values.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @retval None
*/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
if(GPIOx == GPIOA)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
}
else if(GPIOx == GPIOB)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
}
else if(GPIOx == GPIOC)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
}
else if(GPIOx == GPIOD)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
}
else if(GPIOx == GPIOE)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
}
else
{
if(GPIOx == GPIOF)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
}
}
}
/**
* @brief Initializes the GPIOx peripheral according to the specified
* parameters in the GPIO_InitStruct.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO
* peripheral.
* @note GPIO_Pin: selects the pin to be configured:
* GPIO_Pin_0->GPIO_Pin_15 for GPIOA, GPIOB, GPIOC, GPIOD and GPIOE;
* GPIO_Pin_0->GPIO_Pin_2, GPIO_Pin_4, GPIO_Pin_6, GPIO_Pin_9
* and GPIO_Pin_10 for GPIOF.
* @retval None
*/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
uint32_t tmpreg = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
/*-------------------------- Configure the port pins -----------------------*/
/*-- GPIO Mode Configuration --*/
for (pinpos = 0x00; pinpos < 0x10; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
/* Get the port pins position */
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if (currentpin == pos)
{
if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
{
/* Check Speed mode parameters */
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
/* Speed mode configuration */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
/* Check Output mode parameters */
assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
/* Output mode configuration */
GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
}
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
/* Use temporary variable to update PUPDR register configuration, to avoid
unexpected transition in the GPIO pin configuration. */
tmpreg = GPIOx->PUPDR;
tmpreg &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
tmpreg |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
GPIOx->PUPDR = tmpreg;
}
}
}
/**
* @brief Fills each GPIO_InitStruct member with its default value.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
}
/**
* @brief Locks GPIO Pins configuration registers.
* The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx: where x can be (A or B or D) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint32_t tmp = 0x00010000;
/* Check the parameters */
assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
tmp |= GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Reset LCKK bit */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Read LCKK bit */
tmp = GPIOx->LCKR;
/* Read LCKK bit */
tmp = GPIOx->LCKR;
}
/**
* @}
*/
/** @defgroup GPIO_Group2 GPIO Read and Write
* @brief GPIO Read and Write
*
@verbatim
===============================================================================
##### GPIO Read and Write #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* @note This parameter can be GPIO_Pin_x where x can be :
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
* (0..2, 4, 6, 9..10) for GPIOF.
* @retval The input port pin value.
*/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @retval The input port pin value.
*/
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint16_t)GPIOx->IDR);
}
/**
* @brief Reads the specified output data port bit.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_Pin: Specifies the port bit to read.
* @note This parameter can be GPIO_Pin_x where x can be :
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
* (0..2, 4, 6, 9..10) for GPIOF.
* @retval The output port pin value.
*/
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/**
* @brief Reads the specified GPIO output data port.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @retval GPIO output data port value.
*/
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint16_t)GPIOx->ODR);
}
/**
* @brief Sets the selected data port bits.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* @note This parameter can be GPIO_Pin_x where x can be :
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
* (0..2, 4, 6, 9..10) for GPIOF.
* @retval None
*/
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BSRR = GPIO_Pin;
}
/**
* @brief Clears the selected data port bits.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* @note This parameter can be GPIO_Pin_x where x can be :
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
* (0..2, 4, 6, 9..10) for GPIOF.
* @retval None
*/
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BRR = GPIO_Pin;
}
/**
* @brief Sets or clears the selected data port bit.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* @note This parameter can be GPIO_Pin_x where x can be :
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
* (0..2, 4, 6, 9..10) for GPIOF.
* @param BitVal: specifies the value to be written to the selected bit.
* This parameter can be one of the BitAction enumeration values:
* @arg Bit_RESET: to clear the port pin
* @arg Bit_SET: to set the port pin
* @retval None
*/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_BIT_ACTION(BitVal));
if (BitVal != Bit_RESET)
{
GPIOx->BSRR = GPIO_Pin;
}
else
{
GPIOx->BRR = GPIO_Pin ;
}
}
/**
* @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param PortVal: specifies the value to be written to the port output data
* register.
* @retval None
*/
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
GPIOx->ODR = PortVal;
}
/**
* @}
*/
/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
* @brief GPIO Alternate functions configuration functions
*
@verbatim
===============================================================================
##### GPIO Alternate functions configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
* @param GPIO_PinSource: specifies the pin for the Alternate function.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* @param GPIO_AF: selects the pin to be used as Alternate function.
* This parameter can be one of the following value:
* @arg GPIO_AF_0: JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT, MCO, NJTRST,
* TRACED, TRACECK.
* @arg GPIO_AF_1: OUT, TIM2, TIM15, TIM16, TIM17.
* @arg GPIO_AF_2: COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16.
* @arg GPIO_AF_3: COMP7_OUT, TIM8, TIM15, Touch, HRTIM.
* @arg GPIO_AF_4: I2C1, I2C2, TIM1, TIM8, TIM16, TIM17.
* @arg GPIO_AF_5: IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5
* @arg GPIO_AF_6: IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8
* @arg GPIO_AF_7: AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT, USART1,
* USART2, USART3.
* @arg GPIO_AF_8: COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT, COMP5_OUT,
* COMP6_OUT.
* @arg GPIO_AF_9: AOP4_OUT, CAN, TIM1, TIM8, TIM15.
* @arg GPIO_AF_10: AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17.
* @arg GPIO_AF_11: TIM1, TIM8.
* @arg GPIO_AF_12: TIM1, HRTIM.
* @arg GPIO_AF_13: HRTIM, AOP2_OUT.
* @arg GPIO_AF_14: USBDM, USBDP.
* @arg GPIO_AF_15: OUT.
* @note The pin should already been configured in Alternate Function mode(AF)
* using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
* @note Refer to the Alternate function mapping table in the device datasheet
* for the detailed mapping of the system and peripherals alternate
* function I/O pins.
* @retval None
*/
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
{
uint32_t temp = 0x00;
uint32_t temp_2 = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
assert_param(IS_GPIO_AF(GPIO_AF));
temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_hrtim.c
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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c
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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_iwdg.c
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/**
******************************************************************************
* @file stm32f30x_iwdg.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Independent watchdog (IWDG) peripheral:
* + Prescaler and Counter configuration
* + IWDG activation
* + Flag management
*
@verbatim
===============================================================================
##### IWDG features #####
===============================================================================
[..] The IWDG can be started by either software or hardware (configurable
through option byte).
[..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
thus stays active even if the main clock fails.
Once the IWDG is started, the LSI is forced ON and cannot be disabled
(LSI cannot be disabled too), and the counter starts counting down from
the reset value of 0xFFF. When it reaches the end of count value (0x000)
a system reset is generated.
The IWDG counter should be reloaded at regular intervals to prevent
an MCU reset.
[..] The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
[..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
reset occurs.
[..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
The IWDG timeout may vary due to LSI frequency dispersion. STM32F30x
devices provide the capability to measure the LSI frequency (LSI clock
connected internally to TIM16 CH1 input capture). The measured value
can be used to have an IWDG timeout with an acceptable accuracy.
For more information, please refer to the STM32F30x Reference manual.
##### How to use this driver #####
===============================================================================
[..] This driver allows to use IWDG peripheral with either window option enabled
or disabled. To do so follow one of the two procedures below.
(#) Window option is enabled:
(++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
in software mode (no need to enable the LSI, it will be enabled
by hardware).
(++) Enable write access to IWDG_PR and IWDG_RLR registers using
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
(++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
(++) Configure the IWDG counter value using IWDG_SetReload() function.
This value will be loaded in the IWDG counter each time the counter
is reloaded, then the IWDG will start counting down from this value.
(++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
(++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
(#) Window option is disabled:
(++) Enable write access to IWDG_PR and IWDG_RLR registers using
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
(++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
(++) Configure the IWDG counter value using IWDG_SetReload() function.
This value will be loaded in the IWDG counter each time the counter
is reloaded, then the IWDG will start counting down from this value.
(++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
(++) reload the IWDG counter at regular intervals during normal operation
to prevent an MCU reset, using IWDG_ReloadCounter() function.
(++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
in software mode (no need to enable the LSI, it will be enabled
by hardware).
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_iwdg.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup IWDG
* @brief IWDG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ---------------------- IWDG registers bit mask ----------------------------*/
/* KR register bit mask */
#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup IWDG_Private_Functions
* @{
*/
/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
* @brief Prescaler and Counter configuration functions
*
@verbatim
===============================================================================
##### Prescaler and Counter configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
* This parameter can be one of the following values:
* @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
* @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
* @retval None
*/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
{
/* Check the parameters */
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
IWDG->KR = IWDG_WriteAccess;
}
/**
* @brief Sets IWDG Prescaler value.
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
* This parameter can be one of the following values:
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
* @retval None
*/
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
{
/* Check the parameters */
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
IWDG->PR = IWDG_Prescaler;
}
/**
* @brief Sets IWDG Reload value.
* @param Reload: specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
* @retval None
*/
void IWDG_SetReload(uint16_t Reload)
{
/* Check the parameters */
assert_param(IS_IWDG_RELOAD(Reload));
IWDG->RLR = Reload;
}
/**
* @brief Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param None
* @retval None
*/
void IWDG_ReloadCounter(void)
{
IWDG->KR = KR_KEY_RELOAD;
}
/**
* @brief Sets the IWDG window value.
* @param WindowValue: specifies the window value to be compared to the downcounter.
* @retval None
*/
void IWDG_SetWindowValue(uint16_t WindowValue)
{
/* Check the parameters */
assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
IWDG->WINR = WindowValue;
}
/**
* @}
*/
/** @defgroup IWDG_Group2 IWDG activation function
* @brief IWDG activation function
*
@verbatim
===============================================================================
##### IWDG activation function #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param None
* @retval None
*/
void IWDG_Enable(void)
{
IWDG->KR = KR_KEY_ENABLE;
}
/**
* @}
*/
/** @defgroup IWDG_Group3 Flag management function
* @brief Flag management function
*
@verbatim
===============================================================================
##### Flag management function #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the specified IWDG flag is set or not.
* @param IWDG_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg IWDG_FLAG_PVU: Prescaler Value Update on going
* @arg IWDG_FLAG_RVU: Reload Value Update on going
* @arg IWDG_FLAG_WVU: Counter Window Value Update on going
* @retval The new state of IWDG_FLAG (SET or RESET).
*/
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

230
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c
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@ -1,230 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_misc.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
*
@verbatim
===============================================================================
##### How to configure Interrupts using driver #####
===============================================================================
[..] This section provide functions allowing to configure the NVIC interrupts
(IRQ). The Cortex-M4 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
function according to the following table.
The table below gives the allowed values of the pre-emption priority
and subpriority according to the Priority Grouping configuration
performed by NVIC_PriorityGroupConfig function.
(#) Enable and Configure the priority of the selected IRQ Channels.
[..]
(@) When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
the IRQ priority will be managed only by subpriority.
The sub-priority is only used to sort pending exception priorities,
and does not affect active exceptions.
(@) Lower priority values gives higher priority.
(@) Priority Order:
(#@) Lowest Preemption priority.
(#@) Lowest Subpriority.
(#@) Lowest hardware priority (IRQn position).
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_misc.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup MISC_Private_Functions
* @{
*/
/**
* @brief Configures the priority grouping: pre-emption priority and subpriority.
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority.
* 4 bits for subpriority.
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority.
* 3 bits for subpriority.
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority.
* 2 bits for subpriority.
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority.
* 1 bits for subpriority.
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority.
* 0 bits for subpriority.
* @note When NVIC_PriorityGroup_0 is selected, it will no be any nested
* interrupt. This interrupts priority is managed only with subpriority.
* @retval None
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
}
/**
* @brief Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
* the configuration information for the specified NVIC peripheral.
* @retval None
*/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority --------------------------------*/
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
tmppre = (0x4 - tmppriority);
tmpsub = tmpsub >> tmppriority;
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
tmppriority = tmppriority << 0x04;
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
/* Enable the Selected IRQ Channels --------------------------------------*/
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
else
{
/* Disable the Selected IRQ Channels -------------------------------------*/
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
}
/**
* @brief Sets the vector table location and Offset.
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
* This parameter can be one of the following values:
* @arg NVIC_VectTab_RAM
* @arg NVIC_VectTab_FLASH
* @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
* @retval None
*/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
{
/* Check the parameters */
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
assert_param(IS_NVIC_OFFSET(Offset));
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief Selects the condition for the system to enter low power mode.
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
* This parameter can be one of the following values:
* @arg NVIC_LP_SEVONPEND
* @arg NVIC_LP_SLEEPDEEP
* @arg NVIC_LP_SLEEPONEXIT
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_NVIC_LP(LowPowerMode));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SCB->SCR |= LowPowerMode;
}
else
{
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
}
}
/**
* @brief Configures the SysTick clock source.
* @param SysTick_CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

575
lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c
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@ -1,575 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_opamp.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the operational amplifiers (OPAMP1,...OPAMP4) peripheral:
* + OPAMP Configuration
* + OPAMP calibration
*
@verbatim
==============================================================================
##### OPAMP Peripheral Features #####
==============================================================================
[..]
The device integrates 4 operational amplifiers OPAMP1, OPAMP2, OPAMP3 and OPAMP4:
(+) The OPAMPs non inverting input can be selected among the list shown by
table below.
(+) The OPAMPs inverting input can be selected among the list shown by
table below.
(+) The OPAMPs outputs can be internally connected to the inverting input
(follower mode)
(+) The OPAMPs outputs can be internally connected to resistor feedback
output (Programmable Gain Amplifier mode)
(+) The OPAMPs outputs can be internally connected to ADC
(+) The OPAMPs can be calibrated to compensate the offset compensation
(+) Timer-controlled Mux for automatic switch of inverting and
non-inverting input
OPAMPs inverting/non-inverting inputs:
+--------------------------------------------------------------+
| | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
|-----------------|--------|--------|--------|--------|--------|
| | PGA | OK | OK | OK | OK |
| Inverting Input | Vout | OK | OK | OK | OK |
| | IO1 | PC5 | PC5 | PB10 | PB10 |
| | IO2 | PA3 | PA5 | PB2 | PD8 |
|-----------------|--------|--------|--------|--------|--------|
| | IO1 | PA7 | PD14 | PB13 | PD11 |
| Non Inverting | IO2 | PA5 | PB14 | PA5 | PB11 |
| Input | IO3 | PA3 | PB0 | PA1 | PA4 |
| | IO4 | PA1 | PA7 | PB0 | PB13 |
+--------------------------------------------------------------+
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions to configure and program the OPAMP
of all STM32F30x devices.
To use the OPAMP, perform the following steps:
(#) Enable the SYSCFG APB clock to get write access to OPAMP
register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
(#) Configure the OPAMP input in analog mode using GPIO_Init()
(#) Configure the OPAMP using OPAMP_Init() function:
(++) Select the inverting input
(++) Select the non-inverting inverting input
(#) Enable the OPAMP using OPAMP_Cmd() function
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_opamp.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup OPAMP
* @brief OPAMP driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define OPAMP_CSR_DEFAULT_MASK ((uint32_t)0xFFFFFF93)
#define OPAMP_CSR_TIMERMUX_MASK ((uint32_t)0xFFFFF8FF)
#define OPAMP_CSR_TRIMMING_MASK ((uint32_t)0x0000001F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup OPAMP_Private_Functions
* @{
*/
/** @defgroup OPAMP_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes OPAMP peripheral registers to their default reset values.
* @note Deinitialization can't be performed if the OPAMP configuration is locked.
* To unlock the configuration, perform a system reset.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
* to select the OPAMP peripheral.
* @param None
* @retval None
*/
void OPAMP_DeInit(uint32_t OPAMP_Selection)
{
/*!< Set OPAMP_CSR register to reset value */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = ((uint32_t)0x00000000);
}
/**
* @brief Initializes the OPAMP peripheral according to the specified parameters
* in OPAMP_InitStruct
* @note If the selected OPAMP is locked, initialization can't be performed.
* To unlock the configuration, perform a system reset.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
* to select the OPAMP peripheral.
* @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains
* the configuration information for the specified OPAMP peripheral.
* - OPAMP_InvertingInput specifies the inverting input of OPAMP
* - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP
* @retval None
*/
void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_OPAMP_INVERTING_INPUT(OPAMP_InitStruct->OPAMP_InvertingInput));
assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput));
/*!< Get the OPAMPx_CSR register value */
tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
/*!< Clear the inverting and non inverting bits selection bits */
tmpreg &= (uint32_t) (OPAMP_CSR_DEFAULT_MASK);
/*!< Configure OPAMP: inverting and non inverting inputs */
tmpreg |= (uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput | OPAMP_InitStruct->OPAMP_NonInvertingInput);
/*!< Write to OPAMPx_CSR register */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
}
/**
* @brief Fills each OPAMP_InitStruct member with its default value.
* @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct)
{
OPAMP_InitStruct->OPAMP_NonInvertingInput = OPAMP_NonInvertingInput_IO1;
OPAMP_InitStruct->OPAMP_InvertingInput = OPAMP_InvertingInput_IO1;
}
/**
* @brief Configure the feedback resistor gain.
* @note If the selected OPAMP is locked, gain configuration can't be performed.
* To unlock the configuration, perform a system reset.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
* to select the OPAMP peripheral.
* @param NewState: new state of the OPAMP peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect)
{
/* Check the parameters */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_OPAMP_PGAGAIN(OPAMP_PGAGain));
assert_param(IS_OPAMP_PGACONNECT(OPAMP_PGAConnect));
/* Reset the configuration bits */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_PGGAIN);
/* Set the new configuration */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_PGAGain | OPAMP_PGAConnect);
}
/**
* @brief Configure the OPAMP's internal reference.
* @note This feature is used when calibration enabled or OPAMP's reference
* connected to the non inverting input.
* @note If the selected OPAMP is locked, Vref configuration can't be performed.
* To unlock the configuration, perform a system reset.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
* to select the OPAMP peripheral.
* @param OPAMP_Vref: This parameter can be:
* OPAMP_Vref_3VDDA: OPMAP Vref = 3.3% VDDA
* OPAMP_Vref_10VDDA: OPMAP Vref = 10% VDDA
* OPAMP_Vref_50VDDA: OPMAP Vref = 50% VDDA
* OPAMP_Vref_90VDDA: OPMAP Vref = 90% VDDA
* @retval None
*/
void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_OPAMP_VREF(OPAMP_Vref));
/*!< Get the OPAMPx_CSR register value */
tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
/*!< Clear the CALSEL bits */
tmpreg &= (uint32_t) (~OPAMP_CSR_CALSEL);
/*!< Configure OPAMP reference */
tmpreg |= (uint32_t)(OPAMP_Vref);
/*!< Write to OPAMPx_CSR register */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
}
/**
* @brief Connnect the internal reference to the OPAMP's non inverting input.
* @note If the selected OPAMP is locked, Vref configuration can't be performed.
* To unlock the configuration, perform a system reset.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
* to select the OPAMP peripheral.
* @param NewState: new state of the OPAMP peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Connnect the internal reference to the OPAMP's non inverting input */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_FORCEVP);
}
else
{
/* Disconnnect the internal reference to the OPAMP's non inverting input */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_FORCEVP);
}
}
/**
* @brief Enables or disables connecting the OPAMP's internal reference to ADC.
* @note If the selected OPAMP is locked, Vref connection can't be performed.
* To unlock the configuration, perform a system reset.
* @param NewState: new state of the Vrefint output.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable output internal reference */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TSTREF);
}
else
{
/* Disable output internal reference */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TSTREF);
}
}
/**
* @brief Configure the OPAMP peripheral (secondary inputs) for timer-controlled
* mux mode according to the specified parameters in OPAMP_InitStruct.
* @note If the selected OPAMP is locked, timer-controlled mux configuration
* can't be performed.
* To unlock the configuration, perform a system reset.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
* to select the OPAMP peripheral.
* @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains
* the configuration information for the specified OPAMP peripheral.
* - OPAMP_InvertingInput specifies the inverting input of OPAMP
* - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP
* @note PGA and Vout can't be selected as seconadry inverting input.
* @retval None
*/
void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_OPAMP_SECONDARY_INVINPUT(OPAMP_InitStruct->OPAMP_InvertingInput));
assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput));
/*!< Get the OPAMPx_CSR register value */
tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
/*!< Clear the secondary inverting bit, secondary non inverting bit and TCMEN bits */
tmpreg &= (uint32_t) (OPAMP_CSR_TIMERMUX_MASK);
/*!< Configure OPAMP: secondary inverting and non inverting inputs */
tmpreg |= (uint32_t)((uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput<<3) | (uint32_t)(OPAMP_InitStruct->OPAMP_NonInvertingInput<<7));
/*!< Write to OPAMPx_CSR register */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
}
/**
* @brief Enable or disable the timer-controlled mux mode.
* @note If the selected OPAMP is locked, enable/disable can't be performed.
* To unlock the configuration, perform a system reset.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
* to select the OPAMP peripheral.
* @param NewState: new state of the OPAMP peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the timer-controlled Mux mode */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TCMEN);
}
else
{
/* Disable the timer-controlled Mux mode */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TCMEN);
}
}
/**
* @brief Enable or disable the OPAMP peripheral.
* @note If the selected OPAMP is locked, enable/disable can't be performed.
* To unlock the configuration, perform a system reset.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
* to select the OPAMP peripheral.
* @param NewState: new state of the OPAMP peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected OPAMPx peripheral */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_OPAMPxEN);
}
else
{
/* Disable the selected OPAMPx peripheral */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_OPAMPxEN);
}
}
/**
* @brief Return the output level (high or low) during calibration of the selected OPAMP.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
* to select the OPAMP peripheral.
* - OPAMP output is low when the non-inverting input is at a lower
* voltage than the inverting input
* - OPAMP output is high when the non-inverting input is at a higher
* voltage than the inverting input
* @note OPAMP ouput level is provided only during calibration phase.
* @retval Returns the selected OPAMP output level: low or high.
*
*/
uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection)
{
uint32_t opampout = 0x0;
/* Check the parameters */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
/* Check if selected OPAMP output is high */
if ((*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) & (OPAMP_CSR_OUTCAL)) != 0)
{
opampout = OPAMP_OutputLevel_High;
}
else
{
opampout = OPAMP_OutputLevel_Low;
}
/* Return the OPAMP output level */
return (uint32_t)(opampout);
}
/**
* @brief Select the trimming mode.
* @param OffsetTrimming: the selected offset trimming mode.
* This parameter can be one of the following values:
* @arg OPAMP_Trimming_Factory: factory trimming values are used for offset
* calibration
* @arg OPAMP_Trimming_User: user trimming values are used for offset
* calibration
* @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig()
* function or OPAMP_OffsetTrimLowPowerConfig() function to adjust
* trimming value.
* @retval None
*/
void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming)
{
/* Check the parameters */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming));
/* Reset USERTRIM bit */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (~(uint32_t) (OPAMP_CSR_USERTRIM));
/* Select trimming mode */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= OPAMP_Trimming;
}
/**
* @brief Configure the trimming value of the OPAMP.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
* to select the OPAMP peripheral.
* @param OPAMP_Input: the selected OPAMP input.
* This parameter can be one of the following values:
* @arg OPAMP_Input_Inverting: Inverting input is selected to configure the trimming value
* @arg OPAMP_Input_NonInverting: Non inverting input is selected to configure the trimming value
* @param OPAMP_TrimValue: the trimming value. This parameter can be any value lower
* or equal to 0x0000001F.
* @retval None
*/
void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_OPAMP_INPUT(OPAMP_Input));
assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
/*!< Get the OPAMPx_CSR register value */
tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
/*!< Clear the trimming bits */
tmpreg &= ((uint32_t)~(OPAMP_CSR_TRIMMING_MASK<<OPAMP_Input));
/*!< Configure the new trimming value */
tmpreg |= (uint32_t)(OPAMP_TrimValue<<OPAMP_Input);
/*!< Write to OPAMPx_CSR register */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
}
/**
* @brief Start or stop the calibration of selected OPAMP peripheral.
* @note If the selected OPAMP is locked, start/stop can't be performed.
* To unlock the configuration, perform a system reset.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
* to select the OPAMP peripheral.
* @param NewState: new state of the OPAMP peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Start the OPAMPx calibration */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_CALON);
}
else
{
/* Stop the OPAMPx calibration */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_CALON);
}
}
/**
* @}
*/
/** @defgroup OPAMP_Group2 OPAMP configuration locking function
* @brief OPAMP1,...OPAMP4 configuration locking function
* OPAMP1,...OPAMP4 configuration can be locked each separately.
* Unlocking is performed by system reset.
*
@verbatim
===============================================================================
##### Configuration Lock function #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Lock the selected OPAMP configuration.
* @note Locking the configuration means that all control bits are read-only.
* To unlock the OPAMP configuration, perform a system reset.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
* to select the OPAMP peripheral.
* @retval None
*/
void OPAMP_LockConfig(uint32_t OPAMP_Selection)
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
/* Set the lock bit corresponding to selected OPAMP */
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_LOCK);
}
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_pwr.c
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@ -1,538 +0,0 @@
/**
******************************************************************************
* @file stm32f30x_pwr.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Backup Domain Access
* + PVD configuration
* + WakeUp pins configuration
* + Low Power modes configuration
* + Flags management
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_pwr.h"
#include "stm32f30x_rcc.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup PWR
* @brief PWR driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* --------- PWR registers bit address in the alias region ---------- */
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of DBP bit */
#define CR_OFFSET (PWR_OFFSET + 0x00)
#define DBP_BitNumber 0x08
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
/* Alias word address of PVDE bit */
#define PVDE_BitNumber 0x04
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
/* ------------------ PWR registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PWR_Private_Functions
* @{
*/
/** @defgroup PWR_Group1 Backup Domain Access function
* @brief Backup Domain Access function
*
@verbatim
==============================================================================
##### Backup Domain Access function #####
==============================================================================
[..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers
and RTC backup registers) are protected against possible stray write accesses.
[..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function.
@endverbatim
* @{
*/
/**
* @brief Deinitializes the PWR peripheral registers to their default reset values.
* @param None
* @retval None
*/
void PWR_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
}
/**
* @brief Enables or disables access to the RTC and backup registers.
* @note If the HSE divided by 32 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @param NewState: new state of the access to the RTC and backup registers.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_BackupAccessCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
}
/**
* @}
*/
/** @defgroup PWR_Group2 PVD configuration functions
* @brief PVD configuration functions
*
@verbatim
===============================================================================
##### PVD configuration functions #####
==============================================================================
[..]
(+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
PVD threshold. This event is internally connected to the EXTI line16
and can generate an interrupt if enabled through the EXTI registers.
(+) The PVD is stopped in Standby mode.
@endverbatim
* @{
*/
/**
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
* @param PWR_PVDLevel: specifies the PVD detection level
* This parameter can be one of the following values:
* @arg PWR_PVDLevel_0: PVD detection level set to 2.18V
* @arg PWR_PVDLevel_1: PVD detection level set to 2.28V
* @arg PWR_PVDLevel_2: PVD detection level set to 2.38V
* @arg PWR_PVDLevel_3: PVD detection level set to 2.48V
* @arg PWR_PVDLevel_4: PVD detection level set to 2.58V
* @arg PWR_PVDLevel_5: PVD detection level set to 2.68V
* @arg PWR_PVDLevel_6: PVD detection level set to 2.78V
* @arg PWR_PVDLevel_7: PVD detection level set to 2.88V
* @retval None
*/
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
tmpreg = PWR->CR;
/* Clear PLS[7:5] bits */
tmpreg &= CR_PLS_MASK;
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
tmpreg |= PWR_PVDLevel;
/* Store the new value */
PWR->CR = tmpreg;
}
/**
* @brief Enables or disables the Power Voltage Detector(PVD).
* @param NewState: new state of the PVD.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_PVDCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
}
/**
* @}
*/
/** @defgroup PWR_Group3 WakeUp pins configuration functions
* @brief WakeUp pins configuration functions
*
@verbatim
===============================================================================
##### WakeUp pins configuration functions #####
===============================================================================
[..]
(+) WakeUp pins are used to wakeup the system from Standby mode. These pins are
forced in input pull down configuration and are active on rising edges.
(+) There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and
WakeUp Pin 3 on PE.06.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the WakeUp Pin functionality.
* @param PWR_WakeUpPin: specifies the WakeUpPin.
* This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
* @param NewState: new state of the WakeUp Pin functionality.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the EWUPx pin */
PWR->CSR |= PWR_WakeUpPin;
}
else
{
/* Disable the EWUPx pin */
PWR->CSR &= ~PWR_WakeUpPin;
}
}
/**
* @}
*/
/** @defgroup PWR_Group4 Low Power modes configuration functions
* @brief Low Power modes configuration functions
*
@verbatim
===============================================================================
##### Low Power modes configuration functions #####
==============================================================================
[..] The devices feature three low-power modes:
(+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
(+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode
(+) Standby mode: VCORE domain powered off
*** Sleep mode ***
==================
[..]
(+) Entry:
(++) The Sleep mode is entered by executing the WFE() or WFI() instructions.
(+) Exit:
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
controller (NVIC) can wake up the device from Sleep mode.
*** Stop mode ***
=================
[..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI,
and the HSE RC oscillators are disabled. Internal SRAM and register
contents are preserved.
The voltage regulator can be configured either in normal or low-power mode.
(+) Entry:
(++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
function with regulator in LowPower or with Regulator ON.
(+) Exit:
(++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode
or any internal IPs (I2C or UASRT) wakeup event.
*** Standby mode ***
====================
[..] The Standby mode allows to achieve the lowest power consumption. It is based
on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
The VCORE domain is consequently powered off. The PLL, the HSI, and the HSE
oscillator are also switched off. SRAM and register
contents are lost except for the Backup domain (RTC registers, RTC backup
registers and Standby circuitry).
[..] The voltage regulator is OFF.
(+) Entry:
(++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
(+) Exit:
(++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
*** Auto-wakeup (AWU) from low-power mode ***
=============================================
[..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper
event, a time-stamp event, or a comparator event, without depending on an
external interrupt (Auto-wakeup mode).
(+) RTC auto-wakeup (AWU) from the Stop mode
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
(+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
or Event modes) using the EXTI_Init() function.
(+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
(+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
and RTC_AlarmCmd() functions.
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
is necessary to:
(+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
or Event modes) using the EXTI_Init() function.
(+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
function.
(+++) Configure the RTC to detect the tamper or time stamp event using the
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
functions.
(+) RTC auto-wakeup (AWU) from the Standby mode
(++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
(+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
(+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
and RTC_AlarmCmd() functions.
(++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
is necessary to:
(+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
function.
(+++) Configure the RTC to detect the tamper or time stamp event using the
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
functions.
(+) Comparator auto-wakeup (AWU) from the Stop mode
(++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
(+++) Configure the correspondant comparator EXTI Line to be sensitive to
the selected edges (falling, rising or falling and rising)
(Interrupt or Event modes) using the EXTI_Init() function.
(+++) Configure the comparator to generate the event.
@endverbatim
* @{
*/
/**
* @brief Enters Sleep mode.
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
* @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
* @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
* @retval None
*/
void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
/* Clear SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
/* Select SLEEP mode entry -------------------------------------------------*/
if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
}
/**
* @brief Enters STOP mode.
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
* the HSI RC oscillator is selected as system clock.
* @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced.
* @param PWR_Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PWR_Regulator_ON: STOP mode with regulator ON
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
* @retval None
*/
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDSR bits */
tmpreg &= CR_DS_MASK;
/* Set LPDSR bit according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
}
/**
* @brief Enters STANDBY mode.
* @note In Standby mode, all I/O pins are high impedance except for:
* @note Reset pad (still available)
* @note RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
* time-stamp, RTC Alarm out, or RTC clock calibration out.
* @note WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled.
* @param None
* @retval None
*/
void PWR_EnterSTANDBYMode(void)
{
/* Clear Wakeup flag */
PWR->CR |= PWR_CR_CWUF;
/* Select STANDBY mode */
PWR->CR |= PWR_CR_PDDS;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM )
__force_stores();
#endif
/* Request Wait For Interrupt */
__WFI();
}
/**
* @}
*/
/** @defgroup PWR_Group5 Flags management functions
* @brief Flags management functions
*
@verbatim
===============================================================================
##### Flags management functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the specified PWR flag is set or not.
* @param PWR_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
* was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B),
* RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
* resumed from StandBy mode.
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
* by the PWR_PVDCmd() function.
* @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This
* flag indicates the state of the internal voltage reference, VREFINT.
* @retval The new state of PWR_FLAG (SET or RESET).
*/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/**
* @brief Clears the PWR's pending flags.
* @param PWR_FLAG: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag
* @retval None
*/
void PWR_ClearFlag(uint32_t PWR_FLAG)
{
/* Check the parameters */
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
PWR->CR |= PWR_FLAG << 2;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c
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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c
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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c
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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c
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/**
******************************************************************************
* @file stm32f30x_syscfg.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the SYSCFG peripheral:
* + Remapping the memory mapped at 0x00000000
* + Remapping the DMA channels
* + Enabling I2C fast mode plus driving capability for I2C plus
* + Remapping USB interrupt line
* + Configuring the EXTI lines connection to the GPIO port
* + Configuring the CLASSB requirements
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..] The SYSCFG registers can be accessed only when the SYSCFG
interface APB clock is enabled.
[..] To enable SYSCFG APB clock use:
RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE);
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_syscfg.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup SYSCFG
* @brief SYSCFG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Reset value od SYSCFG_CFGR1 register */
#define CFGR1_CLEAR_MASK ((uint32_t)0x7C000000)
/* ------------ SYSCFG registers bit address in the alias region -------------*/
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
/* --- CFGR1 Register ---*/
/* Alias word address of USB_IT_RMP bit */
#define CFGR1_OFFSET (SYSCFG_OFFSET + 0x00)
#define USBITRMP_BitNumber 0x05
#define CFGR1_USBITRMP_BB (PERIPH_BB_BASE + (CFGR1_OFFSET * 32) + (USBITRMP_BitNumber * 4))
/* --- CFGR2 Register ---*/
/* Alias word address of BYP_ADDR_PAR bit */
#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
#define BYPADDRPAR_BitNumber 0x04
#define CFGR1_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SYSCFG_Private_Functions
* @{
*/
/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
* @brief SYSCFG Initialization and Configuration functions
*
@verbatim
===============================================================================
##### SYSCFG Initialization and Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the SYSCFG registers to their default reset values.
* @param None
* @retval None
* @note MEM_MODE bits are not affected by APB reset.
* MEM_MODE bits took the value from the user option bytes.
*/
void SYSCFG_DeInit(void)
{
/* Reset SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
/* Set FPU Interrupt Enable bits to default value */
SYSCFG->CFGR1 |= 0x7C000000;
/* Reset RAM Write protection bits to default value */
SYSCFG->RCR = 0x00000000;
/* Set EXTICRx registers to reset value */
SYSCFG->EXTICR[0] = 0;
SYSCFG->EXTICR[1] = 0;
SYSCFG->EXTICR[2] = 0;
SYSCFG->EXTICR[3] = 0;
/* Set CFGR2 register to reset value */
SYSCFG->CFGR2 = 0;
/* Set CFGR3 register to reset value */
SYSCFG->CFGR3 = 0;
}
/**
* @brief Configures the memory mapping at address 0x00000000.
* @param SYSCFG_MemoryRemap: selects the memory remapping.
* This parameter can be one of the following values:
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
* @retval None
*/
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
{
uint32_t tmpcfgr1 = 0;
/* Check the parameter */
assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
/* Get CFGR1 register value */
tmpcfgr1 = SYSCFG->CFGR1;
/* Clear MEM_MODE bits */
tmpcfgr1 &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
/* Set the new MEM_MODE bits value */
tmpcfgr1 |= (uint32_t) SYSCFG_MemoryRemap;
/* Set CFGR1 register with the new memory remap configuration */
SYSCFG->CFGR1 = tmpcfgr1;
}
/**
* @brief Configures the DMA channels remapping.
* @param SYSCFG_DMARemap: selects the DMA channels remap.
* This parameter can be one of the following values:
* @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from DMA1 channel1 to channel2
* @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from DMA1 channel3 to channel4
* @arg SYSCFG_DMARemap_TIM6DAC1Ch1: Remap TIM6/DAC1 DMA requests from DMA2 channel 3 to DMA1 channel 3
* @arg SYSCFG_DMARemap_TIM7DAC1Ch2: Remap TIM7/DAC2 DMA requests from DMA2 channel 4 to DMA1 channel 4
* @arg SYSCFG_DMARemap_ADC2ADC4: Remap ADC2 and ADC4 DMA requests from DMA2 channel1/channel3 to channel3/channel4
* @arg SYSCFG_DMARemap_DAC2Ch1: Remap DAC2 DMA requests to DMA1 channel5
* @arg SYSCFG_DMARemapCh2_SPI1_RX: Remap SPI1 RX DMA1 CH2 requests
* @arg SYSCFG_DMARemapCh4_SPI1_RX: Remap SPI1 RX DMA CH4 requests
* @arg SYSCFG_DMARemapCh6_SPI1_RX: Remap SPI1 RX DMA CH6 requests
* @arg SYSCFG_DMARemapCh3_SPI1_TX: Remap SPI1 TX DMA CH2 requests
* @arg SYSCFG_DMARemapCh5_SPI1_TX: Remap SPI1 TX DMA CH5 requests
* @arg SYSCFG_DMARemapCh7_SPI1_TX: Remap SPI1 TX DMA CH7 requests
* @arg SYSCFG_DMARemapCh7_I2C1_RX: Remap I2C1 RX DMA CH7 requests
* @arg SYSCFG_DMARemapCh3_I2C1_RX: Remap I2C1 RX DMA CH3 requests
* @arg SYSCFG_DMARemapCh5_I2C1_RX: Remap I2C1 RX DMA CH5 requests
* @arg SYSCFG_DMARemapCh6_I2C1_TX: Remap I2C1 TX DMA CH6 requests
* @arg SYSCFG_DMARemapCh2_I2C1_TX: Remap I2C1 TX DMA CH2 requests
* @arg SYSCFG_DMARemapCh4_I2C1_TX: Remap I2C1 TX DMA CH4 requests
* @arg SYSCFG_DMARemapCh4_ADC2: Remap ADC2 DMA1 Ch4 requests
* @arg SYSCFG_DMARemapCh2_ADC2: Remap ADC2 DMA1 Ch2 requests
* @param NewState: new state of the DMA channel remapping.
* This parameter can be: Enable or Disable.
* @note When enabled, DMA channel of the selected peripheral is remapped
* @note When disabled, Default DMA channel is mapped to the selected peripheral
* @note
* By default TIM17 DMA requests is mapped to channel 1
* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable)
* to remap TIM17 DMA requests to DMA1 channel 2
* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable)
* to map TIM17 DMA requests to DMA1 channel 1 (default mapping)
* @retval None
*/
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if ((SYSCFG_DMARemap & 0x80000000)!= 0x80000000)
{
if (NewState != DISABLE)
{
/* Remap the DMA channel */
SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
}
else
{
/* use the default DMA channel mapping */
SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
}
}
else
{
if (NewState != DISABLE)
{
/* Remap the DMA channel */
SYSCFG->CFGR3 |= (uint32_t)SYSCFG_DMARemap;
}
else
{
/* use the default DMA channel mapping */
SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_DMARemap);
}
}
}
/**
* @brief Configures the remapping capabilities of DAC/TIM triggers.
* @param SYSCFG_TriggerRemap: selects the trigger to be remapped.
* This parameter can be one of the following values:
* @arg SYSCFG_TriggerRemap_DACTIM3: Remap DAC trigger from TIM8 to TIM3
* @arg SYSCFG_TriggerRemap_TIM1TIM17: Remap TIM1 ITR3 from TIM4 TRGO to TIM17 OC
* @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG1: Remap DAC trigger to HRTIM1 TRIG1
* @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG2: Remap DAC trigger to HRTIM1 TRIG2
* @param NewState: new state of the trigger mapping.
* This parameter can be: ENABLE or DISABLE.
* @note ENABLE: Enable fast mode plus driving capability for selected pin
* @note DISABLE: Disable fast mode plus driving capability for selected pin
* @retval None
*/
void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SYSCFG_TRIGGER_REMAP(SYSCFG_TriggerRemap));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if ((SYSCFG_TriggerRemap & 0x80000000)!= 0x80000000)
{
if (NewState != DISABLE)
{
/* Remap the trigger */
SYSCFG->CFGR1 |= (uint32_t)SYSCFG_TriggerRemap;
}
else
{
/* Use the default trigger mapping */
SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_TriggerRemap);
}
}
else
{
if (NewState != DISABLE)
{
/* Remap the trigger */
SYSCFG->CFGR3 |= (uint32_t)SYSCFG_TriggerRemap;
}
else
{
/* Use the default trigger mapping */
SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_TriggerRemap);
}
}
}
/**
* @brief Configures the remapping capabilities of encoder mode.
* @ note This feature implement the so-called M/T method for measuring speed
* and position using quadrature encoders.
* @param SYSCFG_EncoderRemap: selects the remap option for encoder mode.
* This parameter can be one of the following values:
* @arg SYSCFG_EncoderRemap_No: No remap
* @arg SYSCFG_EncoderRemap_TIM2: Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2
* @arg SYSCFG_EncoderRemap_TIM3: Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2
* @arg SYSCFG_EncoderRemap_TIM4: Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2
* @retval None
*/
void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap)
{
/* Check the parameter */
assert_param(IS_SYSCFG_ENCODER_REMAP(SYSCFG_EncoderRemap));
/* Reset the encoder mode remapping bits */
SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_CFGR1_ENCODER_MODE);
/* Set the selected configuration */
SYSCFG->CFGR1 |= (uint32_t)(SYSCFG_EncoderRemap);
}
/**
* @brief Remaps the USB interrupt lines.
* @param NewState: new state of the mapping of USB interrupt lines.
* This parameter can be:
* @param ENABLE: Remap the USB interrupt line as following:
* @arg USB Device High Priority (USB_HP) interrupt mapped to line 74.
* @arg USB Device Low Priority (USB_LP) interrupt mapped to line 75.
* @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 76.
* @param DISABLE: Use the default USB interrupt line:
* @arg USB Device High Priority (USB_HP) interrupt mapped to line 19.
* @arg USB Device Low Priority (USB_LP) interrupt mapped to line 20.
* @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 42.
* @retval None
*/
void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState)
{
/* Check the parameter */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Remap the USB interupt lines */
*(__IO uint32_t *) CFGR1_USBITRMP_BB = (uint32_t)NewState;
}
/**
* @brief Configures the I2C fast mode plus driving capability.
* @param SYSCFG_I2CFastModePlus: selects the pin.
* This parameter can be one of the following values:
* @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
* @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
* @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
* @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
* @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for I2C1 pins
* @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins
* @param NewState: new state of the DMA channel remapping.
* This parameter can be:
* @arg ENABLE: Enable fast mode plus driving capability for selected I2C pin
* @arg DISABLE: Disable fast mode plus driving capability for selected I2C pin
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
* I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaing I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be enabled
* only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
* @retval None
*/
void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable fast mode plus driving capability for selected I2C pin */
SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
}
else
{
/* Disable fast mode plus driving capability for selected I2C pin */
SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
}
}
/**
* @brief Enables or disables the selected SYSCFG interrupts.
* @param SYSCFG_IT: specifies the SYSCFG interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg SYSCFG_IT_IXC: Inexact Interrupt
* @arg SYSCFG_IT_IDC: Input denormal Interrupt
* @arg SYSCFG_IT_OFC: Overflow Interrupt
* @arg SYSCFG_IT_UFC: Underflow Interrupt
* @arg SYSCFG_IT_DZC: Divide-by-zero Interrupt
* @arg SYSCFG_IT_IOC: Invalid operation Interrupt
* @param NewState: new state of the specified SYSCFG interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_SYSCFG_IT(SYSCFG_IT));
if (NewState != DISABLE)
{
/* Enable the selected SYSCFG interrupts */
SYSCFG->CFGR1 |= SYSCFG_IT;
}
else
{
/* Disable the selected SYSCFG interrupts */
SYSCFG->CFGR1 &= ((uint32_t)~SYSCFG_IT);
}
}
/**
* @brief Selects the GPIO pin used as EXTI Line.
* @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source
* for EXTI lines where x can be (A, B, C, D, E or F).
* @param EXTI_PinSourcex: specifies the EXTI line to be configured.
* This parameter can be EXTI_PinSourcex where x can be (0..15)
* @retval None
*/
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
{
uint32_t tmp = 0x00;
/* Check the parameters */
assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
}
/**
* @brief Connects the selected parameter to the break input of TIM1.
* @note The selected configuration is locked and can be unlocked by system reset
* @param SYSCFG_Break: selects the configuration to be connected to break
* input of TIM1
* This parameter can be any combination of the following values:
* @arg SYSCFG_Break_PVD: PVD interrupt is connected to the break input of TIM1.
* @arg SYSCFG_Break_SRAMParity: SRAM Parity error is connected to the break input of TIM1.
* @arg SYSCFG_Break_HardFault: Lockup output of CortexM4 is connected to the break input of TIM1.
* @retval None
*/
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
{
/* Check the parameter */
assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
}
/**
* @brief Disables the parity check on RAM.
* @note Disabling the parity check on RAM locks the configuration bit.
* To re-enable the parity check on RAM perform a system reset.
* @param None
* @retval None
*/
void SYSCFG_BypassParityCheckDisable(void)
{
/* Disable the adddress parity check on RAM */
*(__IO uint32_t *) CFGR1_BYPADDRPAR_BB = (uint32_t)0x00000001;
}
/**
* @brief Enables the ICODE SRAM write protection.
* @note Enabling the ICODE SRAM write protection locks the configuration bit.
* To disable the ICODE SRAM write protection perform a system reset.
* @param None
* @retval None
*/
void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP)
{
/* Check the parameter */
assert_param(IS_SYSCFG_PAGE(SYSCFG_SRAMWRP));
/* Enable the write-protection on the selected ICODE SRAM page */
SYSCFG->RCR |= (uint32_t)SYSCFG_SRAMWRP;
}
/**
* @brief Checks whether the specified SYSCFG flag is set or not.
* @param SYSCFG_Flag: specifies the SYSCFG flag to check.
* This parameter can be one of the following values:
* @arg SYSCFG_FLAG_PE: SRAM parity error flag.
* @retval The new state of SYSCFG_Flag (SET or RESET).
*/
FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
{
(void)SYSCFG_Flag;
FlagStatus bitstatus = RESET;
/* Check the parameter */
assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
/* Check the status of the specified SPI flag */
if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
{
/* SYSCFG_Flag is set */
bitstatus = SET;
}
else
{
/* SYSCFG_Flag is reset */
bitstatus = RESET;
}
/* Return the SYSCFG_Flag status */
return bitstatus;
}
/**
* @brief Clears the selected SYSCFG flag.
* @param SYSCFG_Flag: selects the flag to be cleared.
* This parameter can be any combination of the following values:
* @arg SYSCFG_FLAG_PE: SRAM parity error flag.
* @retval None
*/
void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
{
/* Check the parameter */
assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c
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/**
******************************************************************************
* @file stm32f30x_wwdg.c
* @author MCD Application Team
* @version V1.1.1
* @date 04-April-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Window watchdog (WWDG) peripheral:
* + Prescaler, Refresh window and Counter configuration
* + WWDG activation
* + Interrupts and flags management
*
* @verbatim
*
==============================================================================
##### WWDG features #####
==============================================================================
[..] Once enabled the WWDG generates a system reset on expiry of a programmed
time period, unless the program refreshes the counter (downcounter)
before to reach 0x3F value (i.e. a reset is generated when the counter
value rolls over from 0x40 to 0x3F).
[..] An MCU reset is also generated if the counter value is refreshed
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
[..] Once enabled the WWDG cannot be disabled except by a system reset.
[..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
reset occurs.
[..] The WWDG counter input clock is derived from the APB clock divided
by a programmable prescaler.
[..] WWDG counter clock = PCLK1 / Prescaler.
[..] WWDG timeout = (WWDG counter clock) * (counter value).
[..] Min-max timeout value @36MHz (PCLK1): ~114us / ~58.3ms.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
function.
(#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
(#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
(#) Set the WWDG counter value and start it using WWDG_Enable() function.
When the WWDG is enabled the counter value should be configured to
a value greater than 0x40 to prevent generating an immediate reset.
(#) Optionally you can enable the Early wakeup interrupt which is
generated when the counter reach 0x40.
Once enabled this interrupt cannot be disabled except by a system reset.
(#) Then the application program must refresh the WWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
WWDG_SetCounter() function. This operation must occur only when
the counter value is lower than the refresh window value,
programmed using WWDG_SetWindowValue().
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f30x_wwdg.h"
#include "stm32f30x_rcc.h"
/** @addtogroup STM32F30x_StdPeriph_Driver
* @{
*/
/** @defgroup WWDG
* @brief WWDG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* --------------------- WWDG registers bit mask ---------------------------- */
/* CFR register bit mask */
#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
#define CFR_W_MASK ((uint32_t)0xFFFFFF80)
#define BIT_MASK ((uint8_t)0x7F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup WWDG_Private_Functions
* @{
*/
/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
* @brief Prescaler, Refresh window and Counter configuration functions
*
@verbatim
==============================================================================
##### Prescaler, Refresh window and Counter configuration functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the WWDG peripheral registers to their default reset values.
* @param None
* @retval None
*/
void WWDG_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
}
/**
* @brief Sets the WWDG Prescaler.
* @param WWDG_Prescaler: specifies the WWDG Prescaler.
* This parameter can be one of the following values:
* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
* @retval None
*/
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
/* Clear WDGTB[1:0] bits */
tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
tmpreg |= WWDG_Prescaler;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/**
* @brief Sets the WWDG window value.
* @param WindowValue: specifies the window value to be compared to the downcounter.
* This parameter value must be lower than 0x80.
* @retval None
*/
void WWDG_SetWindowValue(uint8_t WindowValue)
{
__IO uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
/* Clear W[6:0] bits */
tmpreg = WWDG->CFR & CFR_W_MASK;
/* Set W[6:0] bits according to WindowValue value */
tmpreg |= WindowValue & (uint32_t) BIT_MASK;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/**
* @brief Enables the WWDG Early Wakeup interrupt(EWI).
* @note Once enabled this interrupt cannot be disabled except by a system reset.
* @param None
* @retval None
*/
void WWDG_EnableIT(void)
{
WWDG->CFR |= WWDG_CFR_EWI;
}
/**
* @brief Sets the WWDG counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
* an immediate reset).
* @retval None
*/
void WWDG_SetCounter(uint8_t Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
/* Write to T[6:0] bits to configure the counter value, no need to do
a read-modify-write; writing a 0 to WDGA bit does nothing */
WWDG->CR = Counter & BIT_MASK;
}
/**
* @}
*/
/** @defgroup WWDG_Group2 WWDG activation functions
* @brief WWDG activation functions
*
@verbatim
==============================================================================
##### WWDG activation function #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables WWDG and load the counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
* an immediate reset).
* @retval None
*/
void WWDG_Enable(uint8_t Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
WWDG->CR = WWDG_CR_WDGA | Counter;
}
/**
* @}
*/
/** @defgroup WWDG_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
==============================================================================
##### Interrupts and flags management functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the Early Wakeup interrupt flag is set or not.
* @param None
* @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
*/
FlagStatus WWDG_GetFlagStatus(void)
{
FlagStatus bitstatus = RESET;
if ((WWDG->SR) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears Early Wakeup interrupt flag.
* @param None
* @retval None
*/
void WWDG_ClearFlag(void)
{
WWDG->SR = (uint32_t)RESET;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32_assert_template.h
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/**
******************************************************************************
* @file stm32_assert.h
* @author MCD Application Team
* @brief STM32 assert template file.
* This file should be copied to the application folder and renamed
* to stm32_assert.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32_ASSERT_H
#define __STM32_ASSERT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(char* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32_ASSERT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h
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/**
******************************************************************************
* @file stm32f3xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_H
#define __STM32F3xx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_conf.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup HAL
* @{
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup HAL_Private_Macros
* @{
*/
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region
* @brief SYSCFG registers bit address in the alias region
* @{
*/
/* ------------ SYSCFG registers bit address in the alias region -------------*/
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
/* --- CFGR2 Register ---*/
/* Alias word address of BYP_ADDR_PAR bit */
#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U)
#define BYPADDRPAR_BitNumber 0x04U
#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))
/**
* @}
*/
#if defined(SYSCFG_CFGR1_DMA_RMP)
/** @defgroup HAL_DMA_Remapping HAL DMA Remapping
* Elements values convention: 0xXXYYYYYY
* - YYYYYY : Position in the register
* - XX : Register index
* - 00: CFGR1 register in SYSCFG
* - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
* @{
*/
#define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
#define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U) /*!< TIM16 DMA request remap
1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
#define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U) /*!< TIM17 DMA request remap
1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
#if defined(SYSCFG_CFGR3_DMA_RMP)
#if !defined(HAL_REMAP_CFGR3_MASK)
#define HAL_REMAP_CFGR3_MASK (0x01000000U)
#endif
#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
11: Map on DMA1 channel 2 */
#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
01: Map on DMA1 channel 4 */
#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
10: Map on DMA1 channel 6 */
#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
11: Map on DMA1 channel 3 */
#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
01: Map on DMA1 channel 5 */
#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
10: Map on DMA1 channel 7 */
#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
11: Map on DMA1 channel 7 */
#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
01: Map on DMA1 channel 3 */
#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
10: Map on DMA1 channel 5 */
#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
11: Map on DMA1 channel 6 */
#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
01: Map on DMA1 channel 2 */
#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
10: Map on DMA1 channel 4 */
#define HAL_REMAPDMA_ADC2_DMA1_CH2 (0x01000100U) /*!< ADC2 DMA remap
x0: No remap (ADC2 on DMA2)
10: Map on DMA1 channel 2 */
#define HAL_REMAPDMA_ADC2_DMA1_CH4 (0x01000300U) /*!< ADC2 DMA remap
11: Map on DMA1 channel 4 */
#endif /* SYSCFG_CFGR3_DMA_RMP */
#if defined(SYSCFG_CFGR3_DMA_RMP)
#define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
(((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
(((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
(((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
(((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
(((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
(((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
(((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
(((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
(((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
(((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
(((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
(((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
(((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
(((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
(((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
(((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
(((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
(((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
(((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
(((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
#else
#define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
(((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
(((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
(((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
(((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
(((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
(((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
#endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
/**
* @}
*/
#endif /* SYSCFG_CFGR1_DMA_RMP */
/** @defgroup HAL_Trigger_Remapping HAL Trigger Remapping
* Elements values convention: 0xXXYYYYYY
* - YYYYYY : Position in the register
* - XX : Register index
* - 00: CFGR1 register in SYSCFG
* - 01: CFGR3 register in SYSCFG
* @{
*/
#define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
0: No remap (DAC trigger is TIM8_TRGO)
1: Remap (DAC trigger is TIM3_TRGO) */
#define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U) /*!< TIM1 ITR3 trigger remap
0: No remap
1: Remap (TIM1_TRG3 = TIM17_OC) */
#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
#if !defined(HAL_REMAP_CFGR3_MASK)
#define HAL_REMAP_CFGR3_MASK (0x01000000U)
#endif
#define HAL_REMAPTRIGGER_DAC1_TRIG3 (0x01010000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
0: Remap (DAC trigger is TIM15_TRGO)
1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
#define HAL_REMAPTRIGGER_DAC1_TRIG5 (0x01020000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
0: No remap
1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
(((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
(((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
(((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
#else
#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
(((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
/**
* @}
*/
#if defined (STM32F302xE)
/** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
* @{
*/
#define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
0: No remap (TIM1_CC3)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
0: No remap (TIM2_CC2)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
0: No remap (TIM4_CC4)
1: Remap (TIM20_CC1) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
0: No remap (TIM6_TRGO)
1: Remap (TIM20_CC2) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
0: No remap (TIM3_CC4)
1: Remap (TIM20_CC3) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
0: No remap (TIM2_CC1)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
0: No remap (EXTI line 15)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
0: No remap (TIM3_CC1)
1: Remap (TIM20_CC4) */
#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13))
/**
* @}
*/
#endif /* STM32F302xE */
#if defined (STM32F303xE) || defined (STM32F398xx)
/** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
* @{
*/
#define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
0: No remap (TIM1_CC3)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
0: No remap (TIM2_CC2)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
0: No remap (TIM4_CC4)
1: Remap (TIM20_CC1) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
0: No remap (TIM6_TRGO)
1: Remap (TIM20_CC2) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
0: No remap (TIM3_CC4)
1: Remap (TIM20_CC3) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
0: No remap (TIM2_CC1)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
0: No remap (EXTI line 15)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
0: No remap (TIM3_CC1)
1: Remap (TIM20_CC4) */
#define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5
0: No remap (EXTI line 2)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6
0: No remap (TIM4_CC1)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15
0: No remap (TIM2_CC1)
1: Remap (TIM20_CC1) */
#define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5
0: No remap (TIM4_CC3)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11
0: No remap (TIM1_CC3)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14
0: No remap (TIM7_TRGO)
1: Remap (TIM20_CC2) */
#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14))
/**
* @}
*/
#endif /* STM32F303xE || STM32F398xx */
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
/** @brief Fast-mode Plus driving capability on a specific GPIO
*/
#if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
#define SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast-mode Plus on PB6 */
#endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
#if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
#define SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast-mode Plus on PB7 */
#endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
#define SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast-mode Plus on PB8 */
#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
#define SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast-mode Plus on PB9 */
#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
/**
* @}
*/
#if defined(SYSCFG_RCR_PAGE0)
/* CCM-SRAM defined */
/** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection
* @{
*/
#define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */
#define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */
#define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */
#define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */
#if defined(SYSCFG_RCR_PAGE4)
/* More than 4KB CCM-SRAM defined */
#define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */
#define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */
#define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */
#define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */
#endif /* SYSCFG_RCR_PAGE4 */
#if defined(SYSCFG_RCR_PAGE8)
#define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */
#define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */
#define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */
#define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */
#define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */
#define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */
#define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */
#define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */
#endif /* SYSCFG_RCR_PAGE8 */
#if defined(SYSCFG_RCR_PAGE8)
#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU))
#elif defined(SYSCFG_RCR_PAGE4)
#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU))
#else
#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU))
#endif /* SYSCFG_RCR_PAGE8 */
/**
* @}
*/
#endif /* SYSCFG_RCR_PAGE0 */
/** @defgroup HAL_SYSCFG_Interrupts HAL SYSCFG Interrupts
* @{
*/
#define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */
#define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */
#define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */
#define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */
#define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */
#define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */
#define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
*/
/** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode
* @{
*/
#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
#define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
#define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
/**
* @}
*/
/** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode
* @{
*/
#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
#define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
#define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
#define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM20_STOP))
#define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM20_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
#define __HAL_FREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
#define __HAL_UNFREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_HRTIM1_STOP */
/**
* @}
*/
/** @defgroup Memory_Mapping_Selection Memory Mapping Selection
* @{
*/
#if defined(SYSCFG_CFGR1_MEM_MODE)
/** @brief Main Flash memory mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
#endif /* SYSCFG_CFGR1_MEM_MODE */
#if defined(SYSCFG_CFGR1_MEM_MODE_0)
/** @brief System Flash memory mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
}while(0U)
#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
/** @brief Embedded SRAM mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
}while(0U)
#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
#if defined(SYSCFG_CFGR1_MEM_MODE_2)
#define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \
}while(0U)
#endif /* SYSCFG_CFGR1_MEM_MODE_2 */
/**
* @}
*/
/** @defgroup Encoder_Mode Encoder Mode
* @{
*/
#if defined(SYSCFG_CFGR1_ENCODER_MODE)
/** @brief No Encoder mode
*/
#define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
#endif /* SYSCFG_CFGR1_ENCODER_MODE */
#if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
/** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
*/
#define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
}while(0U)
#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
#if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
/** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
*/
#define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
}while(0U)
#endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
#if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
/** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
*/
#define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
}while(0U)
#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
/**
* @}
*/
/** @defgroup DMA_Remap_Enable DMA Remap Enable
* @{
*/
#if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
/** @brief DMA remapping enable/disable macros
* @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
*/
#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
(((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
(SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
(SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
}while(0U)
#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
(((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
(SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
(SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
}while(0U)
#elif defined(SYSCFG_CFGR1_DMA_RMP)
/** @brief DMA remapping enable/disable macros
* @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
*/
#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
SYSCFG->CFGR1 |= (__DMA_REMAP__); \
}while(0U)
#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
}while(0U)
#endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
/**
* @}
*/
/** @defgroup FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
* That you can find above these macros.
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0U)
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0U)
/**
* @}
*/
/** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable
* @{
*/
/** @brief SYSCFG interrupt enable/disable macros
* @param __INTERRUPT__ This parameter can be a value of @ref HAL_SYSCFG_Interrupts
*/
#define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
SYSCFG->CFGR1 |= (__INTERRUPT__); \
}while(0U)
#define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
}while(0U)
/**
* @}
*/
#if defined(SYSCFG_CFGR1_USB_IT_RMP)
/** @defgroup USB_Interrupt_Remap USB Interrupt Remap
* @{
*/
/** @brief USB interrupt remapping enable/disable macros
*/
#define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
#define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
/**
* @}
*/
#endif /* SYSCFG_CFGR1_USB_IT_RMP */
#if defined(SYSCFG_CFGR1_VBAT)
/** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable
* @{
*/
/** @brief SYSCFG interrupt enable/disable macros
*/
#define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
#define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
/**
* @}
*/
#endif /* SYSCFG_CFGR1_VBAT */
#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
* @{
*/
/** @brief SYSCFG Break Lockup lock
* Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
* @note The selected configuration is locked and can be unlocked by system reset
*/
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
}while(0U)
/**
* @}
*/
#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
#if defined(SYSCFG_CFGR2_PVD_LOCK)
/** @defgroup PVD_Lock_Enable PVD Lock
* @{
*/
/** @brief SYSCFG Break PVD lock
* Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
* @note The selected configuration is locked and can be unlocked by system reset
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
}while(0U)
/**
* @}
*/
#endif /* SYSCFG_CFGR2_PVD_LOCK */
#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
/** @defgroup SRAM_Parity_Lock SRAM Parity Lock
* @{
*/
/** @brief SYSCFG Break SRAM PARITY lock
* Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
* @note The selected configuration is locked and can be unlocked by system reset
*/
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
}while(0U)
/**
* @}
*/
#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
/** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable
* @{
*/
#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
/** @brief Trigger remapping enable/disable macros
* @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
*/
#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
(((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
(SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
(SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
}while(0U)
#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
(((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
(SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
(SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
}while(0U)
#else
/** @brief Trigger remapping enable/disable macros
* @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
*/
#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
(SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
}while(0U)
#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
(SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
}while(0U)
#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
/**
* @}
*/
#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
/** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable
* @{
*/
/** @brief ADC trigger remapping enable/disable macros
* @param __ADCTRIGGER_REMAP__ This parameter can be a value of @ref HAL_ADC_Trigger_Remapping
*/
#define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
(SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \
}while(0U)
#define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
(SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \
}while(0U)
/**
* @}
*/
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
/** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable
* @{
*/
/**
* @brief Parity check on RAM disable macro
* @note Disabling the parity check on RAM locks the configuration bit.
* To re-enable the parity check on RAM perform a system reset.
*/
#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U)
/**
* @}
*/
#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
#if defined(SYSCFG_RCR_PAGE0)
/** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable
* @{
*/
/** @brief CCM RAM page write protection enable macro
* @param __PAGE_WP__ This parameter can be a value of @ref HAL_Page_Write_Protection
* @note write protection can only be disabled by a system reset
*/
#define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
SYSCFG->RCR |= (__PAGE_WP__); \
}while(0U)
/**
* @}
*/
#endif /* SYSCFG_RCR_PAGE0 */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(__IO uint32_t Delay);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
void HAL_DBGMCU_EnableDBGSleepMode(void);
void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h
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@ -1,241 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_adc.h
* @author MCD Application Team
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_ADC_H
#define __STM32F3xx_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/* Include ADC HAL Extended module */
/* (include on top of file since ADC structures are defined in extended file) */
#include "stm32f3xx_hal_adc_ex.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Types ADC Exported Types
* @{
*/
/**
* @brief HAL ADC state machine: ADC states definition (bitfields)
* @note ADC state machine is managed by bitfields, state must be compared
* with bit by bit.
* For example:
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master ( */
/**
* @brief ADC handle Structure definition
*/
typedef struct __ADC_HandleTypeDef
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC required parameters */
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
}ADC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup ADC_Exported_Macro ADC Exported Macros
* @{
*/
/** @brief Reset ADC handle state
* @param __HANDLE__ ADC handle
* @retval None
*/
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADC_Exported_Functions ADC Exported Functions
* @{
*/
/** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
/**
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
/* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
/* Non-blocking mode: DMA */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
/**
* @}
*/
/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
* @brief ADC Peripheral State functions
* @{
*/
/* Peripheral State functions *************************************************/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32F3xx_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h
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819
lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h
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@ -1,819 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_can.h
* @author MCD Application Team
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_CAN_H
#define __STM32F3xx_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F302x8) || \
defined(STM32F373xC) || defined(STM32F378xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup CAN
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CAN_Exported_Types CAN Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
}HAL_CAN_StateTypeDef;
/**
* @brief CAN init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
uint32_t Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of @ref CAN_operating_mode */
uint32_t SJW; /*!< Specifies the maximum number of time quanta
the CAN hardware is allowed to lengthen or
shorten a bit to perform resynchronization.
This parameter can be a value of @ref CAN_synchronisation_jump_width */
uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
This parameter can be set to ENABLE or DISABLE. */
uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
This parameter can be set to ENABLE or DISABLE. */
}CAN_InitTypeDef;
/**
* @brief CAN filter configuration structure definition
*/
typedef struct
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
uint32_t FilterScale; /*!< Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
uint32_t FilterActivation; /*!< Enable or disable the filter.
This parameter can be set to ENABLE or DISABLE. */
uint32_t BankNumber; /*!< Select the start slave bank filter
F3 devices don't support CAN2 interface (Slave). Therefore this parameter
is meaningless but it has been kept for compatibility accross STM32 families */
}CAN_FilterConfTypeDef;
/**
* @brief CAN Tx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
uint8_t Data[8]; /*!< Contains the data to be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
}CanTxMsgTypeDef;
/**
* @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
uint8_t Data[8]; /*!< Contains the data to be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
This parameter can be CAN_FIFO0 or CAN_FIFO1 */
}CanRxMsgTypeDef;
/**
* @brief CAN handle Structure definition
*/
typedef struct
{
CAN_TypeDef *Instance; /*!< Register base address */
CAN_InitTypeDef Init; /*!< CAN required parameters */
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
HAL_LockTypeDef Lock; /*!< CAN locking object */
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
__IO uint32_t ErrorCode; /*!< CAN Error code
This parameter can be a value of @ref CAN_Error_Code */
}CAN_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CAN_Exported_Constants CAN Exported Constants
* @{
*/
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */
#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */
#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */
#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */
#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */
#define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */
#define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */
#define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */
/**
* @}
*/
/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
/**
* @}
*/
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
/**
* @}
*/
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
* @{
*/
#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
* @{
*/
#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
* @{
*/
#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
/**
* @}
*/
/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
/**
* @}
*/
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
/**
* @}
*/
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
/** @defgroup CAN_identifier_type CAN Identifier Type
* @{
*/
#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
/**
* @}
*/
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
/**
* @}
*/
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
/**
* @}
*/
/** @defgroup CAN_flags CAN Flags
* @{
*/
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
and CAN_ClearFlag() functions. */
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
CAN_GetFlagStatus() function. */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */
#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */
#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */
#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */
#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */
#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */
#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */
/* Receive Flags */
#define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */
#define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */
#define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */
#define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */
/* Operating Mode Flags */
#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */
#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */
/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
/**
* @}
*/
/** @defgroup CAN_interrupts CAN Interrupts
* @{
*/
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
/* Operating Mode Interrupts */
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
/* Error Interrupts */
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
/**
* @}
*/
/** @defgroup CAN_Mailboxes CAN Mailboxes
* @{
*/
/* Mailboxes definition */
#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CAN_Exported_Macros CAN Exported Macros
* @{
*/
/** @brief Reset CAN handle state
* @param __HANDLE__ CAN handle.
* @retval None
*/
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
/**
* @brief Enable the specified CAN interrupts.
* @param __HANDLE__ CAN handle.
* @param __INTERRUPT__ CAN Interrupt
* @retval None
*/
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable the specified CAN interrupts.
* @param __HANDLE__ CAN handle.
* @param __INTERRUPT__ CAN Interrupt
* @retval None
*/
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/**
* @brief Return the number of pending received messages.
* @param __HANDLE__ CAN handle.
* @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* @retval The number of pending message.
*/
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
/** @brief Check whether the specified CAN flag is set or not.
* @param __HANDLE__ specifies the CAN Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
* @arg CAN_FLAG_WKU: Wake up Flag
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
* @arg CAN_FLAG_EWG: Error Warning Flag
* @arg CAN_FLAG_EPV: Error Passive Flag
* @arg CAN_FLAG_BOF: Bus-Off Flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
/** @brief Clear the specified CAN pending flag.
* @param __HANDLE__ specifies the CAN Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
* @arg CAN_FLAG_WKU: Wake up Flag
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
* @arg CAN_FLAG_EWG: Error Warning Flag
* @arg CAN_FLAG_EPV: Error Passive Flag
* @arg CAN_FLAG_BOF: Bus-Off Flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the CAN Handle.
* @param __INTERRUPT__ specifies the CAN interrupt source to check.
* This parameter can be one of the following values:
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
* @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
* @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Check the transmission status of a CAN Frame.
* @param __HANDLE__ CAN handle.
* @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
* @retval The new status of transmission (TRUE or FALSE).
*/
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
/**
* @brief Release the specified receive FIFO.
* @param __HANDLE__ CAN handle.
* @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* @retval None
*/
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
/**
* @brief Cancel a transmit request.
* @param __HANDLE__ specifies the CAN Handle.
* @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
* @retval None
*/
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
/**
* @brief Enable or disables the DBG Freeze for CAN.
* @param __HANDLE__ specifies the CAN Handle.
* @param __NEWSTATE__ new state of the CAN peripheral.
* This parameter can be: ENABLE (CAN reception/transmission is frozen
* during debug. Reception FIFOs can still be accessed/controlled normally)
* or DISABLE (CAN is working during debug).
* @retval None
*/
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
* @brief I/O operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
* @brief CAN Peripheral State functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup CAN_Private_Types CAN Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CAN_Private_Variables CAN Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
#define CAN_FLAG_MASK (0x000000FFU)
/**
* @}
*/
/* Private Macros -----------------------------------------------------------*/
/** @defgroup CAN_Private_Macros CAN Private Macros
* @{
*/
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
((MODE) == CAN_MODE_LOOPBACK)|| \
((MODE) == CAN_MODE_SILENT) || \
((MODE) == CAN_MODE_SILENT_LOOPBACK))
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST))
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
((SCALE) == CAN_FILTERSCALE_32BIT))
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1))
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
#define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU))
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
/**
* @}
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F302x8 || */
/* STM32F373xC || STM32F378xx */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_CAN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cec.h
View file

@ -1,749 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_cec.h
* @author MCD Application Team
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CEC_H
#define __STM32F3xx_HAL_CEC_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(STM32F373xC) || defined(STM32F378xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup CEC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CEC_Exported_Types CEC Exported Types
* @{
*/
/**
* @brief CEC Init Structure definition
*/
typedef struct
{
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
It can be one of @ref CEC_Signal_Free_Time
and belongs to the set {0U,...,7} where
0x0 is the default configuration
else means 0.5U + (SignalFreeTime - 1U) nominal data bit periods */
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
or CEC_EXTENDED_TOLERANCE */
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
CEC_RX_STOP_ON_BRE: reception is stopped. */
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
CEC line upon Bit Rising Error detection.
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
CEC line upon Long Bit Period Error detection.
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
upon an error detected on a broadcast message.
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
1U) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
b) LBPE detection: error-bit generation on the CEC line
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
2U) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
there is no error-bit generation in case of Short Bit Period Error detection in
a broadcast message while LSTN bit is set. */
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
own address (OAR). Messages addressed to different destination are ignored.
Broadcast messages are always received.
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
address (OAR) with positive acknowledge. Messages addressed to different destination
are received, but without interfering with the CEC bus: no acknowledge sent. */
uint16_t OwnAddress; /*!< Own addresses configuration
This parameter can be a value of @ref CEC_OWN_ADDRESS */
uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
}CEC_InitTypeDef;
/**
* @brief HAL CEC State structures definition
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7 (not used)
* x : Should be set to 0
* b6 Error information
* 0 : No Error
* 1 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized. HAL CEC Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
}HAL_CEC_StateTypeDef;
/**
* @brief CEC handle Structure definition
*/
typedef struct
{
CEC_TypeDef *Instance; /*!< CEC registers base address */
CEC_InitTypeDef Init; /*!< CEC communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
HAL_LockTypeDef Lock; /*!< Locking object */
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
in case error is reported */
}CEC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
#define HAL_CEC_ERROR_NONE (0x00000000U) /*!< no error */
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
/**
* @}
*/
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
* @{
*/
#define CEC_DEFAULT_SFT (0x00000000U)
#define CEC_0_5_BITPERIOD_SFT (0x00000001U)
#define CEC_1_5_BITPERIOD_SFT (0x00000002U)
#define CEC_2_5_BITPERIOD_SFT (0x00000003U)
#define CEC_3_5_BITPERIOD_SFT (0x00000004U)
#define CEC_4_5_BITPERIOD_SFT (0x00000005U)
#define CEC_5_5_BITPERIOD_SFT (0x00000006U)
#define CEC_6_5_BITPERIOD_SFT (0x00000007U)
/**
* @}
*/
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
* @{
*/
#define CEC_STANDARD_TOLERANCE (0x00000000U)
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
/**
* @}
*/
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
* @{
*/
#define CEC_NO_RX_STOP_ON_BRE (0x00000000U)
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
/**
* @}
*/
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
* @{
*/
#define CEC_BRE_ERRORBIT_NO_GENERATION (0x00000000U)
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
/**
* @}
*/
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
* @{
*/
#define CEC_LBPE_ERRORBIT_NO_GENERATION (0x00000000U)
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
/**
* @}
*/
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
* @{
*/
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION (0x00000000U)
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
/**
* @}
*/
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
* @{
*/
#define CEC_SFT_START_ON_TXSOM (0x00000000U)
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
/**
* @}
*/
/** @defgroup CEC_Listening_Mode CEC Listening mode option
* @{
*/
#define CEC_REDUCED_LISTENING_MODE (0x00000000U)
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
/**
* @}
*/
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
* @{
*/
#define CEC_CFGR_OAR_LSB_POS (16U)
/**
* @}
*/
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
* @{
*/
#define CEC_INITIATOR_LSB_POS (4U)
/**
* @}
*/
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0U */
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1U */
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2U */
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3U */
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4U */
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5U */
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6U */
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7U */
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9U */
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10U */
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11U */
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12U */
#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13U */
#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14U */
#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15U */
/**
* @}
*/
/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
* @{
*/
#define CEC_IT_TXACKE CEC_IER_TXACKEIE
#define CEC_IT_TXERR CEC_IER_TXERRIE
#define CEC_IT_TXUDR CEC_IER_TXUDRIE
#define CEC_IT_TXEND CEC_IER_TXENDIE
#define CEC_IT_TXBR CEC_IER_TXBRIE
#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define CEC_IT_RXACKE CEC_IER_RXACKEIE
#define CEC_IT_LBPE CEC_IER_LBPEIE
#define CEC_IT_SBPE CEC_IER_SBPEIE
#define CEC_IT_BRE CEC_IER_BREIE
#define CEC_IT_RXOVR CEC_IER_RXOVRIE
#define CEC_IT_RXEND CEC_IER_RXENDIE
#define CEC_IT_RXBR CEC_IER_RXBRIE
/**
* @}
*/
/** @defgroup CEC_Flags_Definitions CEC Flags definition
* @{
*/
#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define CEC_FLAG_TXERR CEC_ISR_TXERR
#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define CEC_FLAG_TXEND CEC_ISR_TXEND
#define CEC_FLAG_TXBR CEC_ISR_TXBR
#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define CEC_FLAG_LBPE CEC_ISR_LBPE
#define CEC_FLAG_SBPE CEC_ISR_SBPE
#define CEC_FLAG_BRE CEC_ISR_BRE
#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define CEC_FLAG_RXEND CEC_ISR_RXEND
#define CEC_FLAG_RXBR CEC_ISR_RXBR
/**
* @}
*/
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
* @{
*/
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
* @{
*/
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
/**
* @}
*/
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
* @{
*/
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CEC_Exported_Macros CEC Exported Macros
* @{
*/
/** @brief Reset CEC handle gstate & RxState
* @param __HANDLE__ CEC handle.
* @retval None
*/
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
} while(0U)
/** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__ specifies the flag to check.
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
* @arg CEC_FLAG_ARBLST: Arbitration Lost
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
* @arg CEC_FLAG_LBPE: Rx Long period Error
* @arg CEC_FLAG_SBPE: Rx Short period Error
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
* @arg CEC_FLAG_RXOVR: Rx Overrun.
* @arg CEC_FLAG_RXEND: End Of Reception.
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
* @retval ITStatus
*/
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/** @brief Clears the interrupt or status flag when raised (write at 1U)
* @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__ specifies the interrupt/status flag to clear.
* This parameter can be one of the following values:
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
* @arg CEC_FLAG_ARBLST: Arbitration Lost
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
* @arg CEC_FLAG_LBPE: Rx Long period Error
* @arg CEC_FLAG_SBPE: Rx Short period Error
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
* @arg CEC_FLAG_RXOVR: Rx Overrun.
* @arg CEC_FLAG_RXEND: End Of Reception.
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
* @retval none
*/
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
/** @brief Enables the specified CEC interrupt.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to enable.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
* @arg CEC_IT_TXEND: End of transmission IT Enable
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
*/
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/** @brief Disables the specified CEC interrupt.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to disable.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
* @arg CEC_IT_TXEND: End of transmission IT Enable
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
*/
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Checks whether or not the specified CEC interrupt is enabled.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to check.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
* @arg CEC_IT_TXEND: End of transmission IT Enable
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval FlagStatus
*/
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/** @brief Enables the CEC device
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
/** @brief Disables the CEC device
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
/** @brief Set Transmission Start flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
/** @brief Set Transmission End flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
*/
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
/** @brief Get Transmission Start flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
/** @brief Get Transmission End flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
/** @brief Clear OAR register
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
* @param __HANDLE__ specifies the CEC Handle.
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
* @retval none
*/
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CEC_Exported_Functions
* @{
*/
/** @addtogroup CEC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
/**
* @}
*/
/** @addtogroup CEC_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
/**
* @}
*/
/** @addtogroup CEC_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions ************************************************/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup CEC_Private_Types CEC Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CEC_Private_Variables CEC Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CEC_Private_Constants CEC Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CEC_Private_Macros CEC Private Macros
* @{
*/
#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
((__MODE__) == CEC_FULL_LISTENING_MODE))
/** @brief Check CEC message size.
* The message size is the payload size: without counting the header,
* it varies from 0 byte (ping operation, one header only, no payload) to
* 15 bytes (1 opcode and up to 14 operands following the header).
* @param __SIZE__ CEC message size.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
/** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register.
* @param __ADDRESS__ CEC own address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
/** @brief Check CEC initiator or destination logical address setting.
* Initiator and destination addresses are coded over 4 bits.
* @param __ADDRESS__ CEC initiator or logical address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CEC_Private_Functions CEC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_CEC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_comp.h
* @author MCD Application Team
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_COMP_H
#define __STM32F3xx_HAL_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup COMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Types COMP Exported Types
* @{
*/
/**
* @brief COMP Init structure definition
*/
typedef struct
{
uint32_t InvertingInput; /*!< Selects the inverting input of the comparator.
This parameter can be a value of @ref COMPEx_InvertingInput */
uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator.
This parameter can be a value of @ref COMPEx_NonInvertingInput
Note: Only available on STM32F302xB/xC, STM32F303xB/xC and STM32F358xx devices */
uint32_t Output; /*!< Selects the output redirection of the comparator.
This parameter can be a value of @ref COMPEx_Output */
uint32_t OutputPol; /*!< Selects the output polarity of the comparator.
This parameter can be a value of @ref COMP_OutputPolarity */
uint32_t Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
This parameter can be a value of @ref COMPEx_Hysteresis
Note: Only available on STM32F302xB/xC, STM32F303xB/xC, STM32F373xB/xC, STM32F358xx and STM32F378xx devices */
uint32_t BlankingSrce; /*!< Selects the output blanking source of the comparator.
This parameter can be a value of @ref COMPEx_BlankingSrce
Note: Not available on STM32F373xB/C and STM32F378xx devices */
uint32_t Mode; /*!< Selects the operating consumption mode of the comparator
to adjust the speed/consumption.
This parameter can be a value of @ref COMPEx_Mode
Note: Not available on STM32F301x6/x8, STM32F302x6/x8, STM32F334x6/x8, STM32F318xx and STM32F328xx devices */
uint32_t WindowMode; /*!< Selects the window mode of the comparator X (X=2U, 4 or 6 if available).
This parameter can be a value of @ref COMPEx_WindowMode */
uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode).
This parameter can be a value of @ref COMP_TriggerMode */
}COMP_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized or disabled */
HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */
HAL_COMP_STATE_READY_LOCKED = 0x11U, /*!< COMP initialized but the configuration is locked */
HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */
}HAL_COMP_StateTypeDef;
/**
* @brief COMP Handle Structure definition
*/
typedef struct
{
COMP_TypeDef *Instance; /*!< Register base address */
COMP_InitTypeDef Init; /*!< COMP required parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
}COMP_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup COMP_Exported_Constants COMP Exported Constants
* @{
*/
/** @defgroup COMP_OutputPolarity COMP Output Polarity
* @{
*/
#define COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output on GPIO isn't inverted */
#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
/**
* @}
*/
/** @defgroup COMP_OutputLevel COMP Output Level
* @{
*/
/* When output polarity is not inverted, comparator output is low when
the non-inverting input is at a lower voltage than the inverting input*/
#define COMP_OUTPUTLEVEL_LOW (0x00000000U)
/* When output polarity is not inverted, comparator output is high when
the non-inverting input is at a higher voltage than the inverting input */
#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUT
/**
* @}
*/
/** @defgroup COMP_TriggerMode COMP Trigger Mode
* @{
*/
#define COMP_TRIGGERMODE_NONE (0x00000000U) /*!< No External Interrupt trigger detection */
#define COMP_TRIGGERMODE_IT_RISING (0x00000001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define COMP_TRIGGERMODE_IT_FALLING (0x00000002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define COMP_TRIGGERMODE_IT_RISING_FALLING (0x00000003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define COMP_TRIGGERMODE_EVENT_RISING (0x00000010U) /*!< Event Mode with Rising edge trigger detection */
#define COMP_TRIGGERMODE_EVENT_FALLING (0x00000020U) /*!< Event Mode with Falling edge trigger detection */
#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (0x00000030U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup COMP_State_Lock COMP State Lock
* @{
*/
#define COMP_STATE_BIT_LOCK (0x00000010U) /* Lock bit in COMP handle state */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup COMP_Exported_Macros COMP Exported Macros
* @{
*/
/** @brief Reset COMP handle state.
* @param __HANDLE__ COMP handle.
* @retval None
*/
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
/**
* @}
*/
/* Include COMP HAL Extended module */
#include "stm32f3xx_hal_comp_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup COMP_Exported_Functions
* @{
*/
/** @addtogroup COMP_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/* IO operation functions *****************************************************/
/** @addtogroup COMP_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
/* Callback in Interrupt mode */
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup COMP_Exported_Functions_Group3
* @{
*/
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/* Peripheral State functions **************************************************/
/** @addtogroup COMP_Exported_Functions_Group4
* @{
*/
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup COMP_Private_Macros COMP Private Macros
* @{
*/
/** @defgroup COMP_IS_COMP_Definitions COMP Private macros to check input parameters
* @{
*/
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
((__POL__) == COMP_OUTPUTPOL_INVERTED))
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_COMP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_conf.h
* @author MCD Application Team
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CONF_H
#define __STM32F3xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CEC_MODULE_ENABLED
#define HAL_COMP_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_HRTIM_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_OPAMP_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_SDADC_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_SMBUS_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_TSC_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
* Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
* Timeout value
*/
#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */
#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE (40000U)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief Time out for LSE start up value in ms.
*/
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
* - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
* - External clock not generated on EVAL 373
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE (8000000U) /*!< Value of the External oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE (3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define INSTRUCTION_CACHE_ENABLE 0U
#define DATA_CACHE_ENABLE 0U
#define USE_SPI_CRC 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/*#define USE_FULL_ASSERT 1U*/
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f3xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f3xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f3xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f3xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f3xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f3xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f3xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32f3xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f3xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f3xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f3xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f3xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f3xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f3xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f3xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32f3xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f3xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f3xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f3xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f3xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32f3xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f3xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f3xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f3xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SDADC_MODULE_ENABLED
#include "stm32f3xx_hal_sdadc.h"
#endif /* HAL_SDADC_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f3xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32f3xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f3xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f3xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include "stm32f3xx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f3xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f3xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f3xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(char* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

442
lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h
View file

@ -1,442 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CORTEX_H
#define __STM32F3xx_HAL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup CORTEX
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
* @{
*/
#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef;
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
/**
* @}
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
#define SYSTICK_CLKSOURCE_HCLK (0x00000004U)
/**
* @}
*/
#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE (0x00000000U)
#define MPU_HARDFAULT_NMI (0x00000002U)
#define MPU_PRIVILEGED_DEFAULT (0x00000004U)
#define MPU_HFNMI_PRIVDEF (0x00000006U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01U)
#define MPU_REGION_DISABLE ((uint8_t)0x00U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported Macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions
* @{
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
* @}
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
#if (__MPU_PRESENT == 1U)
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
((GROUP) == NVIC_PRIORITYGROUP_1) || \
((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
* @{
*/
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
/**
* @}
*/
#if (__MPU_PRESENT == 1U)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
((SIZE) == MPU_REGION_SIZE_64B) || \
((SIZE) == MPU_REGION_SIZE_128B) || \
((SIZE) == MPU_REGION_SIZE_256B) || \
((SIZE) == MPU_REGION_SIZE_512B) || \
((SIZE) == MPU_REGION_SIZE_1KB) || \
((SIZE) == MPU_REGION_SIZE_2KB) || \
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
* @brief CORTEX private functions
* @{
*/
#if (__MPU_PRESENT == 1U)
void HAL_MPU_Disable(void);
void HAL_MPU_Enable(uint32_t MPU_Control);
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -1,366 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_crc.h
* @author MCD Application Team
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CRC_H
#define __STM32F3xx_HAL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup CRC CRC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CRC_Exported_Types CRC Exported Types
* @{
*/
/**
* @brief CRC HAL State Structure definition
*/
typedef enum
{
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
}HAL_CRC_StateTypeDef;
/**
* @brief CRC Init Structure definition
*/
typedef struct
{
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1.
In that case, there is no need to set GeneratingPolynomial field.
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7U, 8U, 16 or 32-bit long value for a polynomial degree
respectively equal to 7U, 8U, 16 or 32. This field is written in normal representation,
e.g., for a polynomial of degree 7U, X^7U + X^6U + X^5U + X^2U + 1 is written 0x65.
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
Value can be either one of
@arg CRC_POLYLENGTH_32B (32-bit CRC),
@arg CRC_POLYLENGTH_16B (16-bit CRC),
@arg CRC_POLYLENGTH_8B (8-bit CRC),
@arg CRC_POLYLENGTH_7B (7-bit CRC). */
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
is set to DEFAULT_INIT_VALUE_ENABLE. */
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
Can be either one of the following values
@arg CRC_INPUTDATA_INVERSION_NONE, no input data inversion
@arg CRC_INPUTDATA_INVERSION_BYTE, byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
@arg CRC_INPUTDATA_INVERSION_HALFWORD, halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
@arg CRC_INPUTDATA_INVERSION_WORD, word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458U */
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either
@arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion,
@arg CRC_OUTPUTDATA_INVERSION_ENABLE: CRC 0x11223344 is converted into 0x22CC4488U */
}CRC_InitTypeDef;
/**
* @brief CRC Handle Structure definition
*/
typedef struct
{
CRC_TypeDef *Instance; /*!< Register base address */
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
HAL_LockTypeDef Lock; /*!< CRC Locking object */
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
Can be either
@arg CRC_INPUTDATA_FORMAT_BYTES, input data is a stream of bytes (8-bit data)
@arg CRC_INPUTDATA_FORMAT_HALFWORDS, input data is a stream of half-words (16-bit data)
@arg CRC_INPUTDATA_FORMAT_WORDS, input data is a stream of words (32-bit data)
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
must occur if InputBufferFormat is not one of the three values listed above */
}CRC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
* @{
*/
#define DEFAULT_CRC32_POLY 0x04C11DB7 /*!< X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1U */
/**
* @}
*/
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
/**
* @}
*/
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7U */
/**
* @}
*/
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
* @{
*/
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
/**
* @}
*/
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
* @{
*/
#define CRC_POLYLENGTH_32B (0x00000000U) /*!< Resort to a 32-bit long generating polynomial */
#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */
#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */
#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */
/**
* @}
*/
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
* @{
*/
#define HAL_CRC_LENGTH_32B 32 /*!< 32-bit long CRC */
#define HAL_CRC_LENGTH_16B 16 /*!< 16-bit long CRC */
#define HAL_CRC_LENGTH_8B 8 /*!< 8-bit long CRC */
#define HAL_CRC_LENGTH_7B 7 /*!< 7-bit long CRC */
/**
* @}
*/
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
* @{
*/
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
* the CRC APIs to provide a correct result */
#define CRC_INPUTDATA_FORMAT_UNDEFINED (0x00000000U) /*!< Undefined input data format */
#define CRC_INPUTDATA_FORMAT_BYTES (0x00000001U) /*!< Input data in byte format */
#define CRC_INPUTDATA_FORMAT_HALFWORDS (0x00000002U) /*!< Input data in half-word format */
#define CRC_INPUTDATA_FORMAT_WORDS (0x00000003U) /*!< Input data in word format */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{
*/
/** @brief Reset CRC handle state.
* @param __HANDLE__ CRC handle.
* @retval None
*/
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/**
* @brief Reset CRC Data Register.
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/**
* @brief Set CRC INIT non-default value
* @param __HANDLE__ CRC handle
* @param __INIT__ 32-bit initial value
* @retval None
*/
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
/**
* @brief Store a 8-bit data in the Independent Data(ID) register.
* @param __HANDLE__ CRC handle
* @param __VALUE__ 8-bit value to be stored in the ID register
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
* @brief Return the 8-bit data stored in the Independent Data(ID) register.
* @param __HANDLE__ CRC handle
* @retval 8-bit value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup CRC_Private_Macros CRC Private Macros
* @{
*/
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
((LENGTH) == CRC_POLYLENGTH_16B) || \
((LENGTH) == CRC_POLYLENGTH_8B) || \
((LENGTH) == CRC_POLYLENGTH_7B))
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
/**
* @}
*/
/* Include CRC HAL Extended module */
#include "stm32f3xx_hal_crc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/** @addtogroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/** @addtogroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions.
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/** @addtogroup CRC_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/**
* @}
*/
/** @defgroup HAL_CRC_Alias_Exported_Functions CRC aliases for Exported Functions
* @{
*/
/* Aliases for inter STM32 series compatibility */
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -1,173 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_crc_ex.h
* @author MCD Application Team
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CRC_EX_H
#define __STM32F3xx_HAL_CRC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup CRCEx CRCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
* @{
*/
/** @defgroup CRCEx_Input_Data_Inversion CRC Extended Input Data Inversion Modes
* @{
*/
#define CRC_INPUTDATA_INVERSION_NONE (0x00000000U) /*!< No input data inversion */
#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) /*!< Word-wise input data inversion */
/**
* @}
*/
/** @defgroup CRCEx_Output_Data_Inversion CRC Extended Output Data Inversion Modes
* @{
*/
#define CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U) /*!< No output data inversion */
#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
* @{
*/
/**
* @brief Set CRC output reversal
* @param __HANDLE__ CRC handle
* @retval None.
*/
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
/**
* @brief Unset CRC output reversal
* @param __HANDLE__ CRC handle
* @retval None.
*/
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
/**
* @brief Set CRC non-default polynomial
* @param __HANDLE__ CRC handle
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
* @retval None.
*/
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup CRCEx_Private_Macros CRCEx Private Macros
* @{
*/
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRCEx_Exported_Functions CRC Extended Exported Functions
* @{
*/
/** @addtogroup CRCEx_Exported_Functions_Group1 CRC Extended Initialization and de-initialization functions
* @brief Extended Initialization and Configuration functions.
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
/**
* @}
*/
/* Peripheral Control functions ***********************************************/
/* Peripheral State and Error functions ***************************************/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_CRC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -1,454 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_dac.h
* @author MCD Application Team
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_DAC_H
#define __STM32F3xx_HAL_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Types DAC Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
}HAL_DAC_StateTypeDef;
/**
* @brief DAC Configuration regular Channel structure definition
*/
typedef struct
{
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DACEx_trigger_selection */
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer
For a given DAC channel, is this paramater applies then DAC_OutputSwitch
does not apply */
uint32_t DAC_OutputSwitch; /*!< Specifies whether the DAC channel output switch is enabled or disabled.
This parameter can be a value of @ref DAC_OutputSwitch
For a given DAC channel, is this paramater applies then DAC_OutputBuffer
does not apply */
}DAC_ChannelConfTypeDef;
/**
* @brief DAC handle Structure definition
*/
typedef struct __DAC_HandleTypeDef
{
DAC_TypeDef *Instance; /*!< Register base address */
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
HAL_LockTypeDef Lock; /*!< DAC locking object */
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1U */
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2U */
__IO uint32_t ErrorCode; /*!< DAC Error code */
}DAC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_Exported_Constants DAC Exported Constants
* @{
*/
/** @defgroup DAC_Error_Code DAC Error Code
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
/**
* @}
*/
/** @defgroup DAC_lfsrunmask_triangleamplitude DAC lfsrunmask triangleamplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 (0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TRIANGLEAMPLITUDE_1 (0x00000000U) /*!< Select max triangle amplitude of 1U */
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3U */
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7U */
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15U */
#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31U */
#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63U */
#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127U */
#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255U */
#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511U */
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023U */
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047U */
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095U */
/**
* @}
*/
/** @defgroup DAC_output_buffer DAC output buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE (0x00000000U)
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
/**
* @}
*/
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
/** @defgroup DAC_output_switch DAC output switch
* @{
*/
#define DAC_OUTPUTSWITCH_DISABLE (0x00000000U)
#define DAC_OUTPUTSWITCH_ENABLE ((uint32_t)DAC_CR_OUTEN1)
/**
* @}
*/
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/** @defgroup DAC_data_alignement DAC data alignement
* @{
*/
#define DAC_ALIGN_12B_R (0x00000000U)
#define DAC_ALIGN_12B_L (0x00000004U)
#define DAC_ALIGN_8B_R (0x00000008U)
/**
* @}
*/
/** @defgroup DAC_flags_definition DAC flags definition
* @{
*/
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
/**
* @}
*/
/** @defgroup DAC_interrupts_definition DAC interrupts definition
* @{
*/
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1)
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_CR_DMAUDRIE2)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Macros DAC Exported Macros
* @{
*/
/** @brief Reset DAC handle state
* @param __HANDLE__ specifies the DAC handle.
* @retval None
*/
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
/** @brief Enable the DAC channel
* @param __HANDLE__ specifies the DAC handle.
* @param __DAC_Channel__ specifies the DAC channel
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Disable the DAC channel
* @param __HANDLE__ specifies the DAC handle
* @param __DAC_Channel__ specifies the DAC channel.
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Set DHR12R1 alignment
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
/** @brief Enable the DAC interrupt
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/** @brief Disable the DAC interrupt
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/** @brief Check whether the specified DAC interrupt source is enabled or not
* @param __HANDLE__ DAC handle
* @param __INTERRUPT__ DAC interrupt source to check
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @retval State of interruption (SET or RESET)
*/
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to get.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @addtogroup DAC_Private_Macros
* @{
*/
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define IS_DAC_OUTPUT_SWITCH_STATE(STATE) (((STATE) == DAC_OUTPUTSWITCH_DISABLE) || \
((STATE) == DAC_OUTPUTSWITCH_ENABLE))
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
((ALIGN) == DAC_ALIGN_12B_L) || \
((ALIGN) == DAC_ALIGN_8B_R))
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
/**
* @}
*/
/* Include DAC HAL Extended module */
#include "stm32f3xx_hal_dac_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DAC_Exported_Functions
* @{
*/
/** @addtogroup DAC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group4
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32F3xx_HAL_DAC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac_ex.h
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@ -1,359 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_dac_ex.h
* @author MCD Application Team
* @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_DAC_EX_H
#define __STM32F3xx_HAL_DAC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup DACEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
* @{
*/
/** @defgroup DACEx_trigger_selection DACEx trigger selection
* @{
*/
#if defined(STM32F301x8) || defined(STM32F318xx)
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F301x8 || STM32F318xx */
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
defined(STM32F302x8)
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F302xE || */
/* STM32F302xC || */
/* STM32F302x8 */
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx)
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 selection */
#define DAC_TRIGGER_T8_TRGO DAC_TRIGGER_T3_TRGO /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM8 selection */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F328xx)
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F303x8 || STM32F328xx */
#if defined(STM32F373xC) || defined(STM32F378xx)
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel (DAC1) */
#define DAC_TRIGGER_T18_TRGO DAC_TRIGGER_T5_TRGO /*!< TIM18 TRGO selected as external conversion trigger for DAC channel (DAC2) */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F373xC || STM32F378xx */
#if defined(STM32F334x8)
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 remap */
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for TIM15 selection */
#define DAC_TRIGGER_HRTIM1_DACTRG1 DAC_TRIGGER_T15_TRGO /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for HRTIM1 DACTRG1 selection */
#define DAC_TRIGGER_HRTIM1_DACTRG2 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC channel (DAC1)
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG5) for HRTIM1 DACTRG2 remap */
#define DAC_TRIGGER_HRTIM1_DACTRG3 DAC_TRIGGER_HRTIM1_DACTRG2 /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC channel (DAC2)*/
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM1_DACTRG2) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F334x8 */
/**
* @}
*/
/** @defgroup DACEx_Channel_selection DACEx Channel selection
* @{
*/
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
#endif /* STM32F302xE || */
/* STM32F302xC || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx)
#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
#define DAC_CHANNEL_2 (0x00000010U) /*!< DAC Channel 2U */
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
#define DAC_CHANNEL_2 (0x00000010U) /*!< DAC Channel 2U */
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F373xC || STM32F378xx */
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DACEx_Private_Macros DACEx Private Macros
* @{
*/
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
#endif /* STM32F302xE || */
/* STM32F302xC || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2))
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2))
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F373xC || STM32F378xx */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DACEx_Exported_Functions
* @{
*/
/** @addtogroup DACEx_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F373xC || STM32F378xx */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_HAL_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

180
lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h
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@ -1,180 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_DEF
#define __STM32F3xx_HAL_DEF
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h"
#if defined USE_LEGACY
#include "Legacy/stm32_hal_legacy.h"
#endif
#include <stdio.h>
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
(__DMA_HANDLE_).Parent = (__HANDLE__); \
} while(0U)
#define UNUSED(x) ((void)(x))
/** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
#if (USE_RTOS == 1U)
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0U)
#endif /* USE_RTOS */
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__GNUC__) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif
#ifdef __cplusplus
}
#endif
#endif /* ___STM32F3xx_HAL_DEF */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

470
lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h
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@ -1,470 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_dma.h
* @author MCD Application Team
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_DMA_H
#define __STM32F3xx_HAL_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types
* @{
*/
/**
* @brief DMA Configuration Structure definition
*/
typedef struct
{
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef;
/**
* @brief HAL DMA State structures definition
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03 /*!< DMA timeout state */
}HAL_DMA_StateTypeDef;
/**
* @brief HAL DMA Error Code structure definition
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
/**
* @brief HAL DMA Callback ID structure definition
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
}HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
uint32_t ChannelIndex; /*!< DMA Channel Index */
} DMA_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants
* @{
*/
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
/**
* @}
*/
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
/**
* @}
*/
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_mode DMA mode
* @{
*/
#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
/**
* @}
*/
/** @defgroup DMA_Priority_level DMA Priority level
* @{
*/
#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
/**
* @}
*/
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{
*/
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
/**
* @}
*/
/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
*/
#define DMA_FLAG_GL1 (0x00000001U)
#define DMA_FLAG_TC1 (0x00000002U)
#define DMA_FLAG_HT1 (0x00000004U)
#define DMA_FLAG_TE1 (0x00000008U)
#define DMA_FLAG_GL2 (0x00000010U)
#define DMA_FLAG_TC2 (0x00000020U)
#define DMA_FLAG_HT2 (0x00000040U)
#define DMA_FLAG_TE2 (0x00000080U)
#define DMA_FLAG_GL3 (0x00000100U)
#define DMA_FLAG_TC3 (0x00000200U)
#define DMA_FLAG_HT3 (0x00000400U)
#define DMA_FLAG_TE3 (0x00000800U)
#define DMA_FLAG_GL4 (0x00001000U)
#define DMA_FLAG_TC4 (0x00002000U)
#define DMA_FLAG_HT4 (0x00004000U)
#define DMA_FLAG_TE4 (0x00008000U)
#define DMA_FLAG_GL5 (0x00010000U)
#define DMA_FLAG_TC5 (0x00020000U)
#define DMA_FLAG_HT5 (0x00040000U)
#define DMA_FLAG_TE5 (0x00080000U)
#define DMA_FLAG_GL6 (0x00100000U)
#define DMA_FLAG_TC6 (0x00200000U)
#define DMA_FLAG_HT6 (0x00400000U)
#define DMA_FLAG_TE6 (0x00800000U)
#define DMA_FLAG_GL7 (0x01000000U)
#define DMA_FLAG_TC7 (0x02000000U)
#define DMA_FLAG_HT7 (0x04000000U)
#define DMA_FLAG_TE7 (0x08000000U)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{
*/
/** @brief Reset DMA handle state
* @param __HANDLE__ DMA handle.
* @retval None
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
/* Interrupt & Flag management */
/**
* @brief Enables the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disables the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval The state of DMA_IT (SET or RESET).
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
* @param __HANDLE__ DMA handle
*
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
/**
* @}
*/
/* Include DMA HAL Extended module */
#include "stm32f3xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions
* @{
*/
/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* Input and Output operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
* @brief DMA private macros
* @{
*/
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
((STATE) == DMA_MINC_DISABLE))
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD))
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
((SIZE) == DMA_MDATAALIGN_WORD ))
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
((MODE) == DMA_CIRCULAR))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_DMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -1,290 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_dma_ex.h
* @author MCD Application Team
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_DMA_EX_H
#define __STM32F3xx_HAL_DMA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup DMAEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
* @{
*/
/* Interrupt & Flag management */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
/**
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
DMA_FLAG_TC5)
/**
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
DMA_FLAG_HT5)
/**
* @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
DMA_FLAG_TE5)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
DMA_FLAG_GL5)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
(DMA1->ISR & (__FLAG__)))
/**
* @brief Clears the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
(DMA1->IFCR = (__FLAG__)))
/**
* @}
*/
#else /* STM32F301x8_STM32F302x8_STM32F318xx_STM32F303x8_STM32F334x8_STM32F328xx Product devices */
/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
* @{
*/
/**
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7)
/**
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7)
/**
* @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
DMA_FLAG_GL7)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
/**
* @brief Clears the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#endif /* __STM32F3xx_HAL_DMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -1,397 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_flash.h
* @author MCD Application Team
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_FLASH_H
#define __STM32F3xx_HAL_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @addtogroup FLASH_Private_Constants
* @{
*/
#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */
/**
* @}
*/
/** @addtogroup FLASH_Private_Macros
* @{
*/
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
((__LATENCY__) == FLASH_LATENCY_1) || \
((__LATENCY__) == FLASH_LATENCY_2))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASH Procedure structure definition
*/
typedef enum
{
FLASH_PROC_NONE = 0U,
FLASH_PROC_PAGEERASE = 1U,
FLASH_PROC_MASSERASE = 2U,
FLASH_PROC_PROGRAMHALFWORD = 3U,
FLASH_PROC_PROGRAMWORD = 4U,
FLASH_PROC_PROGRAMDOUBLEWORD = 5U
} FLASH_ProcedureTypeDef;
/**
* @brief FLASH handle Structure definition
*/
typedef struct
{
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
__IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
__IO uint64_t Data; /*!< Internal variable to save data to be programmed */
HAL_LockTypeDef Lock; /*!< FLASH locking object */
__IO uint32_t ErrorCode; /*!< FLASH error code
This parameter can be a value of @ref FLASH_Error_Codes */
} FLASH_ProcessTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
/** @defgroup FLASH_Error_Codes FLASH Error Codes
* @{
*/
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
/**
* @}
*/
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_DOUBLEWORD (0x03U) /*!<Program a double word (64-bit) at a specified address*/
/**
* @}
*/
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
#define FLASH_LATENCY_0 (0x00000000U) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
/**
* @}
*/
/** @defgroup FLASH_Flag_definition FLASH Flag definition
* @{
*/
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
/**
* @}
*/
/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
* @{
*/
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @brief macros to control FLASH features
* @{
*/
/** @defgroup FLASH_Half_Cycle FLASH Half Cycle
* @brief macros to handle FLASH half cycle
* @{
*/
/**
* @brief Enable the FLASH half cycle access.
* @retval None
*/
#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
/**
* @brief Disable the FLASH half cycle access.
* @retval None
*/
#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
/**
* @}
*/
/** @defgroup FLASH_EM_Latency FLASH Latency
* @brief macros to handle FLASH Latency
* @{
*/
/**
* @brief Set the FLASH Latency.
* @param __LATENCY__ FLASH Latency
* This parameter can be one of the following values:
* @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
* @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
* @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles
* @retval None
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
/**
* @brief Get the FLASH Latency.
* @retval FLASH Latency
* This parameter can be one of the following values:
* @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
* @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
* @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles
*/
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
/**
* @}
*/
/** @defgroup FLASH_Prefetch FLASH Prefetch
* @brief macros to handle FLASH Prefetch buffer
* @{
*/
/**
* @brief Enable the FLASH prefetch buffer.
* @retval None
*/
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
/**
* @brief Disable the FLASH prefetch buffer.
* @retval None
*/
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
/**
* @}
*/
/** @defgroup FLASH_Interrupt FLASH Interrupts
* @brief macros to handle FLASH interrupts
* @{
*/
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
* @arg @ref FLASH_IT_ERR Error Interrupt
* @retval none
*/
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__))
/**
* @brief Disable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
* @arg @ref FLASH_IT_ERR Error Interrupt
* @retval none
*/
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__))
/**
* @brief Get the specified FLASH flag status.
* @param __FLAG__ specifies the FLASH flag to check.
* This parameter can be one of the following values:
* @arg @ref FLASH_FLAG_BSY FLASH Busy flag
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the specified FLASH flag.
* @param __FLAG__ specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
* @retval none
*/
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))
/**
* @}
*/
/**
* @}
*/
/* Include FLASH HAL Extended module */
#include "stm32f3xx_hal_flash_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Functions
* @{
*/
/** @addtogroup FLASH_Exported_Functions_Group1
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
/* FLASH IRQ handler function */
void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/**
* @}
*/
/** @addtogroup FLASH_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
/**
* @}
*/
/** @addtogroup FLASH_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
uint32_t HAL_FLASH_GetError(void);
/**
* @}
*/
/**
* @}
*/
/* Private function -------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_FLASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h
View file

@ -1,498 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_flash_ex.h
* @author MCD Application Team
* @brief Header file of Flash HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_FLASH_EX_H
#define __STM32F3xx_HAL_FLASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup FLASHEx
* @{
*/
/** @addtogroup FLASHEx_Private_Constants
* @{
*/
#define FLASH_SIZE_DATA_REGISTER (0x1FFFF7CCU)
/**
* @}
*/
/** @addtogroup FLASHEx_Private_Macros
* @{
*/
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
((VALUE) == FLASH_TYPEERASE_MASSERASE))
#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
((VALUE) == OB_WRPSTATE_ENABLE))
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
((LEVEL) == OB_RDP_LEVEL_1))/*||\
((LEVEL) == OB_RDP_LEVEL_2))*/
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
#define IS_OB_SDACD_VDD_MONITOR(VDD_MONITOR) (((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_SET) || \
((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_RESET))
#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
((ADDRESS) <= 0x0803FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= 0x0807FFFFU))
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
((ADDRESS) <= 0x0800FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
((ADDRESS) <= 0x08007FFFU) : ((ADDRESS) <= 0x08003FFFU))))
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0803FFFFU) : \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0801FFFFU) : \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU)))
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0807FFFFU)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU) : \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08007FFFU) : \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08003FFFU)))
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
* @{
*/
/**
* @brief FLASH Erase structure definition
*/
typedef struct
{
uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
This parameter can be a value of @ref FLASHEx_Type_Erase */
uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */
uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
} FLASH_EraseInitTypeDef;
/**
* @brief FLASH Options bytes program structure definition
*/
typedef struct
{
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
This parameter can be a value of @ref FLASHEx_OB_Type */
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_OB_WRP_State */
uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY / SDADC12_VDD_MONITOR
This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
@ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring,
@ref FLASHEx_OB_RAM_Parity_Check_Enable.
@if STM32F373xC
And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
@endif
@if STM32F378xx
And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
@endif
*/
uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
This parameter can be a value of @ref FLASHEx_OB_Data_Address */
uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
} FLASH_OBProgramInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
* @{
*/
/** @defgroup FLASHEx_Page_Size FLASHEx Page Size
* @{
*/
#define FLASH_PAGE_SIZE 0x800
/**
* @}
*/
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
* @{
*/
#define FLASH_TYPEERASE_PAGES (0x00U) /*!<Pages erase only*/
#define FLASH_TYPEERASE_MASSERASE (0x01U) /*!<Flash mass erase activation*/
/**
* @}
*/
/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
* @{
*/
/** @defgroup FLASHEx_OB_Type Option Bytes Type
* @{
*/
#define OPTIONBYTE_WRP (0x01U) /*!<WRP option byte configuration*/
#define OPTIONBYTE_RDP (0x02U) /*!<RDP option byte configuration*/
#define OPTIONBYTE_USER (0x04U) /*!<USER option byte configuration*/
#define OPTIONBYTE_DATA (0x08U) /*!<DATA option byte configuration*/
/**
* @}
*/
/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
* @{
*/
#define OB_WRPSTATE_DISABLE (0x00U) /*!<Disable the write protection of the desired pages*/
#define OB_WRPSTATE_ENABLE (0x01U) /*!<Enable the write protection of the desired pagess*/
/**
* @}
*/
/** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection
* @{
*/
#define OB_WRP_PAGES0TO1 (0x00000001U) /* Write protection of page 0 to 1 */
#define OB_WRP_PAGES2TO3 (0x00000002U) /* Write protection of page 2 to 3 */
#define OB_WRP_PAGES4TO5 (0x00000004U) /* Write protection of page 4 to 5 */
#define OB_WRP_PAGES6TO7 (0x00000008U) /* Write protection of page 6 to 7 */
#define OB_WRP_PAGES8TO9 (0x00000010U) /* Write protection of page 8 to 9 */
#define OB_WRP_PAGES10TO11 (0x00000020U) /* Write protection of page 10 to 11 */
#define OB_WRP_PAGES12TO13 (0x00000040U) /* Write protection of page 12 to 13 */
#define OB_WRP_PAGES14TO15 (0x00000080U) /* Write protection of page 14 to 15 */
#define OB_WRP_PAGES16TO17 (0x00000100U) /* Write protection of page 16 to 17 */
#define OB_WRP_PAGES18TO19 (0x00000200U) /* Write protection of page 18 to 19 */
#define OB_WRP_PAGES20TO21 (0x00000400U) /* Write protection of page 20 to 21 */
#define OB_WRP_PAGES22TO23 (0x00000800U) /* Write protection of page 22 to 23 */
#define OB_WRP_PAGES24TO25 (0x00001000U) /* Write protection of page 24 to 25 */
#define OB_WRP_PAGES26TO27 (0x00002000U) /* Write protection of page 26 to 27 */
#define OB_WRP_PAGES28TO29 (0x00004000U) /* Write protection of page 28 to 29 */
#define OB_WRP_PAGES30TO31 (0x00008000U) /* Write protection of page 30 to 31 */
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
#define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
#define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
#define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
#define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
#define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
#define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
#define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
#define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
#define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
#define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
#define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
#define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
#define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
#define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
#define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
#define OB_WRP_PAGES62TO127 (0x80000000U) /* Write protection of page 62 to 127 */
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
#define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
#define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
#define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
#define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
#define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
#define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
#define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
#define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
#define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
#define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
#define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
#define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
#define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
#define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
#define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
#define OB_WRP_PAGES62TO255 (0x80000000U) /* Write protection of page 62 to 255 */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#define OB_WRP_PAGES0TO15MASK (0x000000FFU)
#define OB_WRP_PAGES16TO31MASK (0x0000FF00U)
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
#define OB_WRP_PAGES48TO127MASK (0xFF000000U)
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
#define OB_WRP_PAGES48TO255MASK (0xFF000000U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
#define OB_WRP_PAGES48TO127MASK (0xFF000000U)
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) \
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
#define OB_WRP_ALLPAGES (0xFFFFFFFFU) /*!< Write protection of all pages */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define OB_WRP_ALLPAGES (0x0000FFFFU) /*!< Write protection of all pages */
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
/**
* @}
*/
/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
* @{
*/
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
it's no more possible to go back to level 1 or 0U */
/**
* @}
*/
/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x01U) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware IWDG selected */
/**
* @}
*/
/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
* @{
*/
#define OB_STOP_NO_RST ((uint8_t)0x02U) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
/**
* @}
*/
/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
* @{
*/
#define OB_STDBY_NO_RST ((uint8_t)0x04U) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
/**
* @}
*/
/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
* @{
*/
#define OB_BOOT1_RESET ((uint8_t)0x00U) /*!< BOOT1 Reset */
#define OB_BOOT1_SET ((uint8_t)0x10U) /*!< BOOT1 Set */
/**
* @}
*/
/** @defgroup FLASHEx_OB_VDDA_Analog_Monitoring Option Byte VDDA Analog Monitoring
* @{
*/
#define OB_VDDA_ANALOG_ON ((uint8_t)0x20U) /*!< Analog monitoring on VDDA Power source ON */
#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00U) /*!< Analog monitoring on VDDA Power source OFF */
/**
* @}
*/
/** @defgroup FLASHEx_OB_RAM_Parity_Check_Enable Option Byte SRAM Parity Check Enable
* @{
*/
#define OB_SRAM_PARITY_SET ((uint8_t)0x00U) /*!< SRAM parity check enable set */
#define OB_SRAM_PARITY_RESET ((uint8_t)0x40U) /*!< SRAM parity check enable reset */
/**
* @}
*/
#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
/** @defgroup FLASHEx_OB_SDADC12_VDD_MONITOR OB SDADC12 VDD MONITOR
* @{
*/
#define OB_SDACD_VDD_MONITOR_RESET ((uint8_t)0x00U) /*!< SDADC VDD Monitor reset */
#define OB_SDACD_VDD_MONITOR_SET ((uint8_t)0x80U) /*!< SDADC VDD Monitor set */
/**
* @}
*/
#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
* @{
*/
#define OB_DATA_ADDRESS_DATA0 (0x1FFFF804U)
#define OB_DATA_ADDRESS_DATA1 (0x1FFFF806U)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
*/
/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
/**
* @}
*/
/** @addtogroup FLASHEx_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_FLASH_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -1,313 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_GPIO_H
#define __STM32F3xx_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull */
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
}GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
}GPIO_PinState;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins GPIO pins
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ
* - X : GPIO mode or EXTI Mode
* - y : External IT or Event trigger detection
* - z : IO configuration on External IT or Event
* - Y : Output type (Push Pull or Open Drain)
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
*/
#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */
#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup GPIO_speed GPIO speed
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */
/**
* @}
*/
/** @defgroup GPIO_pull GPIO pull
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @brief Check whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending flags.
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending bits.
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
((__MODE__) == GPIO_MODE_AF_PP) ||\
((__MODE__) == GPIO_MODE_AF_OD) ||\
((__MODE__) == GPIO_MODE_IT_RISING) ||\
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
((__SPEED__) == GPIO_SPEED_FREQ_HIGH))
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
((__PULL__) == GPIO_PULLUP) || \
((__PULL__) == GPIO_PULLDOWN))
/**
* @}
*/
/* Include GPIO HAL Extended module */
#include "stm32f3xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_GPIO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_i2c.h
* @author MCD Application Team
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_I2C_H
#define __STM32F3xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization
section in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :\n
* b7-b6 Error information\n
* 00 : No Error\n
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 IP initilisation status\n
* 0 : Reset (IP not initialized)\n
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (IP in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (IP busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
* b0 Tx state\n
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;
/**
* @}
*/
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :\n
* b7 (not used)\n
* x : Should be set to 0\n
* b6\n
* 0 : None\n
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
* b5\n
* 0 : None\n
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
* b4\n
* 0 : None\n
* 1 : Master (HAL I2C communication is in Master Mode)\n
* b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
} HAL_I2C_ModeTypeDef;
/**
* @}
*/
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
} I2C_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
/**
* @}
*/
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_GENERALCALL_DISABLE (0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
#define I2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP I2C_CR2_STOP
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE I2C_CR2_START
/**
* @}
*/
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @brief I2C Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Include I2C HAL Extended module */
#include "stm32f3xx_hal_i2c_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
/**
* @}
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
* @{
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions are defined in stm32f3xx_hal_i2c.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

179
lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h
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@ -1,179 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_i2c_ex.h
* @author MCD Application Team
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_I2C_EX_H
#define __STM32F3xx_HAL_I2C_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup I2CEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#if defined(SYSCFG_CFGR1_I2C2_FMP)
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#else
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
#endif
#if defined(SYSCFG_CFGR1_I2C3_FMP)
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#else
#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
#endif
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
* @{
*/
/* Private functions are defined in stm32f3xx_hal_i2c_ex.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_I2C_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

486
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View file

@ -1,486 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_i2s.h
* @author MCD Application Team
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_I2S_H
#define __STM32F3xx_HAL_I2S_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup I2S
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2S_Exported_Types I2S Exported Types
* @{
*/
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
This parameter can be a value of @ref I2S_Clock_Source */
uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
This parameter can be a value of @ref I2S_FullDuplex_Mode */
}I2S_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */
}HAL_I2S_StateTypeDef;
/**
* @brief I2S handle Structure definition
*/
typedef struct
{
SPI_TypeDef *Instance; /*!< I2S registers base address */
I2S_InitTypeDef Init; /*!< I2S communication parameters */
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
decremented when a sample is received.
NbSamplesReceived = RxBufferSize-RxBufferCount) */
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
__IO uint32_t ErrorCode; /*!< I2S Error code
This parameter can be a value of @ref I2S_Error */
}I2S_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
/** @defgroup I2S_Error I2S Error
* @{
*/
#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
#define HAL_I2S_ERROR_UNKNOW (0x00000010U) /*!< Unknow Error error */
/**
* @}
*/
/** @defgroup I2S_Clock_Source I2S Clock Source
* @{
*/
#define I2S_CLOCK_EXTERNAL (0x00000001U)
#define I2S_CLOCK_SYSCLK (0x00000002U)
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
((CLOCK) == I2S_CLOCK_SYSCLK))
/**
* @}
*/
/** @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MODE_SLAVE_TX (0x00000000U)
#define I2S_MODE_SLAVE_RX (0x00000100U)
#define I2S_MODE_MASTER_TX (0x00000200U)
#define I2S_MODE_MASTER_RX (0x00000300U)
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
((MODE) == I2S_MODE_SLAVE_RX) || \
((MODE) == I2S_MODE_MASTER_TX)|| \
((MODE) == I2S_MODE_MASTER_RX))
/**
* @}
*/
/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS (0x00000000U)
#define I2S_STANDARD_MSB (0x00000010U)
#define I2S_STANDARD_LSB (0x00000020U)
#define I2S_STANDARD_PCM_SHORT (0x00000030U)
#define I2S_STANDARD_PCM_LONG (0x000000B0U)
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
((STANDARD) == I2S_STANDARD_MSB) || \
((STANDARD) == I2S_STANDARD_LSB) || \
((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
((STANDARD) == I2S_STANDARD_PCM_LONG))
/**
* @}
*/
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B (0x00000000U)
#define I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)
#define I2S_DATAFORMAT_24B (0x00000003U)
#define I2S_DATAFORMAT_32B (0x00000005U)
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
((FORMAT) == I2S_DATAFORMAT_24B) || \
((FORMAT) == I2S_DATAFORMAT_32B))
/**
* @}
*/
/** @defgroup I2S_MCLK_Output I2S MCLK Output
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
/**
* @}
*/
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIOFREQ_192K (192000U)
#define I2S_AUDIOFREQ_96K (96000U)
#define I2S_AUDIOFREQ_48K (48000U)
#define I2S_AUDIOFREQ_44K (44100U)
#define I2S_AUDIOFREQ_32K (32000U)
#define I2S_AUDIOFREQ_22K (22050U)
#define I2S_AUDIOFREQ_16K (16000U)
#define I2S_AUDIOFREQ_11K (11025U)
#define I2S_AUDIOFREQ_8K (8000U)
#define I2S_AUDIOFREQ_DEFAULT (2U)
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
((FREQ) == I2S_AUDIOFREQ_DEFAULT))
/**
* @}
*/
/** @defgroup I2S_FullDuplex_Mode I2S Full Duplex Mode
* @{
*/
#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)
#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)
#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
/**
* @}
*/
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
#define I2S_CPOL_LOW (0x00000000U)
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
((CPOL) == I2S_CPOL_HIGH))
/**
* @}
*/
/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
* @{
*/
#define I2S_IT_TXE SPI_CR2_TXEIE
#define I2S_IT_RXNE SPI_CR2_RXNEIE
#define I2S_IT_ERR SPI_CR2_ERRIE
/**
* @}
*/
/** @defgroup I2S_Flag_definition I2S Flag definition
* @{
*/
#define I2S_FLAG_TXE SPI_SR_TXE
#define I2S_FLAG_RXNE SPI_SR_RXNE
#define I2S_FLAG_UDR SPI_SR_UDR
#define I2S_FLAG_OVR SPI_SR_OVR
#define I2S_FLAG_FRE SPI_SR_FRE
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define I2S_FLAG_BSY SPI_SR_BSY
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2S_Exported_Macros I2S Exported Macros
* @{
*/
/** @brief Reset I2S handle state
* @param __HANDLE__ I2S handle.
* @retval None
*/
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
/** @brief Enable or disable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2S flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun flag
* @arg I2S_FLAG_OVR: Overrun flag
* @arg I2S_FLAG_FRE: Frame error flag
* @arg I2S_FLAG_CHSIDE: Channel Side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the I2S OVR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->DR; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
}while(0U)
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
__IO uint32_t tmpreg;\
tmpreg = ((__HANDLE__)->Instance->SR);\
UNUSED(tmpreg); \
}while(0U)
/**
* @}
*/
/* Include I2S HAL Extended module */
#include "stm32f3xx_hal_i2s_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2S_Exported_Functions
* @{
*/
/** @addtogroup I2S_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/** @addtogroup I2S_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/** @addtogroup I2S_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx || */
/* STM32F373xC || STM32F378xx */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_I2S_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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View file

@ -1,219 +0,0 @@
/**
******************************************************************************
* @file stm32f3xx_hal_i2s_ex.h
* @author MCD Application Team
* @brief Header file of I2S HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_I2S_EX_H
#define __STM32F3xx_HAL_I2S_EX_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup I2SEx I2SEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup I2SEx_Exported_Macros I2S Extended Exported Macros
* @{
*/
#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
/** @brief Enable or disable the specified I2SExt peripheral.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
/** @brief Enable or disable the specified I2SExt interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__))
#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
/** @brief Checks if the specified I2SExt interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2SExt flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun flag
* @arg I2S_FLAG_OVR: Overrun flag
* @arg I2S_FLAG_FRE: Frame error flag
* @arg I2S_FLAG_CHSIDE: Channel Side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the I2SExt OVR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{(I2SxEXT((__HANDLE__)->Instance)->DR;\
(I2SxEXT((__HANDLE__)->Instance)->SR;}while(0U)
/** @brief Clears the I2SExt UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__)(I2SxEXT((__HANDLE__)->Instance)->SR)
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Initialization/de-initialization functions ********************************/
/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
* @{
*/
#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
/** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended Features Functions
* @{
*/
/* Extended features functions ************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
/**
* @}
*/
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup I2S I2S
* @{
*/
/** @addtogroup I2S_Exported_Functions I2S Exported Functions
* @{
*/
#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
/** @addtogroup I2S_Exported_Functions_Group2 IO operation functions
* @{
*/
/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
/* Callback used in non blocking modes (DMA only) */
void HAL_I2S_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx || */
/* STM32F373xC || STM32F378xx */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_I2S_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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