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Merge pull request #4756 from iNavFlight/de_disable_irq

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[SYS] Disable all hardware IRQs prior to reboot to ensure they don't fire when handler is not initialized
This commit is contained in:
Konstantin Sharlaimov 2019-05-27 23:24:10 +02:00 • committed by GitHub
commit c336dd9c24
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GPG key ID: 4AEE18F83AFDEB23
3 changed files with 52 additions and 5 deletions
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23
src/main/drivers/system_stm32f30x.c
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@ -27,19 +27,36 @@
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
void SetSysClock(uint8_t underclock); void SetSysClock(uint8_t underclock);
inline static void NVIC_DisableAllIRQs(void)
{
// We access CMSIS NVIC registers directly here
for (int x = 0; x < 8; x++) {
// Mask all IRQs controlled by a ICERx
NVIC->ICER[x] = 0xFFFFFFFF;
// Clear all pending IRQs controlled by a ICPRx
NVIC->ICPR[x] = 0xFFFFFFFF;
}
}
void systemReset(void) void systemReset(void)
{ {
// Disable all NVIC interrupts
__disable_irq();
NVIC_DisableAllIRQs();
// Generate system reset // Generate system reset
SCB->AIRCR = AIRCR_VECTKEY_MASK | (uint32_t)0x04; SCB->AIRCR = AIRCR_VECTKEY_MASK | (uint32_t)0x04;
} }
void systemResetToBootloader(void) void systemResetToBootloader(void)
{ {
// 1FFFF000 -> 20000200 -> SP __disable_irq();
// 1FFFF004 -> 1FFFF021 -> PC NVIC_DisableAllIRQs();
*((uint32_t *)0x20009FFC) = 0xDEADBEEF; // 40KB SRAM STM32F30X *((uint32_t *)0x20009FFC) = 0xDEADBEEF; // 40KB SRAM STM32F30X
systemReset();
// Generate system reset
SCB->AIRCR = AIRCR_VECTKEY_MASK | (uint32_t)0x04;
} }

17
src/main/drivers/system_stm32f4xx.c
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@ -32,16 +32,31 @@
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
void SetSysClock(void); void SetSysClock(void);
inline static void NVIC_DisableAllIRQs(void)
{
// We access CMSIS NVIC registers directly here
for (int x = 0; x < 8; x++) {
// Mask all IRQs controlled by a ICERx
NVIC->ICER[x] = 0xFFFFFFFF;
// Clear all pending IRQs controlled by a ICPRx
NVIC->ICPR[x] = 0xFFFFFFFF;
}
}
void systemReset(void) void systemReset(void)
{ {
__disable_irq(); __disable_irq();
NVIC_DisableAllIRQs();
NVIC_SystemReset(); NVIC_SystemReset();
} }
void systemResetToBootloader(void) void systemResetToBootloader(void)
{ {
*((uint32_t *)0x2001FFFC) = 0xDEADBEEF; // 128KB SRAM STM32F4XX
__disable_irq(); __disable_irq();
NVIC_DisableAllIRQs();
*((uint32_t *)0x2001FFFC) = 0xDEADBEEF; // 128KB SRAM STM32F4XX
NVIC_SystemReset(); NVIC_SystemReset();
} }

17
src/main/drivers/system_stm32f7xx.c
View file

@ -31,16 +31,31 @@
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
void SystemClock_Config(void); void SystemClock_Config(void);
inline static void NVIC_DisableAllIRQs(void)
{
// We access CMSIS NVIC registers directly here
for (int x = 0; x < 8; x++) {
// Mask all IRQs controlled by a ICERx
NVIC->ICER[x] = 0xFFFFFFFF;
// Clear all pending IRQs controlled by a ICPRx
NVIC->ICPR[x] = 0xFFFFFFFF;
}
}
void systemReset(void) void systemReset(void)
{ {
__disable_irq(); __disable_irq();
NVIC_DisableAllIRQs();
NVIC_SystemReset(); NVIC_SystemReset();
} }
void systemResetToBootloader(void) void systemResetToBootloader(void)
{ {
(*(__IO uint32_t *) (BKPSRAM_BASE + 4)) = 0xDEADBEEF; // flag that will be readable after reboot
__disable_irq(); __disable_irq();
NVIC_DisableAllIRQs();
(*(__IO uint32_t *) (BKPSRAM_BASE + 4)) = 0xDEADBEEF; // flag that will be readable after reboot
NVIC_SystemReset(); NVIC_SystemReset();
} }