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Fixed timerInit
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55deab18de
commit
c7c9985904
3 changed files with 71 additions and 19 deletions
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@ -6,6 +6,22 @@
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*/
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#include "stm32f30x.h"
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#include "rcc.h"
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#include "timer.h"
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const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
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{ .TIMx = TIM1, .rcc = RCC_APB2(TIM1) },
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{ .TIMx = TIM2, .rcc = RCC_APB1(TIM2) },
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{ .TIMx = TIM3, .rcc = RCC_APB1(TIM3) },
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{ .TIMx = TIM4, .rcc = RCC_APB1(TIM4) },
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{ .TIMx = TIM6, .rcc = RCC_APB1(TIM6) },
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{ .TIMx = TIM7, .rcc = RCC_APB1(TIM7) },
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{ .TIMx = TIM8, .rcc = RCC_APB2(TIM8) },
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{ .TIMx = TIM15, .rcc = RCC_APB2(TIM15) },
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{ .TIMx = TIM16, .rcc = RCC_APB2(TIM16) },
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{ .TIMx = TIM17, .rcc = RCC_APB2(TIM17) },
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};
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/**
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* @brief Selects the TIM Output Compare Mode.
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@ -52,8 +68,7 @@ void TIM_SelectOCxM_NoDisable(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t
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tmp = (uint32_t) TIMx;
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tmp += CCMR_OFFSET;
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if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
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{
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if ((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) {
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tmp += (TIM_Channel>>1);
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/* Reset the OCxM bits in the CCMRx register */
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@ -61,9 +76,7 @@ void TIM_SelectOCxM_NoDisable(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t
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/* Configure the OCxM bits in the CCMRx register */
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*(__IO uint32_t *) tmp |= TIM_OCMode;
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}
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else
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{
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} else {
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tmp += (uint32_t)(TIM_Channel - (uint32_t)4)>> (uint32_t)1;
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/* Reset the OCxM bits in the CCMRx register */
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