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131 lines
4.4 KiB
C
131 lines
4.4 KiB
C
/**
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******************************************************************************
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* @file mt48lc4m32b2.h
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* @author MCD Application Team
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* @brief This file contains all the description of the MT48LC4M32B2 SDRAM
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* memory.
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef MT48LC4M32B2_H
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#define MT48LC4M32B2_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "mt48lc4m32b2_conf.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Components
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* @{
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*/
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/** @addtogroup MT48LC4M32B2
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* @{
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*/
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/** @defgroup MT48LC4M32B2_Exported_Types MT48LC4M32B2 Exported Types
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* @{
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*/
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typedef struct
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{
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uint32_t TargetBank; /*!< Target Bank */
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uint32_t RefreshMode; /*!< Refresh Mode */
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uint32_t RefreshRate; /*!< Refresh Rate */
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uint32_t BurstLength; /*!< Burst Length */
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uint32_t BurstType; /*!< Burst Type */
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uint32_t CASLatency; /*!< CAS Latency */
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uint32_t OperationMode; /*!< Operation Mode */
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uint32_t WriteBurstMode; /*!< Write Burst Mode */
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} MT48LC4M32B2_Context_t;
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/**
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* @}
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*/
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/** @defgroup MT48LC4M32B2_Exported_Constants MT48LC4M32B2 Exported Constants
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* @{
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*/
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#define MT48LC4M32B2_OK (0)
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#define MT48LC4M32B2_ERROR (-1)
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/* Register Mode */
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#define MT48LC4M32B2_BURST_LENGTH_1 0x00000000U
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#define MT48LC4M32B2_BURST_LENGTH_2 0x00000001U
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#define MT48LC4M32B2_BURST_LENGTH_4 0x00000002U
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#define MT48LC4M32B2_BURST_LENGTH_8 0x00000004U
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#define MT48LC4M32B2_BURST_TYPE_SEQUENTIAL 0x00000000U
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#define MT48LC4M32B2_BURST_TYPE_INTERLEAVED 0x00000008U
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#define MT48LC4M32B2_CAS_LATENCY_2 0x00000020U
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#define MT48LC4M32B2_CAS_LATENCY_3 0x00000030U
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#define MT48LC4M32B2_OPERATING_MODE_STANDARD 0x00000000U
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#define MT48LC4M32B2_WRITEBURST_MODE_PROGRAMMED 0x00000000U
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#define MT48LC4M32B2_WRITEBURST_MODE_SINGLE 0x00000200U
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/* Command Mode */
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#define MT48LC4M32B2_NORMAL_MODE_CMD 0x00000000U
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#define MT48LC4M32B2_CLK_ENABLE_CMD 0x00000001U
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#define MT48LC4M32B2_PALL_CMD 0x00000002U
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#define MT48LC4M32B2_AUTOREFRESH_MODE_CMD 0x00000003U
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#define MT48LC4M32B2_LOAD_MODE_CMD 0x00000004U
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#define MT48LC4M32B2_SELFREFRESH_MODE_CMD 0x00000005U
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#define MT48LC4M32B2_POWERDOWN_MODE_CMD 0x00000006U
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/**
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* @}
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*/
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/** @addtogroup MT48LC4M32B2_Exported_Functions
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* @{
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*/
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int32_t MT48LC4M32B2_Init(SDRAM_HandleTypeDef *Ctx, MT48LC4M32B2_Context_t *pRegMode);
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int32_t MT48LC4M32B2_ClockEnable(SDRAM_HandleTypeDef *Ctx, uint32_t Interface);
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int32_t MT48LC4M32B2_Precharge(SDRAM_HandleTypeDef *Ctx, uint32_t Interface);
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int32_t MT48LC4M32B2_ModeRegConfig(SDRAM_HandleTypeDef *Ctx, MT48LC4M32B2_Context_t *pRegMode);
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int32_t MT48LC4M32B2_TimingConfig(SDRAM_HandleTypeDef *Ctx, FMC_SDRAM_TimingTypeDef *pTiming);
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int32_t MT48LC4M32B2_RefreshMode(SDRAM_HandleTypeDef *Ctx, uint32_t Interface, uint32_t RefreshMode);
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int32_t MT48LC4M32B2_RefreshRate(SDRAM_HandleTypeDef *Ctx, uint32_t RefreshCount);
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int32_t MT48LC4M32B2_EnterPowerMode(SDRAM_HandleTypeDef *Ctx, uint32_t Interface);
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int32_t MT48LC4M32B2_ExitPowerMode(SDRAM_HandleTypeDef *Ctx, uint32_t Interface);
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int32_t MT48LC4M32B2_Sendcmd(SDRAM_HandleTypeDef *Ctx, FMC_SDRAM_CommandTypeDef *SdramCmd);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* MT48LC4M32B2_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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