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/*
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* Copyright (C) OpenTX
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*
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* Based on code named
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* th9x - http://code.google.com/p/th9x
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* er9x - http://code.google.com/p/er9x
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* gruvin9x - http://code.google.com/p/gruvin9x
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*
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* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#pragma once
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#include <stdint.h>
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#define __IO volatile /*!< Defines 'read / write' permissions */
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#ifndef __weak
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#define __weak __attribute__((weak))
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#endif /* __weak */
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#define GPIO_NUMBER 16U
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#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
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((__GPIOx__) == (GPIOB))? 1U :\
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((__GPIOx__) == (GPIOC))? 2U :\
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((__GPIOx__) == (GPIOD))? 3U :\
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((__GPIOx__) == (GPIOE))? 4U :\
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((__GPIOx__) == (GPIOF))? 5U :\
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((__GPIOx__) == (GPIOG))? 6U :\
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((__GPIOx__) == (GPIOH))? 7U :\
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((__GPIOx__) == (GPIOI))? 8U :\
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((__GPIOx__) == (GPIOJ))? 9U : 10U)
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#define HAL_MAX_DELAY 0xFFFFFFFFU
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/* AHB1 Peripheral Clock Enable Disable
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* @brief Enable or disable the AHB1 peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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*/
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#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00U; \
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SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00U; \
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SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00U; \
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SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00U; \
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SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
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#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
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#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
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#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
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/* APB1 Peripheral Clock Enable Disable
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* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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*/
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#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00U; \
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SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00U; \
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SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00U; \
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SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
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UNUSED(tmpreg); \
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} while(0U)
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#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
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#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
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#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
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#define __HAL_LOCK(__HANDLE__) \
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do{ \
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if((__HANDLE__)->Lock == HAL_LOCKED) \
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{ \
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return HAL_BUSY; \
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} \
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else \
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{ \
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(__HANDLE__)->Lock = HAL_LOCKED; \
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} \
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}while (0U)
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#define __HAL_UNLOCK(__HANDLE__) \
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do{ \
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(__HANDLE__)->Lock = HAL_UNLOCKED; \
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}while (0U)
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/* Enable the specified I2C peripheral.
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* @param __HANDLE__ specifies the I2C Handle.
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* @retval None
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*/
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#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
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/* Disable the specified I2C peripheral.
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* @param __HANDLE__ specifies the I2C Handle.
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* @retval None
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*/
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#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
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// I2C Private Constants
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#define I2C_FLAG_MASK 0x0000FFFFU
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#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */
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#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */
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#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
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#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
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#define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */
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#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
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// I2C Private Macros
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#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
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#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
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#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
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#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
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#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
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#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
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#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
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((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
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((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
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#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
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#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
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#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
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#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
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#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
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#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
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#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
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// I2C duty cycle in fast mode
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#define I2C_DUTYCYCLE_2 0x00000000U
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#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
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// I2C addressing mode
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#define I2C_ADDRESSINGMODE_7BIT 0x00004000U
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#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
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// I2C dual addressing mode
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#define I2C_DUALADDRESS_DISABLE 0x00000000U
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#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
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// I2C general call addressing mode
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#define I2C_GENERALCALL_DISABLE 0x00000000U
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#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
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// I2C nostretch mode
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#define I2C_NOSTRETCH_DISABLE 0x00000000U
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#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
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// I2C Error Code definition
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#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */
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#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */
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#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
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#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */
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#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */
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#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
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#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
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#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */
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#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */
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#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */
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// I2C XferOptions definition
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#define I2C_FIRST_FRAME 0x00000001U
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#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U
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#define I2C_NEXT_FRAME 0x00000004U
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#define I2C_FIRST_AND_LAST_FRAME 0x00000008U
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#define I2C_LAST_FRAME_NO_STOP 0x00000010U
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#define I2C_LAST_FRAME 0x00000020U
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// List of XferOptions
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#define I2C_OTHER_FRAME (0x00AA0000U)
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#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U)
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// I2C states
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#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
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#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
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#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
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#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
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#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
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#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
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// I2C Analog Filter
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#define I2C_ANALOGFILTER_ENABLE 0x00000000U
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#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF
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// I2C Memory Address Size
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#define I2C_MEMADD_SIZE_8BIT 0x00000001U
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#define I2C_MEMADD_SIZE_16BIT 0x00000010U
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// DMA Error Code
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#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
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#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
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#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
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#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
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#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
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#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
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#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
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#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
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/* Clears the I2C ADDR pending flag.
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* @param __HANDLE__ specifies the I2C Handle.
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* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
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* @retval None
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*/
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#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
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do{ \
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__IO uint32_t tmpreg = 0x00U; \
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tmpreg = (__HANDLE__)->Instance->SR1; \
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tmpreg = (__HANDLE__)->Instance->SR2; \
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UNUSED(tmpreg); \
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} while(0)
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/* Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
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* @param __HANDLE__ specifies the I2C Handle.
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* @param __FLAG__ specifies the flag to clear.
|
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* This parameter can be any combination of the following values:
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* @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
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* @arg I2C_FLAG_AF: Acknowledge failure flag
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* @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
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* @arg I2C_FLAG_BERR: Bus error flag
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* @retval None
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*/
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#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = (uint16_t)(~((__FLAG__) & I2C_FLAG_MASK)))
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/* Enable or disable the specified I2C interrupts.
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* @param __HANDLE__ specifies the I2C Handle.
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* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
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* This parameter can be one of the following values:
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* @arg I2C_IT_BUF: Buffer interrupt enable
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* @arg I2C_IT_EVT: Event interrupt enable
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* @arg I2C_IT_ERR: Error interrupt enable
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* @retval None
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*/
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#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
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#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
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// DMA Data transfer direction
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#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
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#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
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#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
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/* Enable the specified DMA Stream.
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* @param __HANDLE__ DMA handle
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* @retval None
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||||
*/
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||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
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||||
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||||
/* Disable the specified DMA Stream.
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* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
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||||
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||||
// HAL Status structures definition
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00U,
|
||||
HAL_ERROR = 0x01U,
|
||||
HAL_BUSY = 0x02U,
|
||||
HAL_TIMEOUT = 0x03U
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
// HAL lock structures definition
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00U,
|
||||
HAL_LOCKED = 0x01U
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* HAL State structure definition
|
||||
* HAL I2C State value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : Abort (Abort user request on going)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
|
||||
* b4 (not used)
|
||||
* x : Should be set to 0
|
||||
* b3
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)
|
||||
* 1 : Listen (Peripheral in Address Listen Mode)
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (Peripheral busy with some configuration or internal operations)
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
/* HAL Mode structure definition
|
||||
* HAL I2C Mode value coding follow below described bitmap :
|
||||
* b7 (not used)
|
||||
* x : Should be set to 0
|
||||
* b6
|
||||
* 0 : None
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)
|
||||
* b5
|
||||
* 0 : None
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)
|
||||
* b4
|
||||
* 0 : None
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)
|
||||
* b3-b2-b1-b0 (not used)
|
||||
* xxxx : Should be set to 0000
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
} HAL_I2C_ModeTypeDef;
|
||||
|
||||
// HAL DMA State structures definition
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
|
||||
HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
|
||||
HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
|
||||
}HAL_DMA_StateTypeDef;
|
||||
|
||||
// DMA handle Structure definition
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Stream_TypeDef *Instance; /*!< Register base address */
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
void *Parent; /*!< Parent object state */
|
||||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
|
||||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
|
||||
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
|
||||
void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
|
||||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
|
||||
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
|
||||
uint32_t StreamIndex; /*!< DMA Stream Index */
|
||||
}DMA_HandleTypeDef;
|
||||
|
||||
|
||||
// I2C configuration structure definition
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockSpeed; /*!< Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */
|
||||
uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_addressing_mode */
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_dual_addressing_mode */
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_general_call_addressing_mode */
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_nostretch_mode */
|
||||
} HAL_I2C_InitTypeDef; // WARNING: renamed from I2C_InitTypeDef due to conflict
|
||||
|
||||
// I2C handle structure definition
|
||||
typedef struct
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
HAL_I2C_InitTypeDef Init; /*!< I2C communication parameters (MOD!) */
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
__IO uint32_t XferOptions; /*!< I2C transfer options */
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
|
||||
context for internal usage */
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
__IO uint32_t Devaddress; /*!< I2C Target device address */
|
||||
__IO uint32_t Memaddress; /*!< I2C Target memory address */
|
||||
__IO uint32_t MemaddSize; /*!< I2C Target memory address size */
|
||||
__IO uint32_t EventCount; /*!< I2C Event counter */
|
||||
} I2C_HandleTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register */
|
||||
__IO uint32_t Reserved0;
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
|
||||
} DMA_Base_Registers;
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
Loading…
Add table
Add a link
Reference in a new issue