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[Taranis] Saves around 800bytes RAM (the same space is used for

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DSM2/PPM/PXX pulses on external module)
This commit is contained in:
bsongis 2015-03-31 22:35:13 +02:00
parent 4d2b387098
commit 9886dede73
10 changed files with 141 additions and 126 deletions
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47
radio/src/pulses/dsm2_arm.cpp
View file

@ -39,15 +39,7 @@
#define DSM2_SEND_BIND (1 << 7) #define DSM2_SEND_BIND (1 << 7)
#define DSM2_SEND_RANGECHECK (1 << 5) #define DSM2_SEND_RANGECHECK (1 << 5)
#if defined(PCBTARANIS) #if defined(PCBSKY9X)
uint16_t dsm2Stream[400]; // Likely more than we need
uint16_t *dsm2StreamPtr;
uint16_t dsm2Value;
#else
uint8_t dsm2Stream[64]; // Likely more than we need
uint8_t *dsm2StreamPtr;
uint8_t dsm2SerialByte ;
uint8_t dsm2SerialBitCount;
uint8_t dsm2BindTimer = DSM2_BIND_TIMEOUT; uint8_t dsm2BindTimer = DSM2_BIND_TIMEOUT;
#endif #endif
@ -60,18 +52,17 @@ uint8_t dsm2BindTimer = DSM2_BIND_TIMEOUT;
#define BITLEN_DSM2 (8*2) //125000 Baud => 8uS per bit #define BITLEN_DSM2 (8*2) //125000 Baud => 8uS per bit
#if defined(PCBTARANIS) #if defined(PCBTARANIS)
uint8_t dsm2Index = 0;
void _send_1(uint8_t v) void _send_1(uint8_t v)
{ {
if (dsm2Index == 0) if (modulePulsesData[EXTERNAL_MODULE].dsm2.index == 0)
v -= 2; v -= 2;
else else
v += 2; v += 2;
dsm2Value += v; modulePulsesData[EXTERNAL_MODULE].dsm2.value += v;
*dsm2StreamPtr++ = dsm2Value; *modulePulsesData[EXTERNAL_MODULE].dsm2.ptr++ = modulePulsesData[EXTERNAL_MODULE].dsm2.value;
dsm2Index = (dsm2Index+1) % 2; modulePulsesData[EXTERNAL_MODULE].dsm2.index = (modulePulsesData[EXTERNAL_MODULE].dsm2.index+1) % 2;
} }
void sendByteDsm2(uint8_t b) //max 10 changes 0 10 10 10 10 1 void sendByteDsm2(uint8_t b) //max 10 changes 0 10 10 10 10 1
@ -94,19 +85,19 @@ void sendByteDsm2(uint8_t b) //max 10 changes 0 10 10 10 10 1
} }
void putDsm2Flush() void putDsm2Flush()
{ {
dsm2StreamPtr--; //remove last stopbits and modulePulsesData[EXTERNAL_MODULE].dsm2.ptr--; //remove last stopbits and
*dsm2StreamPtr++ = 44010; // Past the 44000 of the ARR *modulePulsesData[EXTERNAL_MODULE].dsm2.ptr++ = 44010; // Past the 44000 of the ARR
} }
#else #else
void putDsm2SerialBit(uint8_t bit) void putDsm2SerialBit(uint8_t bit)
{ {
dsm2SerialByte >>= 1; modulePulsesData[EXTERNAL_MODULE].dsm2.serialByte >>= 1;
if (bit & 1) { if (bit & 1) {
dsm2SerialByte |= 0x80; modulePulsesData[EXTERNAL_MODULE].dsm2.serialByte |= 0x80;
} }
if (++dsm2SerialBitCount >= 8) { if (++modulePulsesData[EXTERNAL_MODULE].dsm2.serialBitCount >= 8) {
*dsm2StreamPtr++ = dsm2SerialByte; *modulePulsesData[EXTERNAL_MODULE].dsm2.ptr++ = modulePulsesData[EXTERNAL_MODULE].dsm2.serialByte;
dsm2SerialBitCount = 0; modulePulsesData[EXTERNAL_MODULE].dsm2.serialBitCount = 0;
} }
} }
void sendByteDsm2(uint8_t b) // max 10changes 0 10 10 10 10 1 void sendByteDsm2(uint8_t b) // max 10changes 0 10 10 10 10 1
@ -137,18 +128,18 @@ void setupPulsesDSM2(unsigned int port)
static uint8_t dsmDat[2+6*2]={0xFF,0x00, 0x00,0xAA, 0x05,0xFF, 0x09,0xFF, 0x0D,0xFF, 0x13,0x54, 0x14,0xAA}; static uint8_t dsmDat[2+6*2]={0xFF,0x00, 0x00,0xAA, 0x05,0xFF, 0x09,0xFF, 0x0D,0xFF, 0x13,0x54, 0x14,0xAA};
#if defined(PCBSKY9X) #if defined(PCBSKY9X)
dsm2SerialByte = 0 ; modulePulsesData[EXTERNAL_MODULE].dsm2.serialByte = 0 ;
dsm2SerialBitCount = 0 ; modulePulsesData[EXTERNAL_MODULE].dsm2.serialBitCount = 0 ;
#else #else
dsm2Value = 0; modulePulsesData[EXTERNAL_MODULE].dsm2.value = 0;
dsm2Index = 1; modulePulsesData[EXTERNAL_MODULE].dsm2.index = 1;
#endif #endif
dsm2StreamPtr = dsm2Stream; modulePulsesData[EXTERNAL_MODULE].dsm2.ptr = modulePulsesData[EXTERNAL_MODULE].dsm2.pulses;
#if defined(PCBTARANIS) #if defined(PCBTARANIS)
dsm2Value = 100; modulePulsesData[EXTERNAL_MODULE].dsm2.value = 100;
*dsm2StreamPtr++ = dsm2Value; *modulePulsesData[EXTERNAL_MODULE].dsm2.ptr++ = modulePulsesData[EXTERNAL_MODULE].dsm2.value;
#endif #endif
switch (s_current_protocol[port]) { switch (s_current_protocol[port]) {

9
radio/src/pulses/ppm_arm.cpp
View file

@ -36,13 +36,6 @@
#include "../opentx.h" #include "../opentx.h"
#define PPM_STREAM_INIT { 2000, 2200, 2400, 2600, 2800, 3000, 3200, 3400, 9000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
#if defined(PCBTARANIS)
uint16_t ppmStream[NUM_MODULES+1][20] = { PPM_STREAM_INIT, PPM_STREAM_INIT, PPM_STREAM_INIT };
#else
uint16_t ppmStream[NUM_MODULES][20] = { MODULES_INIT(PPM_STREAM_INIT) };
#endif
void setupPulsesPPM(unsigned int port) // Don't enable interrupts through here void setupPulsesPPM(unsigned int port) // Don't enable interrupts through here
{ {
int16_t PPM_range = g_model.extendedLimits ? (512*LIMIT_EXT_PERCENT/100) * 2 : 512 * 2; //range of 0.7..1.7msec int16_t PPM_range = g_model.extendedLimits ? (512*LIMIT_EXT_PERCENT/100) * 2 : 512 * 2; //range of 0.7..1.7msec
@ -65,7 +58,7 @@ void setupPulsesPPM(unsigned int port) // Don't enable interru
pwmptr->PWM_CH_NUM[pwmCh].PWM_CMR |= 0x00000200 ; // CPOL pwmptr->PWM_CH_NUM[pwmCh].PWM_CMR |= 0x00000200 ; // CPOL
#endif #endif
uint16_t * ptr = ppmStream[port]; uint16_t * ptr = (port == TRAINER_MODULE ? trainerPulsesData.ppm.pulses : modulePulsesData[port].ppm.pulses);
int32_t rest = 22500u * 2; int32_t rest = 22500u * 2;
rest += (int32_t(g_model.moduleData[port].ppmFrameLength)) * 1000; rest += (int32_t(g_model.moduleData[port].ppmFrameLength)) * 1000;
for (uint32_t i=firstCh; i<lastCh; i++) { for (uint32_t i=firstCh; i<lastCh; i++) {

3
radio/src/pulses/pulses_arm.cpp
View file

@ -41,6 +41,9 @@ uint8_t s_current_protocol[NUM_MODULES] = { MODULES_INIT(255) };
uint16_t failsafeCounter[NUM_MODULES] = { MODULES_INIT(100) }; uint16_t failsafeCounter[NUM_MODULES] = { MODULES_INIT(100) };
uint8_t moduleFlag[NUM_MODULES] = { 0 }; uint8_t moduleFlag[NUM_MODULES] = { 0 };
ModulePulsesData modulePulsesData[NUM_MODULES];
TrainerPulsesData trainerPulsesData;
void setupPulses(unsigned int port) void setupPulses(unsigned int port)
{ {
uint8_t required_protocol; uint8_t required_protocol;

55
radio/src/pulses/pulses_arm.h
View file

@ -47,6 +47,59 @@ extern uint8_t s_current_protocol[NUM_MODULES];
extern uint8_t s_pulses_paused; extern uint8_t s_pulses_paused;
extern uint16_t failsafeCounter[NUM_MODULES]; extern uint16_t failsafeCounter[NUM_MODULES];
#if defined(PCBSKY9X)
PACK(struct PpmPulsesData {
uint16_t pulses[20];
uint32_t index;
});
PACK(struct PxxPulsesData {
uint8_t pulses[64];
uint8_t *ptr;
uint16_t pcmValue;
uint16_t pcmCrc;
uint32_t pcmOnesCount;
uint16_t serialByte;
uint16_t serialBitCount;
});
PACK(struct Dsm2PulsesData {
uint8_t pulses[64];
uint8_t *ptr;
uint8_t serialByte ;
uint8_t serialBitCount;
});
#else
PACK(struct PpmPulsesData {
uint16_t pulses[20];
uint16_t *ptr;
});
PACK(struct PxxPulsesData {
uint16_t pulses[400];
uint16_t *ptr;
uint16_t pcmValue;
uint16_t pcmCrc;
uint32_t pcmOnesCount;
});
PACK(struct Dsm2PulsesData {
uint16_t pulses[400];
uint16_t *ptr;
uint16_t value;
uint16_t index;
});
#endif
union ModulePulsesData {
PxxPulsesData pxx;
Dsm2PulsesData dsm2;
PpmPulsesData ppm;
};
union TrainerPulsesData {
PpmPulsesData ppm;
};
extern ModulePulsesData modulePulsesData[NUM_MODULES];
extern TrainerPulsesData trainerPulsesData;
void setupPulses(unsigned int port); void setupPulses(unsigned int port);
void setupPulsesDSM2(unsigned int port); void setupPulsesDSM2(unsigned int port);
void setupPulsesPXX(unsigned int port); void setupPulsesPXX(unsigned int port);
@ -64,7 +117,7 @@ inline void startPulses()
setupPulses(INTERNAL_MODULE); setupPulses(INTERNAL_MODULE);
setupPulses(EXTERNAL_MODULE); setupPulses(EXTERNAL_MODULE);
#else #else
setupPulses(0); setupPulses(EXTERNAL_MODULE);
#endif #endif
#if defined(HUBSAN) #if defined(HUBSAN)

56
radio/src/pulses/pxx_arm.cpp
View file

@ -40,18 +40,6 @@
#define PXX_SEND_FAILSAFE (1 << 4) #define PXX_SEND_FAILSAFE (1 << 4)
#define PXX_SEND_RANGECHECK (1 << 5) #define PXX_SEND_RANGECHECK (1 << 5)
#if defined(PCBTARANIS)
uint16_t pxxStream[NUM_MODULES][400];
uint16_t *pxxStreamPtr[NUM_MODULES];
#else
uint8_t pxxStream[NUM_MODULES][64];
uint8_t *pxxStreamPtr[NUM_MODULES];
#endif
uint16_t PxxValue[NUM_MODULES];
uint16_t PcmCrc[NUM_MODULES];
uint8_t PcmOnesCount[NUM_MODULES];
const uint16_t CRCTable[]= const uint16_t CRCTable[]=
{ {
0x0000,0x1189,0x2312,0x329b,0x4624,0x57ad,0x6536,0x74bf, 0x0000,0x1189,0x2312,0x329b,0x4624,0x57ad,0x6536,0x74bf,
@ -90,40 +78,38 @@ const uint16_t CRCTable[]=
void crc(uint8_t data, unsigned int port) void crc(uint8_t data, unsigned int port)
{ {
PcmCrc[port]=(PcmCrc[port]<<8)^(CRCTable[((PcmCrc[port]>>8)^data) & 0xFF]); modulePulsesData[port].pxx.pcmCrc = (modulePulsesData[port].pxx.pcmCrc<<8) ^ (CRCTable[((modulePulsesData[port].pxx.pcmCrc>>8)^data) & 0xFF]);
} }
#if defined(PCBTARANIS) #if defined(PCBTARANIS)
void putPcmPart(uint8_t value, unsigned int port) void putPcmPart(uint8_t value, unsigned int port)
{ {
PxxValue[port] += 18 ; // Output 1 for this time modulePulsesData[port].pxx.pcmValue += 18 ; // Output 1 for this time
*pxxStreamPtr[port]++ = PxxValue[port] ; *modulePulsesData[port].pxx.ptr++ = modulePulsesData[port].pxx.pcmValue ;
PxxValue[port] += 14 ; modulePulsesData[port].pxx.pcmValue += 14 ;
if (value) { if (value) {
PxxValue[port] += 16 ; modulePulsesData[port].pxx.pcmValue += 16 ;
} }
*pxxStreamPtr[port]++ = PxxValue[port] ; // Output 0 for this time *modulePulsesData[port].pxx.ptr++ = modulePulsesData[port].pxx.pcmValue ; // Output 0 for this time
} }
void putPcmFlush(unsigned int port) void putPcmFlush(unsigned int port)
{ {
*pxxStreamPtr[port]++ = 18010 ; // Past the 18000 of the ARR *modulePulsesData[port].pxx.ptr++ = 18010 ; // Past the 18000 of the ARR
} }
#else #else
uint8_t pcmSerialByte[NUM_MODULES];
uint8_t pcmSerialBitCount[NUM_MODULES];
void putPcmSerialBit(uint8_t bit, unsigned int port) void putPcmSerialBit(uint8_t bit, unsigned int port)
{ {
pcmSerialByte[port] >>= 1; modulePulsesData[port].pxx.serialByte >>= 1;
if (bit & 1) { if (bit & 1) {
pcmSerialByte[port] |= 0x80; modulePulsesData[port].pxx.serialByte |= 0x80;
} }
if (++pcmSerialBitCount[port] >= 8) { if (++modulePulsesData[port].pxx.serialBitCount >= 8) {
*pxxStreamPtr[port]++ = pcmSerialByte[port]; *modulePulsesData[port].pxx.ptr++ = modulePulsesData[port].pxx.serialByte;
pcmSerialBitCount[port] = 0; modulePulsesData[port].pxx.serialBitCount = 0;
} }
} }
@ -139,7 +125,7 @@ void putPcmPart(uint8_t value, unsigned int port)
void putPcmFlush(unsigned int port) void putPcmFlush(unsigned int port)
{ {
while (pcmSerialBitCount[port] != 0) { while (modulePulsesData[port].pxx.serialBitCount != 0) {
putPcmSerialBit(1, port); putPcmSerialBit(1, port);
} }
} }
@ -149,14 +135,14 @@ void putPcmFlush(unsigned int port)
void putPcmBit(uint8_t bit, unsigned int port) void putPcmBit(uint8_t bit, unsigned int port)
{ {
if (bit) { if (bit) {
PcmOnesCount[port] += 1; modulePulsesData[port].pxx.pcmOnesCount += 1;
putPcmPart(1, port); putPcmPart(1, port);
} }
else { else {
PcmOnesCount[port] = 0; modulePulsesData[port].pxx.pcmOnesCount = 0;
putPcmPart(0, port); putPcmPart(0, port);
} }
if (PcmOnesCount[port] >= 5) { if (modulePulsesData[port].pxx.pcmOnesCount >= 5) {
putPcmBit(0, port); // Stuff a 0 bit in putPcmBit(0, port); // Stuff a 0 bit in
} }
} }
@ -189,10 +175,10 @@ void setupPulsesPXX(unsigned int port)
{ {
uint16_t chan=0, chan_low=0; uint16_t chan=0, chan_low=0;
pxxStreamPtr[port] = pxxStream[port]; modulePulsesData[port].pxx.ptr = modulePulsesData[port].pxx.pulses;
PxxValue[port] = 0 ; modulePulsesData[port].pxx.pcmValue = 0 ;
PcmCrc[port] = 0; modulePulsesData[port].pxx.pcmCrc = 0;
PcmOnesCount[port] = 0; modulePulsesData[port].pxx.pcmOnesCount = 0;
/* Preamble */ /* Preamble */
putPcmPart(0, port); putPcmPart(0, port);
@ -271,7 +257,7 @@ void setupPulsesPXX(unsigned int port)
/* CRC16 */ /* CRC16 */
putPcmByte(0, port); putPcmByte(0, port);
chan = PcmCrc[port]; chan = modulePulsesData[port].pxx.pcmCrc;
putPcmByte(chan>>8, port); putPcmByte(chan>>8, port);
putPcmByte(chan, port); putPcmByte(chan, port);

1
radio/src/targets/simu/simpgmspace.h
View file

@ -420,6 +420,7 @@ extern OS_MutexID audioMutex;
#define CoLeaveMutexSection(m) pthread_mutex_unlock(&(m)) #define CoLeaveMutexSection(m) pthread_mutex_unlock(&(m))
#define CoTickDelay(...) #define CoTickDelay(...)
#define CoCreateFlag(...) 0 #define CoCreateFlag(...) 0
#define CoGetOSTime(...) 0
inline void UART3_Configure(uint32_t baudrate, uint32_t masterClock) { } inline void UART3_Configure(uint32_t baudrate, uint32_t masterClock) { }
#define UART_Stop(...) #define UART_Stop(...)
#define UART3_Stop(...) #define UART3_Stop(...)

28
radio/src/targets/sky9x/pulses_driver.cpp
View file

@ -36,13 +36,6 @@
#include "../../opentx.h" #include "../../opentx.h"
extern uint16_t ppmStream[NUM_MODULES][20];
volatile uint32_t ppmStreamIndex[NUM_MODULES] = { MODULES_INIT(0) }; // Modified in interrupt routine
extern uint8_t pxxStream[NUM_MODULES][64]; // TODO not here, duplicated
extern uint8_t *pxxStreamPtr[NUM_MODULES]; // TODO not here, duplicated
extern uint8_t dsm2Stream[64]; // Likely more than we need
extern uint8_t *dsm2StreamPtr;
void module_output_active() void module_output_active()
{ {
register Pio *pioptr = PIOA ; register Pio *pioptr = PIOA ;
@ -55,7 +48,6 @@ void module_output_active()
#endif #endif
} }
void init_main_ppm(uint32_t period, uint32_t out_enable) void init_main_ppm(uint32_t period, uint32_t out_enable)
{ {
register Pwm *pwmptr ; register Pwm *pwmptr ;
@ -245,8 +237,8 @@ extern "C" void PWM_IRQHandler(void)
else { else {
// Kick off serial output here // Kick off serial output here
sscptr = SSC; sscptr = SSC;
sscptr->SSC_TPR = CONVERT_PTR_UINT(pxxStream[EXTERNAL_MODULE]); sscptr->SSC_TPR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].pxx.pulses);
sscptr->SSC_TCR = (uint8_t *)pxxStreamPtr[EXTERNAL_MODULE] - (uint8_t *)pxxStream[EXTERNAL_MODULE]; sscptr->SSC_TCR = (uint8_t *)modulePulsesData[EXTERNAL_MODULE].pxx.ptr - (uint8_t *)modulePulsesData[EXTERNAL_MODULE].pxx.pulses;
sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers
} }
break; break;
@ -269,16 +261,16 @@ extern "C" void PWM_IRQHandler(void)
else { else {
// Kick off serial output here // Kick off serial output here
sscptr = SSC; sscptr = SSC;
sscptr->SSC_TPR = CONVERT_PTR_UINT(dsm2Stream); sscptr->SSC_TPR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].dsm2.pulses);
sscptr->SSC_TCR = (uint8_t *)dsm2StreamPtr - (uint8_t *)dsm2Stream; sscptr->SSC_TCR = (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.pulses;
sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers
} }
break; break;
default: default:
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = ppmStream[EXTERNAL_MODULE][ppmStreamIndex[EXTERNAL_MODULE]++]; // Period in half uS pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = modulePulsesData[EXTERNAL_MODULE].ppm.pulses[modulePulsesData[EXTERNAL_MODULE].ppm.index++]; // Period in half uS
if (ppmStream[EXTERNAL_MODULE][ppmStreamIndex[EXTERNAL_MODULE]] == 0) { if (modulePulsesData[EXTERNAL_MODULE].ppm.pulses[modulePulsesData[EXTERNAL_MODULE].ppm.index] == 0) {
ppmStreamIndex[EXTERNAL_MODULE] = 0; modulePulsesData[EXTERNAL_MODULE].ppm.index = 0;
setupPulses(EXTERNAL_MODULE); setupPulses(EXTERNAL_MODULE);
} }
break; break;
@ -287,9 +279,9 @@ extern "C" void PWM_IRQHandler(void)
} }
if (reason & PWM_ISR1_CHID1) { if (reason & PWM_ISR1_CHID1) {
pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = ppmStream[EXTRA_MODULE][ppmStreamIndex[EXTRA_MODULE]++] ; // Period in half uS pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = modulePulsesData[EXTRA_MODULE].ppm.pulses[modulePulsesData[EXTRA_MODULE].ppm.index++] ; // Period in half uS
if (ppmStream[EXTRA_MODULE][ppmStreamIndex[EXTRA_MODULE]] == 0) { if (modulePulsesData[EXTRA_MODULE].ppm.pulses[modulePulsesData[EXTRA_MODULE].ppm.index] == 0) {
ppmStreamIndex[EXTRA_MODULE] = 0; modulePulsesData[EXTRA_MODULE].ppm.index = 0;
setupPulsesPPM(EXTRA_MODULE); setupPulsesPPM(EXTRA_MODULE);
} }
} }

7
radio/src/targets/taranis/board_taranis.h
View file

@ -196,8 +196,11 @@ uint32_t isBootloaderStart(const void * buffer);
void init_no_pulses(uint32_t port); void init_no_pulses(uint32_t port);
void disable_no_pulses(uint32_t port); void disable_no_pulses(uint32_t port);
void init_ppm( uint32_t module_index ); void init_ppm( uint32_t module_index );
void set_external_ppm_parameters(uint32_t idleTime, uint32_t delay, uint32_t positive);
void disable_ppm( uint32_t module_index ); void disable_ppm( uint32_t module_index );
void set_external_ppm_parameters(uint32_t idleTime, uint32_t delay, uint32_t positive);
#if defined(TARANIS_INTERNAL_PPM)
void set_internal_ppm_parameters(uint32_t idleTime, uint32_t delay, uint32_t positive);
#endif
void init_pxx( uint32_t module_index ); void init_pxx( uint32_t module_index );
void disable_pxx( uint32_t module_index ); void disable_pxx( uint32_t module_index );
void init_dsm2( uint32_t module_index ); void init_dsm2( uint32_t module_index );
@ -261,7 +264,7 @@ void pwrOff(void);
uint32_t pwrPressed(void); uint32_t pwrPressed(void);
uint32_t pwrPressedDuration(void); uint32_t pwrPressedDuration(void);
#endif #endif
#define UNEXPECTED_SHUTDOWN() (g_eeGeneral.unexpectedShutdown) #define UNEXPECTED_SHUTDOWN() (g_eeGeneral.unexpectedShutdown)
// Backlight driver // Backlight driver
#if defined(REVPLUS) #if defined(REVPLUS)

49
radio/src/targets/taranis/pulses_driver.cpp
View file

@ -40,11 +40,6 @@ void setupPulses(unsigned int port);
void setupPulsesPPM(unsigned int port); void setupPulsesPPM(unsigned int port);
void setupPulsesPXX(unsigned int port); void setupPulsesPXX(unsigned int port);
uint16_t *ppmStreamPtr[NUM_MODULES];
extern uint16_t ppmStream[NUM_MODULES+1][20];
extern uint16_t pxxStream[NUM_MODULES][400];
extern uint16_t dsm2Stream[400];
static void init_pa10_pxx( void ) ; static void init_pa10_pxx( void ) ;
static void disable_pa10_pxx( void ) ; static void disable_pa10_pxx( void ) ;
#if defined(TARANIS_INTERNAL_PPM) #if defined(TARANIS_INTERNAL_PPM)
@ -272,7 +267,7 @@ static void init_pa10_pxx()
TIM1->CR2 = TIM_CR2_OIS3 ; // O/P idle high TIM1->CR2 = TIM_CR2_OIS3 ; // O/P idle high
TIM1->BDTR = TIM_BDTR_MOE ; // Enable outputs TIM1->BDTR = TIM_BDTR_MOE ; // Enable outputs
TIM1->CCR3 = pxxStream[INTERNAL_MODULE][0]; TIM1->CCR3 = modulePulsesData[INTERNAL_MODULE].pxx.pulses[0];
TIM1->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0 ; // Force O/P high TIM1->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0 ; // Force O/P high
TIM1->EGR = 1 ; // Restart TIM1->EGR = 1 ; // Restart
@ -288,7 +283,7 @@ static void init_pa10_pxx()
DMA2_Stream6->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 DMA2_Stream6->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ; | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
DMA2_Stream6->PAR = CONVERT_PTR_UINT(&TIM1->DMAR); DMA2_Stream6->PAR = CONVERT_PTR_UINT(&TIM1->DMAR);
DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&pxxStream[INTERNAL_MODULE][1]); DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&modulePulsesData[INTERNAL_MODULE].pxx.pulses[1]);
// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ; // DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
// DMA2_Stream2->NDTR = 100 ; // DMA2_Stream2->NDTR = 100 ;
DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA
@ -318,7 +313,7 @@ static void init_pa10_ppm()
{ {
INTERNAL_MODULE_ON(); INTERNAL_MODULE_ON();
// Timer1 // Timer1
ppmStreamPtr[INTERNAL_MODULE] = ppmStream[INTERNAL_MODULE]; modulePulsesData[INTERNAL_MODULE].ppm.ptr = modulePulsesData[INTERNAL_MODULE].ppm.pulses;
//RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock //RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_INTPPM, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_INTPPM, ENABLE);
@ -332,7 +327,7 @@ static void init_pa10_ppm()
// so it has to be called after the peripheral is enabled // so it has to be called after the peripheral is enabled
setupPulsesPPM(INTERNAL_MODULE) ; setupPulsesPPM(INTERNAL_MODULE) ;
TIM1->ARR = *ppmStreamPtr[INTERNAL_MODULE]++ ; TIM1->ARR = *modulePulsesData[INTERNAL_MODULE].ppm.ptr++ ;
TIM1->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz TIM1->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
TIM1->CCER = TIM_CCER_CC3E ; TIM1->CCER = TIM_CCER_CC3E ;
@ -377,13 +372,13 @@ extern "C" void TIM1_CC_IRQHandler()
if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) { if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits
DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&pxxStream[INTERNAL_MODULE][1]); DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&modulePulsesData[INTERNAL_MODULE].pxx.pulses[1]);
DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA
TIM1->CCR3 = pxxStream[INTERNAL_MODULE][0]; TIM1->CCR3 = modulePulsesData[INTERNAL_MODULE].pxx.pulses[0];
TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
} }
else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) { else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) {
ppmStreamPtr[INTERNAL_MODULE] = ppmStream[INTERNAL_MODULE]; modulePulsesData[INTERNAL_MODULE].ppm.ptr = modulePulsesData[INTERNAL_MODULE].ppm.pulses;
TIM1->DIER |= TIM_DIER_UDE ; TIM1->DIER |= TIM_DIER_UDE ;
TIM1->SR &= ~TIM_SR_UIF ; // Clear this flag TIM1->SR &= ~TIM_SR_UIF ; // Clear this flag
TIM1->DIER |= TIM_DIER_UIE ; // Enable this interrupt TIM1->DIER |= TIM_DIER_UIE ; // Enable this interrupt
@ -397,8 +392,8 @@ extern "C" void TIM1_UP_TIM10_IRQHandler()
{ {
TIM1->SR &= ~TIM_SR_UIF ; // Clear flag TIM1->SR &= ~TIM_SR_UIF ; // Clear flag
TIM1->ARR = *ppmStreamPtr[INTERNAL_MODULE]++ ; TIM1->ARR = *modulePulsesData[INTERNAL_MODULE].ppm.ptr++ ;
if ( *ppmStreamPtr[INTERNAL_MODULE] == 0 ) if ( *modulePulsesData[INTERNAL_MODULE].ppm.ptr == 0 )
{ {
TIM1->SR &= ~TIM_SR_CC2IF ; // Clear this flag TIM1->SR &= ~TIM_SR_CC2IF ; // Clear this flag
TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
@ -433,7 +428,7 @@ void init_pa7_pxx()
TIM8->CCER = TIM_CCER_CC1NE ; TIM8->CCER = TIM_CCER_CC1NE ;
TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high
TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs
TIM8->CCR1 = pxxStream[EXTERNAL_MODULE][0] ; TIM8->CCR1 = modulePulsesData[EXTERNAL_MODULE].pxx.pulses[0];
TIM8->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high TIM8->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
TIM8->EGR = 1 ; // Restart TIM8->EGR = 1 ; // Restart
@ -449,7 +444,7 @@ void init_pa7_pxx()
DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ; | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
DMA2_Stream2->PAR = CONVERT_PTR_UINT(&TIM8->DMAR); DMA2_Stream2->PAR = CONVERT_PTR_UINT(&TIM8->DMAR);
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&pxxStream[EXTERNAL_MODULE][1]); DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].pxx.pulses[1]);
// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ; // DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
// DMA2_Stream2->NDTR = 100 ; // DMA2_Stream2->NDTR = 100 ;
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
@ -501,7 +496,7 @@ static void init_pa7_dsm2()
TIM8->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ; TIM8->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ;
TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high
TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs
TIM8->CCR1 = dsm2Stream[0] ; TIM8->CCR1 = modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[0];
TIM8->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high TIM8->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
TIM8->EGR = 1 ; // Restart TIM8->EGR = 1 ; // Restart
@ -517,7 +512,7 @@ static void init_pa7_dsm2()
DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ; | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
DMA2_Stream2->PAR = CONVERT_PTR_UINT(&TIM8->DMAR); DMA2_Stream2->PAR = CONVERT_PTR_UINT(&TIM8->DMAR);
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&dsm2Stream[1]); DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[1]);
// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ; // DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
// DMA2_Stream2->NDTR = 100 ; // DMA2_Stream2->NDTR = 100 ;
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
@ -550,7 +545,7 @@ static void init_pa7_ppm()
EXTERNAL_MODULE_ON(); EXTERNAL_MODULE_ON();
// Timer1 // Timer1
ppmStreamPtr[EXTERNAL_MODULE] = ppmStream[EXTERNAL_MODULE]; modulePulsesData[EXTERNAL_MODULE].ppm.ptr = modulePulsesData[EXTERNAL_MODULE].ppm.pulses;
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
configure_pins( PIN_EXTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_3 | PIN_OS25) ; configure_pins( PIN_EXTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_3 | PIN_OS25) ;
@ -561,7 +556,7 @@ static void init_pa7_ppm()
// so it has to be called after the peripheral is enabled // so it has to be called after the peripheral is enabled
setupPulsesPPM(EXTERNAL_MODULE) ; setupPulsesPPM(EXTERNAL_MODULE) ;
TIM8->ARR = *ppmStreamPtr[EXTERNAL_MODULE]++ ; TIM8->ARR = *modulePulsesData[EXTERNAL_MODULE].ppm.ptr++ ;
TIM8->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz TIM8->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE ; // PWM mode 1 TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE ; // PWM mode 1
@ -603,23 +598,23 @@ extern "C" void TIM8_CC_IRQHandler()
if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) { if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) {
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&pxxStream[EXTERNAL_MODULE][1]); DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].pxx.pulses[1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
TIM8->CCR1 = pxxStream[EXTERNAL_MODULE][0]; TIM8->CCR1 = modulePulsesData[EXTERNAL_MODULE].pxx.pulses[0];
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
} }
#if defined(DSM2) #if defined(DSM2)
else if (s_current_protocol[EXTERNAL_MODULE] >= PROTO_DSM2_LP45 && s_current_protocol[EXTERNAL_MODULE] <= PROTO_DSM2_DSMX) { else if (s_current_protocol[EXTERNAL_MODULE] >= PROTO_DSM2_LP45 && s_current_protocol[EXTERNAL_MODULE] <= PROTO_DSM2_DSMX) {
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&dsm2Stream[1]); DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
TIM8->CCR1 = dsm2Stream[0]; TIM8->CCR1 = modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[0];
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
} }
#endif #endif
else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) { else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) {
ppmStreamPtr[EXTERNAL_MODULE] = ppmStream[EXTERNAL_MODULE]; modulePulsesData[EXTERNAL_MODULE].ppm.ptr = modulePulsesData[EXTERNAL_MODULE].ppm.pulses;
TIM8->DIER |= TIM_DIER_UDE ; TIM8->DIER |= TIM_DIER_UDE ;
TIM8->SR &= ~TIM_SR_UIF ; // Clear this flag TIM8->SR &= ~TIM_SR_UIF ; // Clear this flag
TIM8->DIER |= TIM_DIER_UIE ; // Enable this interrupt TIM8->DIER |= TIM_DIER_UIE ; // Enable this interrupt
@ -633,8 +628,8 @@ extern "C" void TIM8_UP_TIM13_IRQHandler()
{ {
TIM8->SR &= ~TIM_SR_UIF ; // Clear flag TIM8->SR &= ~TIM_SR_UIF ; // Clear flag
TIM8->ARR = *ppmStreamPtr[EXTERNAL_MODULE]++ ; TIM8->ARR = *modulePulsesData[EXTERNAL_MODULE].ppm.ptr++ ;
if (*ppmStreamPtr[EXTERNAL_MODULE] == 0) { if (*modulePulsesData[EXTERNAL_MODULE].ppm.ptr == 0) {
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear this flag TIM8->SR &= ~TIM_SR_CC2IF ; // Clear this flag
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
} }

12
radio/src/targets/taranis/trainer_driver.cpp
View file

@ -36,8 +36,6 @@
#include "../../opentx.h" #include "../../opentx.h"
uint16_t * TrainerPulsePtr;
extern uint16_t ppmStream[NUM_MODULES+1][20];
extern Fifo<32> sbusFifo; extern Fifo<32> sbusFifo;
#define setupTrainerPulses() setupPulsesPPM(TRAINER_MODULE) #define setupTrainerPulses() setupPulsesPPM(TRAINER_MODULE)
@ -45,7 +43,7 @@ extern Fifo<32> sbusFifo;
// Trainer PPM oputput PC9, Timer 3 channel 4, (Alternate Function 2) // Trainer PPM oputput PC9, Timer 3 channel 4, (Alternate Function 2)
void init_trainer_ppm() void init_trainer_ppm()
{ {
TrainerPulsePtr = ppmStream[TRAINER_MODULE]; trainerPulsesData.ppm.ptr = trainerPulsesData.ppm.pulses;
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN ; // Enable portC clock RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN ; // Enable portC clock
configure_pins( PIN_TR_PPM_OUT, PIN_PERIPHERAL | PIN_PORTC | PIN_PER_2 | PIN_OS25) ; configure_pins( PIN_TR_PPM_OUT, PIN_PERIPHERAL | PIN_PORTC | PIN_PER_2 | PIN_OS25) ;
@ -57,7 +55,7 @@ void init_trainer_ppm()
// so it has to be called after the peripheral is enabled // so it has to be called after the peripheral is enabled
setupTrainerPulses() ; setupTrainerPulses() ;
TIM3->ARR = *TrainerPulsePtr++ ; TIM3->ARR = *trainerPulsesData.ppm.ptr++ ;
TIM3->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 2000000 - 1 ; // 0.5uS TIM3->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 2000000 - 1 ; // 0.5uS
TIM3->CCMR2 = TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4PE ; // PWM mode 1 TIM3->CCMR2 = TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4PE ; // PWM mode 1
TIM3->BDTR = TIM_BDTR_MOE ; TIM3->BDTR = TIM_BDTR_MOE ;
@ -174,7 +172,7 @@ extern "C" void TIM3_IRQHandler()
setupTrainerPulses() ; setupTrainerPulses() ;
TrainerPulsePtr = ppmStream[TRAINER_MODULE]; trainerPulsesData.ppm.ptr = trainerPulsesData.ppm.pulses;
TIM3->DIER |= TIM_DIER_UDE ; TIM3->DIER |= TIM_DIER_UDE ;
TIM3->SR &= ~TIM_SR_UIF ; // Clear this flag TIM3->SR &= ~TIM_SR_UIF ; // Clear this flag
TIM3->DIER |= TIM_DIER_UIE ; // Enable this interrupt TIM3->DIER |= TIM_DIER_UIE ; // Enable this interrupt
@ -183,8 +181,8 @@ extern "C" void TIM3_IRQHandler()
// PPM out update interrupt // PPM out update interrupt
if ( (TIM3->DIER & TIM_DIER_UIE) && ( TIM3->SR & TIM_SR_UIF ) ) { if ( (TIM3->DIER & TIM_DIER_UIE) && ( TIM3->SR & TIM_SR_UIF ) ) {
TIM3->SR &= ~TIM_SR_UIF ; // Clear flag TIM3->SR &= ~TIM_SR_UIF ; // Clear flag
TIM3->ARR = *TrainerPulsePtr++ ; TIM3->ARR = *trainerPulsesData.ppm.ptr++ ;
if ( *TrainerPulsePtr == 0 ) { if ( *trainerPulsesData.ppm.ptr == 0 ) {
TIM3->SR &= ~TIM_SR_CC1IF ; // Clear this flag TIM3->SR &= ~TIM_SR_CC1IF ; // Clear this flag
TIM3->DIER |= TIM_DIER_CC1IE ; // Enable this interrupt TIM3->DIER |= TIM_DIER_CC1IE ; // Enable this interrupt
} }