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sync external module (SBUS, DSM, MULTI)
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parent
fe6bd01afe
commit
ca60468f12
6 changed files with 35 additions and 22 deletions
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@ -76,7 +76,6 @@ void _send_1(uint8_t v)
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*extmodulePulsesData.dsm2.ptr++ = v - 1;
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*extmodulePulsesData.dsm2.ptr++ = v - 1;
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extmodulePulsesData.dsm2.index += 1;
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extmodulePulsesData.dsm2.index += 1;
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extmodulePulsesData.dsm2.rest -= v;
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}
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}
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void sendByteDsm2(uint8_t b) // max 10 changes 0 10 10 10 10 1
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void sendByteDsm2(uint8_t b) // max 10 changes 0 10 10 10 10 1
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@ -101,9 +100,9 @@ void sendByteDsm2(uint8_t b) // max 10 changes 0 10 10 10 10 1
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void putDsm2Flush()
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void putDsm2Flush()
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{
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{
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if (extmodulePulsesData.dsm2.index & 1)
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if (extmodulePulsesData.dsm2.index & 1)
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*extmodulePulsesData.dsm2.ptr++ = extmodulePulsesData.dsm2.rest;
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*extmodulePulsesData.dsm2.ptr++ = 60000;
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else
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else
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*(extmodulePulsesData.dsm2.ptr - 1) = extmodulePulsesData.dsm2.rest;
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*(extmodulePulsesData.dsm2.ptr - 1) = 60000;
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}
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}
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#endif
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#endif
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@ -119,7 +118,6 @@ void setupPulsesDSM2()
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extmodulePulsesData.dsm2.serialBitCount = 0 ;
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extmodulePulsesData.dsm2.serialBitCount = 0 ;
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#else
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#else
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extmodulePulsesData.dsm2.index = 0;
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extmodulePulsesData.dsm2.index = 0;
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extmodulePulsesData.dsm2.rest = DSM2_PERIOD * 2000;
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#endif
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#endif
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extmodulePulsesData.dsm2.ptr = extmodulePulsesData.dsm2.pulses;
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extmodulePulsesData.dsm2.ptr = extmodulePulsesData.dsm2.pulses;
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@ -200,10 +200,8 @@ void setupPulsesMultiExternalModule()
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extmodulePulsesData.dsm2.serialByte = 0 ;
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extmodulePulsesData.dsm2.serialByte = 0 ;
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extmodulePulsesData.dsm2.serialBitCount = 0 ;
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extmodulePulsesData.dsm2.serialBitCount = 0 ;
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#else
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#else
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extmodulePulsesData.dsm2.rest = getMultiSyncStatus(EXTERNAL_MODULE).getAdjustedRefreshRate();
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extmodulePulsesData.dsm2.index = 0;
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extmodulePulsesData.dsm2.index = 0;
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#endif
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#endif
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extmodulePulsesData.dsm2.ptr = extmodulePulsesData.dsm2.pulses;
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extmodulePulsesData.dsm2.ptr = extmodulePulsesData.dsm2.pulses;
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setupPulsesMulti(EXTERNAL_MODULE);
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setupPulsesMulti(EXTERNAL_MODULE);
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@ -226,7 +226,6 @@ typedef Dsm2SerialPulsesData Dsm2PulsesData;
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PACK(struct Dsm2TimerPulsesData {
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PACK(struct Dsm2TimerPulsesData {
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pulse_duration_t pulses[MAX_PULSES_TRANSITIONS];
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pulse_duration_t pulses[MAX_PULSES_TRANSITIONS];
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pulse_duration_t * ptr;
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pulse_duration_t * ptr;
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uint16_t rest;
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uint8_t index;
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uint8_t index;
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});
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});
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typedef Dsm2TimerPulsesData Dsm2PulsesData;
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typedef Dsm2TimerPulsesData Dsm2PulsesData;
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@ -55,7 +55,6 @@ static void _send_level(uint8_t v)
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*extmodulePulsesData.dsm2.ptr++ = v - 1;
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*extmodulePulsesData.dsm2.ptr++ = v - 1;
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extmodulePulsesData.dsm2.index+=1;
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extmodulePulsesData.dsm2.index+=1;
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extmodulePulsesData.dsm2.rest -=v;
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}
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}
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void sendByteSbus(uint8_t b) // max 11 changes 0 10 10 10 10 P 1
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void sendByteSbus(uint8_t b) // max 11 changes 0 10 10 10 10 P 1
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@ -113,7 +112,6 @@ void setupPulsesSbus()
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extmodulePulsesData.dsm2.serialByte = 0;
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extmodulePulsesData.dsm2.serialByte = 0;
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extmodulePulsesData.dsm2.serialBitCount = 0;
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extmodulePulsesData.dsm2.serialBitCount = 0;
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#else
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#else
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extmodulePulsesData.dsm2.rest = SBUS_PERIOD_HALF_US;
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extmodulePulsesData.dsm2.index = 0;
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extmodulePulsesData.dsm2.index = 0;
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#endif
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#endif
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@ -179,7 +179,7 @@ void extmoduleSerialStart(uint32_t /*baudrate*/, uint32_t period_half_us, bool i
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EXTMODULE_TIMER->ARR = period_half_us;
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EXTMODULE_TIMER->ARR = period_half_us;
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EXTMODULE_TIMER->CCR2 = period_half_us - 4000;
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EXTMODULE_TIMER->CCR2 = period_half_us - 4000;
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EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
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EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
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EXTMODULE_TIMER->DIER |= TIM_DIER_UDE | TIM_DIER_CC2IE;
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EXTMODULE_TIMER->DIER |= TIM_DIER_UDE;
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EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
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EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
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NVIC_EnableIRQ(EXTMODULE_TIMER_DMA_STREAM_IRQn);
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NVIC_EnableIRQ(EXTMODULE_TIMER_DMA_STREAM_IRQn);
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@ -318,23 +318,36 @@ void extmoduleSendNextFrame()
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#if defined(DSM2)
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#if defined(DSM2)
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case PROTOCOL_CHANNELS_SBUS:
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case PROTOCOL_CHANNELS_SBUS:
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#if defined(PCBX10) || PCBREV >= 13
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EXTMODULE_TIMER->CCER = TIM_CCER_CC3E | (GET_SBUS_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC3P : 0); // reverse polarity for Sbus if needed
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#else
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EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | (GET_SBUS_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1P : 0); // reverse polarity for Sbus if needed
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#endif
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// no break
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case PROTOCOL_CHANNELS_DSM2_LP45:
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case PROTOCOL_CHANNELS_DSM2_LP45:
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case PROTOCOL_CHANNELS_DSM2_DSM2:
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case PROTOCOL_CHANNELS_DSM2_DSM2:
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case PROTOCOL_CHANNELS_DSM2_DSMX:
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case PROTOCOL_CHANNELS_DSM2_DSMX:
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case PROTOCOL_CHANNELS_MULTIMODULE:
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case PROTOCOL_CHANNELS_MULTIMODULE:
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EXTMODULE_TIMER->CCR2 = *(extmodulePulsesData.dsm2.ptr - 1) - 4000; // 2mS in advance
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if (EXTMODULE_TIMER_DMA_STREAM->CR & DMA_SxCR_EN)
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return;
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if (PROTOCOL_CHANNELS_SBUS == moduleState[EXTERNAL_MODULE].protocol) {
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#if defined(PCBX10) || PCBREV >= 13
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EXTMODULE_TIMER->CCER = TIM_CCER_CC3E | (GET_SBUS_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC3P : 0); // reverse polarity for Sbus if needed
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#else
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EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | (GET_SBUS_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1P : 0); // reverse polarity for Sbus if needed
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#endif
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}
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// disable timer
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EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
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// send DMA request
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EXTMODULE_TIMER_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA
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EXTMODULE_TIMER_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA
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EXTMODULE_TIMER_DMA_STREAM->CR |= EXTMODULE_TIMER_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | EXTMODULE_TIMER_DMA_SIZE | DMA_SxCR_PL_0 | DMA_SxCR_PL_1;
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EXTMODULE_TIMER_DMA_STREAM->CR |= EXTMODULE_TIMER_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | EXTMODULE_TIMER_DMA_SIZE | DMA_SxCR_PL_0 | DMA_SxCR_PL_1;
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EXTMODULE_TIMER_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR);
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EXTMODULE_TIMER_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR);
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EXTMODULE_TIMER_DMA_STREAM->M0AR = CONVERT_PTR_UINT(extmodulePulsesData.dsm2.pulses);
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EXTMODULE_TIMER_DMA_STREAM->M0AR = CONVERT_PTR_UINT(extmodulePulsesData.dsm2.pulses);
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EXTMODULE_TIMER_DMA_STREAM->NDTR = extmodulePulsesData.dsm2.ptr - extmodulePulsesData.dsm2.pulses;
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EXTMODULE_TIMER_DMA_STREAM->NDTR = extmodulePulsesData.dsm2.ptr - extmodulePulsesData.dsm2.pulses;
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EXTMODULE_TIMER_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA
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EXTMODULE_TIMER_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA
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// re-init timer
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EXTMODULE_TIMER->EGR = 1;
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EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
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break;
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break;
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#endif
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#endif
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@ -390,13 +403,13 @@ extern "C" void EXTMODULE_TIMER_DMA_IRQHandler()
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DMA_ClearITPendingBit(EXTMODULE_TIMER_DMA_STREAM, EXTMODULE_TIMER_DMA_FLAG_TC);
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DMA_ClearITPendingBit(EXTMODULE_TIMER_DMA_STREAM, EXTMODULE_TIMER_DMA_FLAG_TC);
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EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
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EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
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EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
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//EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
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}
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}
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extern "C" void EXTMODULE_TIMER_IRQHandler()
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extern "C" void EXTMODULE_TIMER_IRQHandler()
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{
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{
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EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // Stop this interrupt
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EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // Stop this interrupt
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EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF;
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EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF;
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if (setupPulsesExternalModule())
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// if (setupPulsesExternalModule())
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extmoduleSendNextFrame();
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// extmoduleSendNextFrame();
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}
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}
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@ -87,6 +87,12 @@ bool isModuleSynchronous(uint8_t module)
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#endif
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#endif
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#if defined(INTMODULE_USART) || defined(EXTMODULE_USART)
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#if defined(INTMODULE_USART) || defined(EXTMODULE_USART)
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case PROTOCOL_CHANNELS_PXX1_SERIAL:
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case PROTOCOL_CHANNELS_PXX1_SERIAL:
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#endif
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#if defined(DSM2)
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case PROTOCOL_CHANNELS_SBUS:
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case PROTOCOL_CHANNELS_DSM2_LP45:
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case PROTOCOL_CHANNELS_DSM2_DSM2:
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case PROTOCOL_CHANNELS_DSM2_DSMX:
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#endif
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#endif
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return true;
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return true;
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}
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}
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@ -108,7 +114,7 @@ void sendSynchronousPulses()
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}
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}
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}
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}
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#define DEBUG_MIXER_SCHEDULER
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//#define DEBUG_MIXER_SCHEDULER
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uint32_t nextMixerTime[NUM_MODULES];
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uint32_t nextMixerTime[NUM_MODULES];
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@ -194,6 +200,7 @@ TASK_FUNCTION(mixerTask)
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if (t0 > maxMixerDuration)
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if (t0 > maxMixerDuration)
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maxMixerDuration = t0;
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maxMixerDuration = t0;
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serialPrint("cnt = %d", EXTMODULE_TIMER->CNT);
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sendSynchronousPulses();
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sendSynchronousPulses();
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}
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}
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}
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}
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