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linux-postmarketos-qcom-sc7180: Update maintainer, bump to newest LTS

Browse source 
Jenneron sent me his Trogdor/Lazor (Acer Chromebook Spin 513-1H) nearly
a year ago, as he doesn't have time to work on it anymore... I didn't
have time to do it either (until now).

I updated maintainer to myself, removed patches that have been merged
and bumped the kernel to newest LTS as of today.

Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Part-of: https://gitlab.postmarketos.org/postmarketOS/pmaports/-/merge_requests/6740
[ci:skip-build]: already built successfully in CI
This commit is contained in:
Alicja Michalska 2025-07-03 21:07:11 +02:00 • committed by Alicja Michalska
parent 3620e3713e
commit 6eb947d2e0
No known key found for this signature in database
GPG key ID: 5AE7F5513E0885CB
13 changed files with 486 additions and 1969 deletions
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32
device/community/linux-postmarketos-qcom-sc7180/0001-remoteproc-qcom-pas-Add-sc7180-adsp.patch
View file

@ -1,32 +0,0 @@
From 46ee4de1b5c5099e937ffa0dc044390e4455c3b3 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Thu, 7 Sep 2023 15:02:35 +0500
Subject: [PATCH 1/8] remoteproc: qcom: pas: Add sc7180 adsp
sc7180 has a dedicated ADSP similar to the one found in sm8250.
Add it's compatible to the driver reusing the existing config so
the devices that use the adsp can probe it.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20230907-sc7180-adsp-rproc-v3-2-6515c3fbe0a3@trvn.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
drivers/remoteproc/qcom_q6v5_pas.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index b5447dd2dd35..55fafc68200e 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -1161,6 +1161,7 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
+ { .compatible = "qcom,sc7180-adsp-pas", .data = &sm8250_adsp_resource},
{ .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init},
{ .compatible = "qcom,sc7280-mpss-pas", .data = &mpss_resource_init},
{ .compatible = "qcom,sc8180x-adsp-pas", .data = &sm8150_adsp_resource},
--
2.43.2

37
device/community/linux-postmarketos-qcom-sc7180/0002-arm64-dts-qcom-sc7180-Add-tertiary-mi2s-pinctrl.patch
View file

@ -1,37 +0,0 @@
From f997651c8dbcdbff191306117c4d4339d09e0924 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Thu, 7 Sep 2023 15:02:36 +0500
Subject: [PATCH 2/8] arm64: dts: qcom: sc7180: Add tertiary mi2s pinctrl
Some devices use tertiary mi2s to connect external audio codec.
Add it near the other two i2s pinctrl definitions so the devices don't
have to duplicate it.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230907-sc7180-adsp-rproc-v3-3-6515c3fbe0a3@trvn.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index f7c528ecb224..db5d04181ac4 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2042,6 +2042,11 @@ pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
pins = "gpio57";
function = "lpass_ext";
};
+
+ ter_mi2s_active: ter-mi2s-active-state {
+ pins = "gpio63", "gpio64", "gpio65", "gpio66";
+ function = "mi2s_2";
+ };
};
remoteproc_mpss: remoteproc@4080000 {
--
2.43.2

162
device/community/linux-postmarketos-qcom-sc7180/0003-arm64-dts-qcom-sc7180-Add-ADSP.patch
View file

@ -1,162 +0,0 @@
From 419d22eeba6b335ba58d8dd9d064b871a37cb1fb Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Thu, 7 Sep 2023 15:02:37 +0500
Subject: [PATCH 3/8] arm64: dts: qcom: sc7180: Add ADSP
sc7180 has an ADSP remoteproc that exclusively controls the audio
hardware on devices that use Qualcomm firmware.
Add it along with the relevant audio services.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20230907-sc7180-adsp-rproc-v3-4-6515c3fbe0a3@trvn.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 122 +++++++++++++++++++++++++++
1 file changed, 122 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index db5d04181ac4..3683419ee8f5 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -20,6 +20,8 @@
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/soc/qcom,apr.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -3781,6 +3783,126 @@ wifi: wifi@18800000 {
status = "disabled";
};
+ remoteproc_adsp: remoteproc@62400000 {
+ compatible = "qcom,sc7180-adsp-pas";
+ reg = <0 0x62400000 0 0x100>;
+
+ interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SC7180_LCX>,
+ <&rpmhpd SC7180_LMX>;
+ power-domain-names = "lcx", "lmx";
+
+ qcom,qmp = <&aoss_qmp>;
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+ label = "lpass";
+ qcom,remote-pid = <2>;
+ mboxes = <&apss_shared 8>;
+
+ apr {
+ compatible = "qcom,apr-v2";
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,domain = <APR_DOMAIN_ADSP>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ service@3 {
+ compatible = "qcom,q6core";
+ reg = <APR_SVC_ADSP_CORE>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+ };
+
+ q6afe: service@4 {
+ compatible = "qcom,q6afe";
+ reg = <APR_SVC_AFE>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ q6afedai: dais {
+ compatible = "qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+
+ q6afecc: clock-controller {
+ compatible = "qcom,q6afe-clocks";
+ #clock-cells = <2>;
+ };
+ };
+
+ q6asm: service@7 {
+ compatible = "qcom,q6asm";
+ reg = <APR_SVC_ASM>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ q6asmdai: dais {
+ compatible = "qcom,q6asm-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ iommus = <&apps_smmu 0x1001 0x0>;
+ };
+ };
+
+ q6adm: service@8 {
+ compatible = "qcom,q6adm";
+ reg = <APR_SVC_ADM>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ q6routing: routing {
+ compatible = "qcom,q6adm-routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x1003 0x0>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x1004 0x0>;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x1005 0x0>;
+ qcom,nsessions = <5>;
+ };
+ };
+ };
+ };
+
lpasscc: clock-controller@62d00000 {
compatible = "qcom,sc7180-lpasscorecc";
reg = <0 0x62d00000 0 0x50000>,
--
2.43.2

324
device/community/linux-postmarketos-qcom-sc7180/0004-ASoC-qcom-sc7180-Add-support-for-qdsp6-baked-sound.patch
View file

@ -1,324 +0,0 @@
From 86b2a5a727c07a83acea7946a132dddc27549299 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Fri, 20 Oct 2023 20:33:47 +0500
Subject: [PATCH 4/8] ASoC: qcom: sc7180: Add support for qdsp6 baked sound
Some sc7180 devices use audio adsp to play sound. The setup for this
adsp is similar to the dirrect lpass usage but requires the use of
different link ids and clocks.
This commit adds support for the qdsp based audio, reusing the common
parts like audio codec setup and jack creation.
Since the setup is mostly generic and codec specific setup is guarded
behind a check, a generic compatible is added, similar to other
platforms. Even though those changes target Acer Aspire 1 as the only
user of the adsp audio on this platform present upstream at the moment
of the commit, those changes should be either dirrectly compatible or
trivially expandable to the other devices that will be added in the
future.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20231020-sc7180-qdsp-sndcard-v1-2-157706b7d06f@trvn.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
---
sound/soc/qcom/sc7180.c | 195 +++++++++++++++++++++++++++++++++++-----
1 file changed, 173 insertions(+), 22 deletions(-)
diff --git a/sound/soc/qcom/sc7180.c b/sound/soc/qcom/sc7180.c
index d1fd40e3f7a9..a198fcda2955 100644
--- a/sound/soc/qcom/sc7180.c
+++ b/sound/soc/qcom/sc7180.c
@@ -5,6 +5,7 @@
// sc7180.c -- ALSA SoC Machine driver for SC7180
#include <dt-bindings/sound/sc7180-lpass.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
@@ -20,8 +21,10 @@
#include "../codecs/rt5682s.h"
#include "common.h"
#include "lpass.h"
+#include "qdsp6/q6afe.h"
#define DEFAULT_MCLK_RATE 19200000
+#define MI2S_BCLK_RATE 1536000
#define RT5682_PLL1_FREQ (48000 * 512)
#define DRIVER_NAME "SC7180"
@@ -134,12 +137,28 @@ static int sc7180_init(struct snd_soc_pcm_runtime *rtd)
return 0;
}
-static int sc7180_snd_startup(struct snd_pcm_substream *substream)
+static int sc7180_qdsp_init(struct snd_soc_pcm_runtime *rtd)
{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_card *card = rtd->card;
- struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+
+ switch (cpu_dai->id) {
+ case PRIMARY_MI2S_RX:
+ return sc7180_headset_init(rtd);
+ case PRIMARY_MI2S_TX:
+ case TERTIARY_MI2S_RX:
+ return 0;
+ case DISPLAY_PORT_RX:
+ return sc7180_hdmi_init(rtd);
+ default:
+ dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
+ cpu_dai->id);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int sc7180_startup_realtek_codec(struct snd_soc_pcm_runtime *rtd)
+{
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
int pll_id, pll_source, pll_in, pll_out, clk_id, ret;
@@ -155,8 +174,40 @@ static int sc7180_snd_startup(struct snd_pcm_substream *substream)
clk_id = RT5682S_SCLK_S_PLL2;
pll_out = RT5682_PLL1_FREQ;
pll_in = DEFAULT_MCLK_RATE;
+ } else {
+ return 0;
+ }
+ snd_soc_dai_set_fmt(codec_dai,
+ SND_SOC_DAIFMT_BC_FC |
+ SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_I2S);
+
+ /* Configure PLL1 for codec */
+ ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source,
+ pll_in, pll_out);
+ if (ret) {
+ dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
+ return ret;
}
+ /* Configure sysclk for codec */
+ ret = snd_soc_dai_set_sysclk(codec_dai, clk_id, pll_out,
+ SND_SOC_CLOCK_IN);
+ if (ret)
+ dev_err(rtd->dev, "snd_soc_dai_set_sysclk err = %d\n",
+ ret);
+
+ return ret;
+}
+
+static int sc7180_snd_startup(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_card *card = rtd->card;
+ struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+ int ret;
+
switch (cpu_dai->id) {
case MI2S_PRIMARY:
if (++data->pri_mi2s_clk_count == 1) {
@@ -166,30 +217,66 @@ static int sc7180_snd_startup(struct snd_pcm_substream *substream)
SNDRV_PCM_STREAM_PLAYBACK);
}
- snd_soc_dai_set_fmt(codec_dai,
- SND_SOC_DAIFMT_BC_FC |
- SND_SOC_DAIFMT_NB_NF |
- SND_SOC_DAIFMT_I2S);
-
- /* Configure PLL1 for codec */
- ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source,
- pll_in, pll_out);
- if (ret) {
- dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
+ ret = sc7180_startup_realtek_codec(rtd);
+ if (ret)
return ret;
+
+ break;
+ case MI2S_SECONDARY:
+ break;
+ case LPASS_DP_RX:
+ break;
+ default:
+ dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
+ cpu_dai->id);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int sc7180_qdsp_snd_startup(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_card *card = rtd->card;
+ struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
+ int ret;
+
+ switch (cpu_dai->id) {
+ case PRIMARY_MI2S_RX:
+ case PRIMARY_MI2S_TX:
+ if (++data->pri_mi2s_clk_count == 1) {
+ snd_soc_dai_set_sysclk(cpu_dai,
+ Q6AFE_LPASS_CLK_ID_MCLK_1,
+ DEFAULT_MCLK_RATE,
+ SNDRV_PCM_STREAM_PLAYBACK);
+ snd_soc_dai_set_sysclk(cpu_dai,
+ Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
+ MI2S_BCLK_RATE,
+ SNDRV_PCM_STREAM_PLAYBACK);
}
- /* Configure sysclk for codec */
- ret = snd_soc_dai_set_sysclk(codec_dai, clk_id, pll_out,
- SND_SOC_CLOCK_IN);
+ snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP);
+
+ ret = sc7180_startup_realtek_codec(rtd);
if (ret)
- dev_err(rtd->dev, "snd_soc_dai_set_sysclk err = %d\n",
- ret);
+ return ret;
break;
- case MI2S_SECONDARY:
+ case TERTIARY_MI2S_RX:
+ snd_soc_dai_set_sysclk(cpu_dai,
+ Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
+ MI2S_BCLK_RATE,
+ SNDRV_PCM_STREAM_PLAYBACK);
+
+ snd_soc_dai_set_fmt(codec_dai,
+ SND_SOC_DAIFMT_BC_FC |
+ SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_I2S);
+ snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP);
break;
- case LPASS_DP_RX:
+ case DISPLAY_PORT_RX:
break;
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
@@ -247,6 +334,42 @@ static void sc7180_snd_shutdown(struct snd_pcm_substream *substream)
}
}
+static void sc7180_qdsp_snd_shutdown(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_card *card = rtd->card;
+ struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+
+ switch (cpu_dai->id) {
+ case PRIMARY_MI2S_RX:
+ case PRIMARY_MI2S_TX:
+ if (--data->pri_mi2s_clk_count == 0) {
+ snd_soc_dai_set_sysclk(cpu_dai,
+ Q6AFE_LPASS_CLK_ID_MCLK_1,
+ 0,
+ SNDRV_PCM_STREAM_PLAYBACK);
+ snd_soc_dai_set_sysclk(cpu_dai,
+ Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
+ 0,
+ SNDRV_PCM_STREAM_PLAYBACK);
+ }
+ break;
+ case TERTIARY_MI2S_RX:
+ snd_soc_dai_set_sysclk(cpu_dai,
+ Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
+ 0,
+ SNDRV_PCM_STREAM_PLAYBACK);
+ break;
+ case DISPLAY_PORT_RX:
+ break;
+ default:
+ dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
+ cpu_dai->id);
+ break;
+ }
+}
+
static int sc7180_adau7002_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
@@ -295,11 +418,30 @@ static int sc7180_adau7002_snd_startup(struct snd_pcm_substream *substream)
return 0;
}
+static int sc7180_qdsp_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_interval *rate = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_RATE);
+ struct snd_interval *channels = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_CHANNELS);
+
+ rate->min = rate->max = 48000;
+ channels->min = channels->max = 2;
+
+ return 0;
+}
+
static const struct snd_soc_ops sc7180_ops = {
.startup = sc7180_snd_startup,
.shutdown = sc7180_snd_shutdown,
};
+static const struct snd_soc_ops sc7180_qdsp_ops = {
+ .startup = sc7180_qdsp_snd_startup,
+ .shutdown = sc7180_qdsp_snd_shutdown,
+};
+
static const struct snd_soc_ops sc7180_adau7002_ops = {
.startup = sc7180_adau7002_snd_startup,
};
@@ -355,7 +497,7 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
struct snd_soc_dai_link *link;
int ret;
int i;
- bool no_headphone = false;
+ bool qdsp = false, no_headphone = false;
/* Allocate the private data */
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
@@ -391,6 +533,8 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
no_headphone = true;
card->dapm_widgets = sc7180_adau7002_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sc7180_adau7002_snd_widgets);
+ } else if (of_device_is_compatible(dev->of_node, "qcom,sc7180-qdsp6-sndcard")) {
+ qdsp = true;
}
ret = qcom_snd_parse_of(card);
@@ -401,6 +545,12 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
if (no_headphone) {
link->ops = &sc7180_adau7002_ops;
link->init = sc7180_adau7002_init;
+ } else if (qdsp) {
+ if (link->no_pcm == 1) {
+ link->ops = &sc7180_qdsp_ops;
+ link->be_hw_params_fixup = sc7180_qdsp_be_hw_params_fixup;
+ link->init = sc7180_qdsp_init;
+ }
} else {
link->ops = &sc7180_ops;
link->init = sc7180_init;
@@ -413,6 +563,7 @@ static int sc7180_snd_platform_probe(struct platform_device *pdev)
static const struct of_device_id sc7180_snd_device_id[] = {
{.compatible = "google,sc7180-trogdor"},
{.compatible = "google,sc7180-coachz"},
+ {.compatible = "qcom,sc7180-qdsp6-sndcard"},
{},
};
MODULE_DEVICE_TABLE(of, sc7180_snd_device_id);
--
2.43.2

54
device/community/linux-postmarketos-qcom-sc7180/0005-arm64-dts-qcom-pm6150-Add-resin-and-rtc-nodes.patch
View file

@ -1,54 +0,0 @@
From 18dfe3c57801796fb6ca2a17f63893e48298eaa4 Mon Sep 17 00:00:00 2001
From: David Wronek <davidwronek@gmail.com>
Date: Thu, 24 Aug 2023 11:15:05 +0200
Subject: [PATCH 5/8] arm64: dts: qcom: pm6150: Add resin and rtc nodes
Add support for the RTC which is the same as on other PMICs and add the
resin child node to the PM6150 PON device, both disabled by default.
Signed-off-by: David Wronek <davidwronek@gmail.com>
Tested-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230824091737.75813-3-davidwronek@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/pm6150.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi
index 7d4d1f2767ed..ddbaf7280b03 100644
--- a/arch/arm64/boot/dts/qcom/pm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
@@ -53,6 +53,14 @@ pm6150_pwrkey: pwrkey {
bias-pull-up;
linux,code = <KEY_POWER>;
};
+
+ pm6150_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ status = "disabled";
+ };
};
pm6150_temp: temp-alarm@2400 {
@@ -88,6 +96,14 @@ pm6150_adc_tm: adc-tm@3500 {
status = "disabled";
};
+ pm6150_rtc: rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>, <0x6100>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
pm6150_gpios: gpio@c000 {
compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
--
2.43.2

34
device/community/linux-postmarketos-qcom-sc7180/0006-arm64-dts-qcom-acer-aspire1-Enable-RTC.patch
View file

@ -1,34 +0,0 @@
From 2384f0140ed50ef2ee57fd575e69dc91fe13652b Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Tue, 5 Dec 2023 16:48:10 +0500
Subject: [PATCH 6/8] arm64: dts: qcom: acer-aspire1: Enable RTC
pm6150 has a read-only RTC that can be used to keep the time with some
extra userspace tools. Enable it.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20231205-aspire1-sound-v2-1-443b7ac0a06f@trvn.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
index 3342cb048038..00b442696618 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
@@ -364,6 +364,10 @@ &pm6150_pon {
status = "disabled";
};
+&pm6150_rtc {
+ status = "okay";
+};
+
&qupv3_id_0 {
status = "okay";
};
--
2.43.2

212
device/community/linux-postmarketos-qcom-sc7180/0007-arm64-dts-qcom-acer-aspire1-Add-sound.patch
View file

@ -1,212 +0,0 @@
From bf688cd32b158a962bbce6103b3f43dda5d80a5a Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Tue, 5 Dec 2023 16:48:12 +0500
Subject: [PATCH 7/8] arm64: dts: qcom: acer-aspire1: Add sound
This laptop has two i2s speakers; an i2s audio codec for the headset
jack; two DMIC microphones in the lid and the displayport audio channel.
This commit adds the audio node that describes all of the above with the
exception of the DMICs that require in-SoC digital codec to be brought
up, which will be done later.
Note that the displayport channel is connected here for completeness,
but the displayport can't be used yet since the HPD signal is created by
the embedded controller, which will be added later.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20231205-aspire1-sound-v2-3-443b7ac0a06f@trvn.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
.../boot/dts/qcom/sc7180-acer-aspire1.dts | 153 ++++++++++++++++++
1 file changed, 153 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
index 00b442696618..5afcb8212f49 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7180.dtsi"
@@ -129,6 +130,113 @@ reg_lcm_3p3: panel-regulator {
pinctrl-names = "default";
};
+ sound: sound {
+ compatible = "qcom,sc7180-qdsp6-sndcard";
+ pinctrl-0 = <&pri_mi2s_active>, <&pri_mi2s_mclk_active>, <&ter_mi2s_active>;
+ pinctrl-names = "default";
+ model = "Acer-Aspire-1";
+
+ audio-routing =
+ "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR";
+
+ multimedia1-dai-link {
+ link-name = "MultiMedia1";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ };
+
+ multimedia2-dai-link {
+ link-name = "MultiMedia2";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
+ };
+ };
+
+ multimedia3-dai-link {
+ link-name = "MultiMedia3";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+ };
+ };
+
+ multimedia4-dai-link {
+ link-name = "MultiMedia4";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>;
+ };
+ };
+
+ primary-rx-dai-link {
+ link-name = "Primary MI2S Playback";
+
+ cpu {
+ sound-dai = <&q6afedai PRIMARY_MI2S_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&alc5682 0>;
+ };
+ };
+
+ primary-tx-dai-link {
+ link-name = "Primary MI2S Capture";
+
+ cpu {
+ sound-dai = <&q6afedai PRIMARY_MI2S_TX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&alc5682 0>;
+ };
+ };
+
+ tertiary-rx-dai-link {
+ link-name = "Tertiary MI2S Playback";
+
+ cpu {
+ sound-dai = <&q6afedai TERTIARY_MI2S_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&max98357a>;
+ };
+ };
+
+ displayport-rx-dai-link {
+ link-name = "DisplayPort Playback";
+
+ cpu {
+ sound-dai = <&q6afedai DISPLAY_PORT_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&mdss_dp>;
+ };
+ };
+ };
+
reg_tp_3p3: touchpad-regulator {
compatible = "regulator-fixed";
regulator-name = "tp_3p3";
@@ -368,6 +476,45 @@ &pm6150_rtc {
status = "okay";
};
+&q6afedai {
+ dai@16 {
+ reg = <PRIMARY_MI2S_RX>;
+ qcom,sd-lines = <1>;
+ };
+
+ dai@17 {
+ reg = <PRIMARY_MI2S_TX>;
+ qcom,sd-lines = <0>;
+ };
+
+ dai@20 {
+ reg = <TERTIARY_MI2S_RX>;
+ qcom,sd-lines = <0>;
+ };
+
+ dai@104 {
+ reg = <DISPLAY_PORT_RX>;
+ };
+};
+
+&q6asmdai {
+ dai@0 {
+ reg = <0>;
+ };
+
+ dai@1 {
+ reg = <1>;
+ };
+
+ dai@2 {
+ reg = <2>;
+ };
+
+ dai@3 {
+ reg = <3>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -376,6 +523,12 @@ &qupv3_id_1 {
status = "okay";
};
+&remoteproc_adsp {
+ memory-region = <&adsp_mem>;
+ firmware-name = "qcom/sc7180/acer/aspire1/qcadsp7180.mbn";
+ status = "okay";
+};
+
&remoteproc_mpss {
firmware-name = "qcom/sc7180/acer/aspire1/qcmpss7180_nm.mbn";
status = "okay";
--
2.43.2

116
device/community/linux-postmarketos-qcom-sc7180/0008-platform-Add-ARM64-platform-directory.patch
View file

@ -1,116 +0,0 @@
From 5da7f1f071d5d0db4978e946263ab783657d0d57 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Sat, 2 Mar 2024 14:37:30 +0500
Subject: [PATCH 08/11] platform: Add ARM64 platform directory
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Some ARM64 based laptops and computers require vendor/board specific
drivers for their embedded controllers. Even though usually the most
important functionality of those devices is implemented inside ACPI,
unfortunately Linux doesn't currently have great support for ACPI on
platforms like Qualcomm Snapdragon that are used in most ARM64 laptops
today. Instead Linux relies on Device Tree for Qualcomm based devices
and it's significantly easier to reimplement the EC functionality in
a dedicated driver than to make use of ACPI code.
This commit introduces a new platform/arm64 subdirectory to give a
place to such drivers for EC-like devices.
A new MAINTAINERS entry is added for this directory. Patches to files in
this directory will be taken up by the platform-drivers-x86 team (i.e.
Hans de Goede and Ilpo Järvinen) with additional review from Bryan
O'Donoghue to represent ARM64 maintainers.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
---
MAINTAINERS | 10 ++++++++++
drivers/platform/Kconfig | 2 ++
drivers/platform/Makefile | 1 +
drivers/platform/arm64/Kconfig | 19 +++++++++++++++++++
drivers/platform/arm64/Makefile | 6 ++++++
5 files changed, 38 insertions(+)
create mode 100644 drivers/platform/arm64/Kconfig
create mode 100644 drivers/platform/arm64/Makefile
diff --git a/MAINTAINERS b/MAINTAINERS
index 40312bb550f0..396be95d4f9a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3007,6 +3007,16 @@ F: drivers/mmc/host/sdhci-of-arasan.c
N: zynq
N: xilinx
+ARM64 PLATFORM DRIVERS
+M: Hans de Goede <hdegoede@redhat.com>
+M: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
+R: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+L: platform-driver-x86@vger.kernel.org
+S: Maintained
+Q: https://patchwork.kernel.org/project/platform-driver-x86/list/
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git
+F: drivers/platform/arm64/
+
ARM64 PORT (AARCH64 ARCHITECTURE)
M: Catalin Marinas <catalin.marinas@arm.com>
M: Will Deacon <will@kernel.org>
diff --git a/drivers/platform/Kconfig b/drivers/platform/Kconfig
index 868b20361769..81a298517df2 100644
--- a/drivers/platform/Kconfig
+++ b/drivers/platform/Kconfig
@@ -14,3 +14,5 @@ source "drivers/platform/olpc/Kconfig"
source "drivers/platform/surface/Kconfig"
source "drivers/platform/x86/Kconfig"
+
+source "drivers/platform/arm64/Kconfig"
diff --git a/drivers/platform/Makefile b/drivers/platform/Makefile
index 41640172975a..fbbe4f77aa5d 100644
--- a/drivers/platform/Makefile
+++ b/drivers/platform/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_OLPC_EC) += olpc/
obj-$(CONFIG_GOLDFISH) += goldfish/
obj-$(CONFIG_CHROME_PLATFORMS) += chrome/
obj-$(CONFIG_SURFACE_PLATFORMS) += surface/
+obj-$(CONFIG_ARM64) += arm64/
diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig
new file mode 100644
index 000000000000..644b83ede093
--- /dev/null
+++ b/drivers/platform/arm64/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# EC-like Drivers for aarch64 based devices.
+#
+
+menuconfig ARM64_PLATFORM_DEVICES
+ bool "ARM64 Platform-Specific Device Drivers"
+ depends on ARM64 || COMPILE_TEST
+ default y
+ help
+ Say Y here to get to see options for platform-specific device drivers
+ for arm64 based devices, primarily EC-like device drivers.
+ This option alone does not add any kernel code.
+
+ If you say N, all options in this submenu will be skipped and disabled.
+
+if ARM64_PLATFORM_DEVICES
+
+endif # ARM64_PLATFORM_DEVICES
diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makefile
new file mode 100644
index 000000000000..f91cdc7155e2
--- /dev/null
+++ b/drivers/platform/arm64/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for linux/drivers/platform/arm64
+#
+# This dir should only include drivers for EC-like devices.
+#
--
2.44.0

652
device/community/linux-postmarketos-qcom-sc7180/0009-platform-arm64-Add-Acer-Aspire-1-embedded-controller.patch
View file

@ -1,652 +0,0 @@
From 309a0174fb1000b308271bd0009d1cfba263f939 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Sat, 9 Jul 2022 00:39:42 +0500
Subject: [PATCH 09/11] platform: arm64: Add Acer Aspire 1 embedded controller
driver
Acer Aspire 1 is a Snapdragon 7c based laptop. It uses an embedded
controller to perform a set of various functions, such as:
- Battery and charger monitoring;
- Keyboard layout control (i.e. fn_lock settings);
- USB Type-C DP alt mode HPD notifications;
- Laptop lid status.
Unfortunately, while all this functionality is implemented in ACPI, it's
currently not possible to use ACPI to boot Linux on such Qualcomm
devices. To allow Linux to still support the features provided by EC,
this driver reimplments the relevant ACPI parts. This allows us to boot
the laptop with Device Tree and retain all the features.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
---
MAINTAINERS | 6 +
drivers/platform/arm64/Kconfig | 16 +
drivers/platform/arm64/Makefile | 2 +
drivers/platform/arm64/acer-aspire1-ec.c | 561 +++++++++++++++++++++++
4 files changed, 585 insertions(+)
create mode 100644 drivers/platform/arm64/acer-aspire1-ec.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 396be95d4f9a..bc5620bfbb32 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -261,6 +261,12 @@ L: linux-acenic@sunsite.dk
S: Maintained
F: drivers/net/ethernet/alteon/acenic*
+ACER ASPIRE 1 EMBEDDED CONTROLLER DRIVER
+M: Nikita Travkin <nikita@trvn.ru>
+S: Maintained
+F: Documentation/devicetree/bindings/platform/acer,aspire1-ec.yaml
+F: drivers/platform/arm64/acer-aspire1-ec.c
+
ACER ASPIRE ONE TEMPERATURE AND FAN DRIVER
M: Peter Kaestle <peter@piie.net>
L: platform-driver-x86@vger.kernel.org
diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig
index 644b83ede093..07d47879a9e3 100644
--- a/drivers/platform/arm64/Kconfig
+++ b/drivers/platform/arm64/Kconfig
@@ -16,4 +16,20 @@ menuconfig ARM64_PLATFORM_DEVICES
if ARM64_PLATFORM_DEVICES
+config EC_ACER_ASPIRE1
+ tristate "Acer Aspire 1 Emedded Controller driver"
+ depends on I2C
+ depends on DRM
+ depends on POWER_SUPPLY
+ depends on INPUT
+ help
+ Say Y here to enable the EC driver for the (Snapdragon-based)
+ Acer Aspire 1 laptop. The EC handles battery and charging
+ monitoring as well as some misc functions like the lid sensor
+ and USB Type-C DP HPD events.
+
+ This driver provides battery and AC status support for the mentioned
+ laptop where this information is not properly exposed via the
+ standard ACPI devices.
+
endif # ARM64_PLATFORM_DEVICES
diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makefile
index f91cdc7155e2..4fcc9855579b 100644
--- a/drivers/platform/arm64/Makefile
+++ b/drivers/platform/arm64/Makefile
@@ -4,3 +4,5 @@
#
# This dir should only include drivers for EC-like devices.
#
+
+obj-$(CONFIG_EC_ACER_ASPIRE1) += acer-aspire1-ec.o
diff --git a/drivers/platform/arm64/acer-aspire1-ec.c b/drivers/platform/arm64/acer-aspire1-ec.c
new file mode 100644
index 000000000000..75a7c2821771
--- /dev/null
+++ b/drivers/platform/arm64/acer-aspire1-ec.c
@@ -0,0 +1,561 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2024, Nikita Travkin <nikita@trvn.ru> */
+
+#include <asm-generic/unaligned.h>
+#include <drm/drm_bridge.h>
+#include <linux/bits.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+#include <linux/usb/typec_mux.h>
+
+#define MILLI_TO_MICRO 1000
+
+#define ASPIRE_EC_EVENT 0x05
+
+#define ASPIRE_EC_EVENT_WATCHDOG 0x20
+#define ASPIRE_EC_EVENT_KBD_BKL_ON 0x57
+#define ASPIRE_EC_EVENT_KBD_BKL_OFF 0x58
+#define ASPIRE_EC_EVENT_LID_CLOSE 0x9b
+#define ASPIRE_EC_EVENT_LID_OPEN 0x9c
+#define ASPIRE_EC_EVENT_BKL_UNBLANKED 0x9d
+#define ASPIRE_EC_EVENT_BKL_BLANKED 0x9e
+#define ASPIRE_EC_EVENT_FG_INF_CHG 0x85
+#define ASPIRE_EC_EVENT_FG_STA_CHG 0xc6
+#define ASPIRE_EC_EVENT_HPD_DIS 0xa3
+#define ASPIRE_EC_EVENT_HPD_CON 0xa4
+
+#define ASPIRE_EC_FG_DYNAMIC 0x07
+#define ASPIRE_EC_FG_STATIC 0x08
+
+#define ASPIRE_EC_FG_FLAG_PRESENT BIT(0)
+#define ASPIRE_EC_FG_FLAG_FULL BIT(1)
+#define ASPIRE_EC_FG_FLAG_DISCHARGING BIT(2)
+#define ASPIRE_EC_FG_FLAG_CHARGING BIT(3)
+
+#define ASPIRE_EC_RAM_READ 0x20
+#define ASPIRE_EC_RAM_WRITE 0x21
+
+#define ASPIRE_EC_RAM_WATCHDOG 0x19
+#define ASPIRE_EC_WATCHDOG_BIT BIT(6)
+
+#define ASPIRE_EC_RAM_KBD_MODE 0x43
+
+#define ASPIRE_EC_RAM_KBD_FN_EN BIT(0)
+#define ASPIRE_EC_RAM_KBD_MEDIA_ON_TOP BIT(5)
+#define ASPIRE_EC_RAM_KBD_ALWAYS_SET BIT(6)
+#define ASPIRE_EC_RAM_KBD_NUM_LAYER_EN BIT(7)
+
+#define ASPIRE_EC_RAM_KBD_MODE_2 0x60
+
+#define ASPIRE_EC_RAM_KBD_MEDIA_NOTIFY BIT(3)
+
+#define ASPIRE_EC_RAM_HPD_STATUS 0xf4
+#define ASPIRE_EC_HPD_CONNECTED 0x03
+
+#define ASPIRE_EC_RAM_LID_STATUS 0x4c
+#define ASPIRE_EC_LID_OPEN BIT(6)
+
+#define ASPIRE_EC_RAM_ADP 0x40
+#define ASPIRE_EC_AC_STATUS BIT(0)
+
+struct aspire_ec {
+ struct i2c_client *client;
+ struct power_supply *bat_psy;
+ struct power_supply *adp_psy;
+ struct input_dev *idev;
+
+ bool bridge_configured;
+ struct drm_bridge bridge;
+ struct work_struct work;
+};
+
+static int aspire_ec_ram_read(struct i2c_client *client, u8 off, u8 *data, u8 data_len)
+{
+ i2c_smbus_write_byte_data(client, ASPIRE_EC_RAM_READ, off);
+ i2c_smbus_read_i2c_block_data(client, ASPIRE_EC_RAM_READ, data_len, data);
+ return 0;
+}
+
+static int aspire_ec_ram_write(struct i2c_client *client, u8 off, u8 data)
+{
+ u8 tmp[2] = {off, data};
+
+ i2c_smbus_write_i2c_block_data(client, ASPIRE_EC_RAM_WRITE, sizeof(tmp), tmp);
+ return 0;
+}
+
+static irqreturn_t aspire_ec_irq_handler(int irq, void *data)
+{
+ struct aspire_ec *ec = data;
+ int id;
+ u8 tmp;
+
+ /*
+ * The original ACPI firmware actually has a small sleep in the handler.
+ *
+ * It seems like in most cases it's not needed but when the device
+ * just exits suspend, our i2c driver has a brief time where data
+ * transfer is not possible yet. So this delay allows us to suppress
+ * quite a bunch of spurious error messages in dmesg. Thus it's kept.
+ */
+ usleep_range(15000, 30000);
+
+ id = i2c_smbus_read_byte_data(ec->client, ASPIRE_EC_EVENT);
+ if (id < 0) {
+ dev_err(&ec->client->dev, "Failed to read event id: %pe\n", ERR_PTR(id));
+ return IRQ_HANDLED;
+ }
+
+ switch (id) {
+ case 0x0: /* No event */
+ break;
+
+ case ASPIRE_EC_EVENT_WATCHDOG:
+ /*
+ * Here acpi responds to the event and clears some bit.
+ * Notify (\_SB.I2C3.BAT1, 0x81) // Information Change
+ * Notify (\_SB.I2C3.ADP1, 0x80) // Status Change
+ */
+ aspire_ec_ram_read(ec->client, ASPIRE_EC_RAM_WATCHDOG, &tmp, sizeof(tmp));
+ tmp &= ~ASPIRE_EC_WATCHDOG_BIT;
+ aspire_ec_ram_write(ec->client, ASPIRE_EC_RAM_WATCHDOG, tmp);
+ break;
+
+ case ASPIRE_EC_EVENT_LID_CLOSE:
+ /* Notify (\_SB.LID0, 0x80) // Status Change */
+ input_report_switch(ec->idev, SW_LID, 1);
+ input_sync(ec->idev);
+ break;
+
+ case ASPIRE_EC_EVENT_LID_OPEN:
+ /* Notify (\_SB.LID0, 0x80) // Status Change */
+ input_report_switch(ec->idev, SW_LID, 0);
+ input_sync(ec->idev);
+ break;
+
+ case ASPIRE_EC_EVENT_FG_INF_CHG:
+ /* Notify (\_SB.I2C3.BAT1, 0x81) // Information Change */
+ fallthrough;
+ case ASPIRE_EC_EVENT_FG_STA_CHG:
+ /* Notify (\_SB.I2C3.BAT1, 0x80) // Status Change */
+ power_supply_changed(ec->bat_psy);
+ power_supply_changed(ec->adp_psy);
+ break;
+
+ case ASPIRE_EC_EVENT_HPD_DIS:
+ if (ec->bridge_configured)
+ drm_bridge_hpd_notify(&ec->bridge, connector_status_disconnected);
+ break;
+
+ case ASPIRE_EC_EVENT_HPD_CON:
+ if (ec->bridge_configured)
+ drm_bridge_hpd_notify(&ec->bridge, connector_status_connected);
+ break;
+
+ case ASPIRE_EC_EVENT_BKL_BLANKED:
+ case ASPIRE_EC_EVENT_BKL_UNBLANKED:
+ /* Display backlight blanked on FN+F6. No action needed. */
+ break;
+
+ case ASPIRE_EC_EVENT_KBD_BKL_ON:
+ case ASPIRE_EC_EVENT_KBD_BKL_OFF:
+ /*
+ * There is a keyboard backlight connector on Aspire 1 that is
+ * controlled by FN+F8. There is no kb backlight on the device though.
+ * Seems like this is used on other devices like Acer Spin 7.
+ * No action needed.
+ */
+ break;
+
+ default:
+ dev_warn(&ec->client->dev, "Unknown event id=0x%x\n", id);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * Power supply.
+ */
+
+struct aspire_ec_bat_psy_static_data {
+ u8 unk1;
+ u8 flags;
+ __le16 unk2;
+ __le16 voltage_design;
+ __le16 capacity_full;
+ __le16 unk3;
+ __le16 serial;
+ u8 model_id;
+ u8 vendor_id;
+} __packed;
+
+static const char * const aspire_ec_bat_psy_battery_model[] = {
+ "AP18C4K",
+ "AP18C8K",
+ "AP19B8K",
+ "AP16M4J",
+ "AP16M5J",
+};
+
+static const char * const aspire_ec_bat_psy_battery_vendor[] = {
+ "SANYO",
+ "SONY",
+ "PANASONIC",
+ "SAMSUNG",
+ "SIMPLO",
+ "MOTOROLA",
+ "CELXPERT",
+ "LGC",
+ "GETAC",
+ "MURATA",
+};
+
+struct aspire_ec_bat_psy_dynamic_data {
+ u8 unk1;
+ u8 flags;
+ u8 unk2;
+ __le16 capacity_now;
+ __le16 voltage_now;
+ __le16 current_now;
+ __le16 unk3;
+ __le16 unk4;
+} __packed;
+
+static int aspire_ec_bat_psy_get_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ union power_supply_propval *val)
+{
+ struct aspire_ec *ec = power_supply_get_drvdata(psy);
+ struct aspire_ec_bat_psy_static_data sdat;
+ struct aspire_ec_bat_psy_dynamic_data ddat;
+ int str_index = 0;
+
+ i2c_smbus_read_i2c_block_data(ec->client, ASPIRE_EC_FG_STATIC, sizeof(sdat), (u8 *)&sdat);
+ i2c_smbus_read_i2c_block_data(ec->client, ASPIRE_EC_FG_DYNAMIC, sizeof(ddat), (u8 *)&ddat);
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_STATUS:
+ val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
+ if (ddat.flags & ASPIRE_EC_FG_FLAG_CHARGING)
+ val->intval = POWER_SUPPLY_STATUS_CHARGING;
+ else if (ddat.flags & ASPIRE_EC_FG_FLAG_DISCHARGING)
+ val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
+ else if (ddat.flags & ASPIRE_EC_FG_FLAG_FULL)
+ val->intval = POWER_SUPPLY_STATUS_FULL;
+ break;
+
+ case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+ val->intval = get_unaligned_le16(&ddat.voltage_now) * MILLI_TO_MICRO;
+ break;
+
+ case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+ val->intval = le16_to_cpu(sdat.voltage_design) * MILLI_TO_MICRO;
+ break;
+
+ case POWER_SUPPLY_PROP_CHARGE_NOW:
+ val->intval = get_unaligned_le16(&ddat.capacity_now) * MILLI_TO_MICRO;
+ break;
+
+ case POWER_SUPPLY_PROP_CHARGE_FULL:
+ val->intval = le16_to_cpu(sdat.capacity_full) * MILLI_TO_MICRO;
+ break;
+
+ case POWER_SUPPLY_PROP_CAPACITY:
+ val->intval = get_unaligned_le16(&ddat.capacity_now) * 100;
+ val->intval /= le16_to_cpu(sdat.capacity_full);
+ break;
+
+ case POWER_SUPPLY_PROP_CURRENT_NOW:
+ val->intval = (s16)get_unaligned_le16(&ddat.current_now) * MILLI_TO_MICRO;
+ break;
+
+ case POWER_SUPPLY_PROP_PRESENT:
+ val->intval = !!(ddat.flags & ASPIRE_EC_FG_FLAG_PRESENT);
+ break;
+
+ case POWER_SUPPLY_PROP_SCOPE:
+ val->intval = POWER_SUPPLY_SCOPE_SYSTEM;
+ break;
+
+ case POWER_SUPPLY_PROP_MODEL_NAME:
+ str_index = sdat.model_id - 1;
+
+ if (str_index >= 0 && str_index < ARRAY_SIZE(aspire_ec_bat_psy_battery_model))
+ val->strval = aspire_ec_bat_psy_battery_model[str_index];
+ else
+ val->strval = "Unknown";
+ break;
+
+ case POWER_SUPPLY_PROP_MANUFACTURER:
+ str_index = sdat.vendor_id - 3; /* ACPI uses 3 as an offset here. */
+
+ if (str_index >= 0 && str_index < ARRAY_SIZE(aspire_ec_bat_psy_battery_vendor))
+ val->strval = aspire_ec_bat_psy_battery_vendor[str_index];
+ else
+ val->strval = "Unknown";
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static enum power_supply_property aspire_ec_bat_psy_props[] = {
+ POWER_SUPPLY_PROP_STATUS,
+ POWER_SUPPLY_PROP_VOLTAGE_NOW,
+ POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+ POWER_SUPPLY_PROP_CHARGE_NOW,
+ POWER_SUPPLY_PROP_CHARGE_FULL,
+ POWER_SUPPLY_PROP_CAPACITY,
+ POWER_SUPPLY_PROP_CURRENT_NOW,
+ POWER_SUPPLY_PROP_PRESENT,
+ POWER_SUPPLY_PROP_SCOPE,
+ POWER_SUPPLY_PROP_MODEL_NAME,
+ POWER_SUPPLY_PROP_MANUFACTURER,
+};
+
+static const struct power_supply_desc aspire_ec_bat_psy_desc = {
+ .name = "aspire-ec-bat",
+ .type = POWER_SUPPLY_TYPE_BATTERY,
+ .get_property = aspire_ec_bat_psy_get_property,
+ .properties = aspire_ec_bat_psy_props,
+ .num_properties = ARRAY_SIZE(aspire_ec_bat_psy_props),
+};
+
+static int aspire_ec_adp_psy_get_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ union power_supply_propval *val)
+{
+ struct aspire_ec *ec = power_supply_get_drvdata(psy);
+ u8 tmp;
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_ONLINE:
+ aspire_ec_ram_read(ec->client, ASPIRE_EC_RAM_ADP, &tmp, sizeof(tmp));
+ val->intval = !!(tmp & ASPIRE_EC_AC_STATUS);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static enum power_supply_property aspire_ec_adp_psy_props[] = {
+ POWER_SUPPLY_PROP_ONLINE,
+};
+
+static const struct power_supply_desc aspire_ec_adp_psy_desc = {
+ .name = "aspire-ec-adp",
+ .type = POWER_SUPPLY_TYPE_MAINS,
+ .get_property = aspire_ec_adp_psy_get_property,
+ .properties = aspire_ec_adp_psy_props,
+ .num_properties = ARRAY_SIZE(aspire_ec_adp_psy_props),
+};
+
+/*
+ * USB-C DP Alt mode HPD.
+ */
+
+static int aspire_ec_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)
+{
+ return flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR ? 0 : -EINVAL;
+}
+
+static void aspire_ec_bridge_update_hpd_work(struct work_struct *work)
+{
+ struct aspire_ec *ec = container_of(work, struct aspire_ec, work);
+ u8 tmp;
+
+ aspire_ec_ram_read(ec->client, ASPIRE_EC_RAM_HPD_STATUS, &tmp, sizeof(tmp));
+ if (tmp == ASPIRE_EC_HPD_CONNECTED)
+ drm_bridge_hpd_notify(&ec->bridge, connector_status_connected);
+ else
+ drm_bridge_hpd_notify(&ec->bridge, connector_status_disconnected);
+}
+
+static void aspire_ec_bridge_hpd_enable(struct drm_bridge *bridge)
+{
+ struct aspire_ec *ec = container_of(bridge, struct aspire_ec, bridge);
+
+ schedule_work(&ec->work);
+}
+
+static const struct drm_bridge_funcs aspire_ec_bridge_funcs = {
+ .hpd_enable = aspire_ec_bridge_hpd_enable,
+ .attach = aspire_ec_bridge_attach,
+};
+
+/*
+ * Sysfs attributes.
+ */
+
+static ssize_t fn_lock_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct aspire_ec *ec = i2c_get_clientdata(to_i2c_client(dev));
+ u8 tmp;
+
+ aspire_ec_ram_read(ec->client, ASPIRE_EC_RAM_KBD_MODE, &tmp, sizeof(tmp));
+
+ return sysfs_emit(buf, "%u\n", !(tmp & ASPIRE_EC_RAM_KBD_MEDIA_ON_TOP));
+}
+
+static ssize_t fn_lock_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct aspire_ec *ec = i2c_get_clientdata(to_i2c_client(dev));
+ u8 tmp;
+
+ bool state;
+ int ret;
+
+ ret = kstrtobool(buf, &state);
+ if (ret)
+ return ret;
+
+ aspire_ec_ram_read(ec->client, ASPIRE_EC_RAM_KBD_MODE, &tmp, sizeof(tmp));
+
+ if (state)
+ tmp &= ~ASPIRE_EC_RAM_KBD_MEDIA_ON_TOP;
+ else
+ tmp |= ASPIRE_EC_RAM_KBD_MEDIA_ON_TOP;
+
+ aspire_ec_ram_write(ec->client, ASPIRE_EC_RAM_KBD_MODE, tmp);
+
+ return count;
+}
+
+static DEVICE_ATTR_RW(fn_lock);
+
+static struct attribute *aspire_ec_attrs[] = {
+ &dev_attr_fn_lock.attr,
+ NULL
+};
+ATTRIBUTE_GROUPS(aspire_ec);
+
+static int aspire_ec_probe(struct i2c_client *client)
+{
+ struct power_supply_config psy_cfg = {0};
+ struct device *dev = &client->dev;
+ struct fwnode_handle *fwnode;
+ struct aspire_ec *ec;
+ int ret;
+ u8 tmp;
+
+ ec = devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL);
+ if (!ec)
+ return -ENOMEM;
+
+ ec->client = client;
+ i2c_set_clientdata(client, ec);
+
+ /* Battery status reports */
+ psy_cfg.drv_data = ec;
+ ec->bat_psy = devm_power_supply_register(dev, &aspire_ec_bat_psy_desc, &psy_cfg);
+ if (IS_ERR(ec->bat_psy))
+ return dev_err_probe(dev, PTR_ERR(ec->bat_psy),
+ "Failed to register battery power supply\n");
+
+ ec->adp_psy = devm_power_supply_register(dev, &aspire_ec_adp_psy_desc, &psy_cfg);
+ if (IS_ERR(ec->adp_psy))
+ return dev_err_probe(dev, PTR_ERR(ec->adp_psy),
+ "Failed to register AC power supply\n");
+
+ /* Lid switch */
+ ec->idev = devm_input_allocate_device(dev);
+ if (!ec->idev)
+ return -ENOMEM;
+
+ ec->idev->name = "aspire-ec";
+ ec->idev->phys = "aspire-ec/input0";
+ input_set_capability(ec->idev, EV_SW, SW_LID);
+
+ ret = input_register_device(ec->idev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Input device register failed\n");
+
+ /* Enable the keyboard fn keys */
+ tmp = ASPIRE_EC_RAM_KBD_FN_EN | ASPIRE_EC_RAM_KBD_ALWAYS_SET;
+ tmp |= ASPIRE_EC_RAM_KBD_MEDIA_ON_TOP;
+ aspire_ec_ram_write(client, ASPIRE_EC_RAM_KBD_MODE, tmp);
+
+ aspire_ec_ram_read(client, ASPIRE_EC_RAM_KBD_MODE_2, &tmp, sizeof(tmp));
+ tmp |= ASPIRE_EC_RAM_KBD_MEDIA_NOTIFY;
+ aspire_ec_ram_write(client, ASPIRE_EC_RAM_KBD_MODE_2, tmp);
+
+ /* External Type-C display attach reports */
+ fwnode = device_get_named_child_node(dev, "connector");
+ if (fwnode) {
+ INIT_WORK(&ec->work, aspire_ec_bridge_update_hpd_work);
+ ec->bridge.funcs = &aspire_ec_bridge_funcs;
+ ec->bridge.of_node = to_of_node(fwnode);
+ ec->bridge.ops = DRM_BRIDGE_OP_HPD;
+ ec->bridge.type = DRM_MODE_CONNECTOR_USB;
+
+ ret = devm_drm_bridge_add(dev, &ec->bridge);
+ if (ret) {
+ fwnode_handle_put(fwnode);
+ return dev_err_probe(dev, ret, "Failed to register drm bridge\n");
+ }
+
+ ec->bridge_configured = true;
+ }
+
+ ret = devm_request_threaded_irq(dev, client->irq, NULL,
+ aspire_ec_irq_handler, IRQF_ONESHOT,
+ dev_name(dev), ec);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to request irq\n");
+
+ return 0;
+}
+
+static int aspire_ec_resume(struct device *dev)
+{
+ struct aspire_ec *ec = i2c_get_clientdata(to_i2c_client(dev));
+ u8 tmp;
+
+ aspire_ec_ram_read(ec->client, ASPIRE_EC_RAM_LID_STATUS, &tmp, sizeof(tmp));
+ input_report_switch(ec->idev, SW_LID, !!(tmp & ASPIRE_EC_LID_OPEN));
+ input_sync(ec->idev);
+
+ return 0;
+}
+
+static const struct i2c_device_id aspire_ec_id[] = {
+ { "aspire1-ec", },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, aspire_ec_id);
+
+static const struct of_device_id aspire_ec_of_match[] = {
+ { .compatible = "acer,aspire1-ec", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, aspire_ec_of_match);
+
+static DEFINE_SIMPLE_DEV_PM_OPS(aspire_ec_pm_ops, NULL, aspire_ec_resume);
+
+static struct i2c_driver aspire_ec_driver = {
+ .driver = {
+ .name = "aspire-ec",
+ .of_match_table = aspire_ec_of_match,
+ .pm = pm_sleep_ptr(&aspire_ec_pm_ops),
+ .dev_groups = aspire_ec_groups,
+ },
+ .probe = aspire_ec_probe,
+ .id_table = aspire_ec_id,
+};
+module_i2c_driver(aspire_ec_driver);
+
+MODULE_DESCRIPTION("Acer Aspire 1 embedded controller");
+MODULE_AUTHOR("Nikita Travkin <nikita@trvn.ru>");
+MODULE_LICENSE("GPL");
--
2.44.0

94
device/community/linux-postmarketos-qcom-sc7180/0010-arm64-dts-qcom-acer-aspire1-Add-embedded-controller.patch
View file

@ -1,94 +0,0 @@
From 2379590f43baff3f0e80326f25df21cc98e8ae11 Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Sat, 9 Jul 2022 00:40:27 +0500
Subject: [PATCH 10/11] arm64: dts: qcom: acer-aspire1: Add embedded controller
The laptop contains an embedded controller that provides a set of
features:
- Battery and charger monitoring
- USB Type-C DP alt mode HPD monitoring
- Lid status detection
- Small amount of keyboard configuration*
[*] The keyboard is handled by the same EC but it has a dedicated i2c
bus and is already enabled. This port only provides fn key behavior
configuration.
Add the EC to the device tree and describe the relationship between the
EC-managed type-c port and the SoC DisplayPort.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
---
.../boot/dts/qcom/sc7180-acer-aspire1.dts | 40 ++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
index 5afcb8212f49..3f0d3e33894a 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
@@ -255,7 +255,25 @@ &i2c2 {
clock-frequency = <400000>;
status = "okay";
- /* embedded-controller@76 */
+ embedded-controller@76 {
+ compatible = "acer,aspire1-ec";
+ reg = <0x76>;
+
+ interrupts-extended = <&tlmm 30 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&ec_int_default>;
+ pinctrl-names = "default";
+
+ connector {
+ compatible = "usb-c-connector";
+
+ port {
+ ec_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp_out>;
+ };
+ };
+ };
+ };
};
&i2c4 {
@@ -419,6 +437,19 @@ &mdss {
status = "okay";
};
+&mdss_dp {
+ data-lanes = <0 1>;
+
+ vdda-1p2-supply = <&vreg_l3c_1p2>;
+ vdda-0p9-supply = <&vreg_l4a_0p8>;
+
+ status = "okay";
+};
+
+&mdss_dp_out {
+ remote-endpoint = <&ec_dp_in>;
+};
+
&mdss_dsi0 {
vdda-supply = <&vreg_l3c_1p2>;
status = "okay";
@@ -857,6 +888,13 @@ codec_irq_default: codec-irq-deault-state {
bias-disable;
};
+ ec_int_default: ec-int-default-state {
+ pins = "gpio30";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
edp_bridge_irq_default: edp-bridge-irq-default-state {
pins = "gpio11";
function = "gpio";
--
2.44.0

78
device/community/linux-postmarketos-qcom-sc7180/0011-HACK-clk-Delay-disabling-unused-clocks-by-10s.patch
View file

@ -1,78 +0,0 @@
From c3fccf1615be6548b50274851557f579b6320b5b Mon Sep 17 00:00:00 2001
From: Nikita Travkin <nikita@trvn.ru>
Date: Mon, 11 Mar 2024 14:53:04 +0500
Subject: [PATCH] HACK: clk: Delay disabling unused clocks by 10s
There is a forever-lasting problem with qcom clocks that causes display
subsystem crash due to "disp_cc_mdss_mdp_clk status stuck at 'off'" if
the clocks were cleaned up before msm claimed this one.
Delay disabling unused clocks by 10 seconds to work around this.
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
---
drivers/clk/clk.c | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 50228cb0c559..f0647ecca9ac 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1347,7 +1347,7 @@ static void clk_core_disable_unprepare(struct clk_core *core)
clk_core_unprepare_lock(core);
}
-static void __init clk_unprepare_unused_subtree(struct clk_core *core)
+static void clk_unprepare_unused_subtree(struct clk_core *core)
{
struct clk_core *child;
@@ -1377,7 +1377,7 @@ static void __init clk_unprepare_unused_subtree(struct clk_core *core)
clk_pm_runtime_put(core);
}
-static void __init clk_disable_unused_subtree(struct clk_core *core)
+static void clk_disable_unused_subtree(struct clk_core *core)
{
struct clk_core *child;
unsigned long flags;
@@ -1431,15 +1431,10 @@ static int __init clk_ignore_unused_setup(char *__unused)
}
__setup("clk_ignore_unused", clk_ignore_unused_setup);
-static int __init clk_disable_unused(void)
+static void clk_disable_unused_work_function(struct work_struct *work)
{
struct clk_core *core;
- if (clk_ignore_unused) {
- pr_warn("clk: Not disabling unused clocks\n");
- return 0;
- }
-
pr_info("clk: Disabling unused clocks\n");
clk_prepare_lock();
@@ -1457,6 +1452,19 @@ static int __init clk_disable_unused(void)
clk_unprepare_unused_subtree(core);
clk_prepare_unlock();
+}
+static DECLARE_DELAYED_WORK(clk_disable_unused_work,
+ clk_disable_unused_work_function);
+
+static int __init clk_disable_unused(void)
+{
+ if (clk_ignore_unused) {
+ pr_warn("clk: Not disabling unused clocks\n");
+ return 0;
+ }
+
+ schedule_delayed_work(&clk_disable_unused_work,
+ msecs_to_jiffies(10000));
return 0;
}
--
2.44.0

33
device/community/linux-postmarketos-qcom-sc7180/APKBUILD
View file

@ -1,7 +1,7 @@
# Maintainer: Jenneron <jenneron@protonmail.com>
# Maintainer: Alicja Michalska <alicja.michalska@9elements.com>
pkgname=linux-postmarketos-qcom-sc7180
pkgver=6.6.28
pkgrel=8
pkgver=6.12.35
pkgrel=9
pkgdesc="Mainline kernel fork for Qualcomm Snapdragon 7c devices"
arch="aarch64"
_carch="arm64"
@ -25,6 +25,7 @@ makedepends="
mpfr-dev
postmarketos-installkernel
xz
python3
"
# Source
@ -35,17 +36,6 @@ case $pkgver in
esac
source="
https://cdn.kernel.org/pub/linux/kernel/v${_kernver%%.*}.x/linux-${pkgver//_/-}.tar.xz
0001-remoteproc-qcom-pas-Add-sc7180-adsp.patch
0002-arm64-dts-qcom-sc7180-Add-tertiary-mi2s-pinctrl.patch
0003-arm64-dts-qcom-sc7180-Add-ADSP.patch
0004-ASoC-qcom-sc7180-Add-support-for-qdsp6-baked-sound.patch
0005-arm64-dts-qcom-pm6150-Add-resin-and-rtc-nodes.patch
0006-arm64-dts-qcom-acer-aspire1-Enable-RTC.patch
0007-arm64-dts-qcom-acer-aspire1-Add-sound.patch
0008-platform-Add-ARM64-platform-directory.patch
0009-platform-arm64-Add-Acer-Aspire-1-embedded-controller.patch
0010-arm64-dts-qcom-acer-aspire1-Add-embedded-controller.patch
0011-HACK-clk-Delay-disabling-unused-clocks-by-10s.patch
$_config
"
builddir="$srcdir/linux-${_kernver//_/-}"
@ -89,17 +79,6 @@ package() {
}
sha512sums="
fdf6def06de85656f8aa010edfb8b2f7f71cdeef9a70b5b35511833fbcf0e4fbfafb6224acfdf475975bc4bc8f05d0291745af5a6ae752a70cbd09ae2d3d17a8 linux-6.6.28.tar.xz
ac68e3e441c90ebc88d75cabcbb54d836256876932689f74a4d492a19c5aab9e207930ff14ba24f2298af44f662616ef34c9b8147a7ebada2db9c11eab55f3f2 0001-remoteproc-qcom-pas-Add-sc7180-adsp.patch
8f8aad35c408b2c29a8ddd2bc71c8542bef73e9b386c010257004e67bccf82fc1ffe9ca8df0b12d6930a776fdb288a365ddceb7d4bbc7031777bef6fdf3534a1 0002-arm64-dts-qcom-sc7180-Add-tertiary-mi2s-pinctrl.patch
a4d8bbf39575e61d228b3b66fa692b207c1ee011e6030fdd097936a1ad28b1d5b01816d989adcb809d05f107aaf9024ccd077e6daa9c65aa2ff23907ee1f0566 0003-arm64-dts-qcom-sc7180-Add-ADSP.patch
30130ae6e49bc0386fd7b34e69961e208806673b2bf2b7bb9abe428766013116baa924536346bceee60db886565c7e2f9c48c8ba2e691381aae544df730b780a 0004-ASoC-qcom-sc7180-Add-support-for-qdsp6-baked-sound.patch
80479f5b598628f48302aa4c224f173cbe02ebb6a9e14a555b9bf06163a40442cdc8e77c7a6e14684a21df0e61627cfa3345cef385d6d3e11c1d412cc924d85a 0005-arm64-dts-qcom-pm6150-Add-resin-and-rtc-nodes.patch
6628e979e9ba579ff3f259f8d2917318342f4cc855a06ac70dc2a81bf3c9e3a6729b1ebee28591db1374afc7a0aabbbf2f2e8b915c735f070528f6ddfd905631 0006-arm64-dts-qcom-acer-aspire1-Enable-RTC.patch
9200a97d795d97e42e89af9cb47fc750ef2784d883327b6e8ca0ad77634c8af20b531f8917c3584c369fd2f36142cea73f51d416e78a99e80c48ae99165bdf18 0007-arm64-dts-qcom-acer-aspire1-Add-sound.patch
1cc7105a6b4aa112f8203416a11cda56a39dfa957679021f7bf38f9503eab51c99cb53aed391cb7cb6ec853b705f0d5032ea5932f8c342152aca916681b507d3 0008-platform-Add-ARM64-platform-directory.patch
08c6cace24a207f4a64a85b17e97646f62a8590b502cd5b6945489d0aeded352e21f0e1b0ec541ae2e61ec7fd4f6bc1e5bf1d5d32f2c6616eb41d39d66f0bab5 0009-platform-arm64-Add-Acer-Aspire-1-embedded-controller.patch
69cfb699990ea7994089016b29cc248cb03483ad3f7620cbba63a779b2ed8928e6fde68484d29b6b8dfd1a8a6fa8d84c441f30180c7a257520ced442dab33876 0010-arm64-dts-qcom-acer-aspire1-Add-embedded-controller.patch
c5edcd74f898b08bc663766668632d351aea40426b3563d53a4b8c6856dd82627f4794d60450e41171c990ebb3649056b36ef432c14c8783168e8060a2e3b094 0011-HACK-clk-Delay-disabling-unused-clocks-by-10s.patch
8a8d4c8c50bd5eba07cf8e0b9a3d7759d8a3ca2c0fb2ecc91e35c93e570bf4184999c73f414c3a9a1bfcc8b6e9dc6fa6ba70de0421e492c77ab6d458df3bffaa config-postmarketos-qcom-sc7180.aarch64
3697bf2c9525c8d11f7e821fa080d8c366ae751af02b471a506224002abe6b23b0ccf17d9694c7590c1b07002289eb19003ba8677bbb0bb09d54458495964188 linux-6.12.35.tar.xz
e5a8b89769f00a5802760aaefbdbe85a91967be74e6911617ccfcf515bac88b1014bcecb8903ce792bee85e4da902126ec5617168f87eb8f899c75b80378eab4 config-postmarketos-qcom-sc7180.aarch64
"

627
device/community/linux-postmarketos-qcom-sc7180/config-postmarketos-qcom-sc7180.aarch64
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