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include: linux: Update kernel headers to version v5.19

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Update kernel headers to v5.19 using utils/update-kernel-headers.sh and
re-instating libcamera local modifications.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Jacopo Mondi <jacopo@jmondi.org>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
This commit is contained in:
Laurent Pinchart 2022-08-01 01:14:48 +03:00
parent 2e77ccbb93
commit 37e85ff1dd
6 changed files with 418 additions and 23 deletions
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86
include/linux/drm_fourcc.h
View file

@ -314,6 +314,13 @@ extern "C" {
*/
#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
/* 2 plane YCbCr420.
* 3 10 bit components and 2 padding bits packed into 4 bytes.
* index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
* index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
*/
#define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
/* 3 plane non-subsampled (444) YCbCr
* 16 bits per component, but only 10 bits are used and 6 bits are padded
* index 0: Y plane, [15:0] Y:x [10:6] little endian
@ -630,6 +637,53 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
/*
* Intel Tile 4 layout
*
* This is a tiled layout using 4KB tiles in a row-major layout. It has the same
* shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
* only differs from Tile Y at the 256B granularity in between. At this
* granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
* of 64B x 8 rows.
*/
#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
/*
* Intel color control surfaces (CCS) for DG2 render compression.
*
* The main surface is Tile 4 and at plane index 0. The CCS data is stored
* outside of the GEM object in a reserved memory area dedicated for the
* storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
* main surface pitch is required to be a multiple of four Tile 4 widths.
*/
#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
/*
* Intel color control surfaces (CCS) for DG2 media compression.
*
* The main surface is Tile 4 and at plane index 0. For semi-planar formats
* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
* 0 and 1, respectively. The CCS for all planes are stored outside of the
* GEM object in a reserved memory area dedicated for the storage of the
* CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
* pitch is required to be a multiple of four Tile 4 widths.
*/
#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
/*
* Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
*
* The main surface is Tile 4 and at plane index 0. The CCS data is stored
* outside of the GEM object in a reserved memory area dedicated for the
* storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
* main surface pitch is required to be a multiple of four Tile 4 widths. The
* clear color is stored at plane index 1 and the pitch should be ignored. The
* format of the 256 bits of clear color data matches the one used for the
* I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
* for details.
*/
#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
/*
* IPU3 Bayer packing layout
*
@ -638,7 +692,7 @@ extern "C" {
* the 6 most significant bits in the last byte unused. The format is little
* endian.
*/
#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 9)
#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 13)
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
@ -677,6 +731,28 @@ extern "C" {
*/
#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
/*
* Qualcomm Tiled Format
*
* Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed.
* Implementation may be platform and base-format specific.
*
* Each macrotile consists of m x n (mostly 4 x 4) tiles.
* Pixel data pitch/stride is aligned with macrotile width.
* Pixel data height is aligned with macrotile height.
* Entire pixel data buffer is aligned with 4k(bytes).
*/
#define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3)
/*
* Qualcomm Alternate Tiled Format
*
* Alternate tiled format typically only used within GMEM.
* Implementation may be platform and base-format specific.
*/
#define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2)
/* Vivante framebuffer modifiers */
/*
@ -929,6 +1005,10 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
* and UV. Some SAND-using hardware stores UV in a separate tiled
* image from Y to reduce the column height, which is not supported
* with these modifiers.
*
* The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
* supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
* wide, but as this is a 10 bpp format that translates to 96 pixels.
*/
#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
@ -1439,11 +1519,11 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
#define AMD_FMT_MOD_PIPE_MASK 0x7
#define AMD_FMT_MOD_SET(field, value) \
((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT)
#define AMD_FMT_MOD_GET(field, value) \
(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
#define AMD_FMT_MOD_CLEAR(field) \
(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
(~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
/* Mobile Industry Processor Interface (MIPI) modifiers */